Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T9,T4,T6

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	161000762	158611447	0	0
AllClkBypReqTrue_A	161000762	123406	0	0
IoClkBypReqFalse_A	161000762	158528301	0	2415
IoClkBypReqTrue_A	161000762	201770	0	0
LcClkBypAckFalse_A	161000762	158616940	0	0
LcClkBypAckTrue_A	161000762	117913	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161000762	158611447	0	0
T4	36388	2915	0	0
T5	176664	176541	0	0
T7	1078	1040	0	0
T8	2550	2139	0	0
T9	15877	14994	0	0
T27	1105	1078	0	0
T28	1442	1294	0	0
T29	1120	1086	0	0
T30	1939	1922	0	0
T31	1946	1922	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161000762	123406	0	0
T4	36388	0	0	0
T5	176664	0	0	0
T6	40336	378	0	0
T8	2550	274	0	0
T9	15877	203	0	0
T12	0	1475	0	0
T19	0	160	0	0
T22	0	158	0	0
T25	0	154	0	0
T27	1105	0	0	0
T28	1442	0	0	0
T29	1120	0	0	0
T30	1939	0	0	0
T31	1946	0	0	0
T82	0	47	0	0
T85	0	237	0	0
T86	0	112	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161000762	158528301	0	2415
T4	36388	2889	0	3
T5	176664	176539	0	3
T7	1078	977	0	3
T8	2550	1951	0	3
T9	15877	14954	0	3
T27	1105	1076	0	3
T28	1442	1292	0	3
T29	1120	1032	0	3
T30	1939	1920	0	3
T31	1946	1920	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161000762	201770	0	0
T4	36388	0	0	0
T5	176664	0	0	0
T6	0	464	0	0
T7	1078	61	0	0
T8	2550	460	0	0
T9	15877	231	0	0
T19	0	211	0	0
T20	0	151	0	0
T22	0	319	0	0
T25	0	254	0	0
T27	1105	0	0	0
T28	1442	0	0	0
T29	1120	52	0	0
T30	1939	0	0	0
T31	1946	0	0	0
T85	0	31	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161000762	158616940	0	0
T4	36388	2915	0	0
T5	176664	176541	0	0
T7	1078	1021	0	0
T8	2550	2197	0	0
T9	15877	15059	0	0
T27	1105	1078	0	0
T28	1442	1294	0	0
T29	1120	1084	0	0
T30	1939	1922	0	0
T31	1946	1922	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161000762	117913	0	0
T4	36388	0	0	0
T5	176664	0	0	0
T6	0	350	0	0
T7	1078	19	0	0
T8	2550	216	0	0
T9	15877	138	0	0
T19	0	40	0	0
T20	0	71	0	0
T22	0	198	0	0
T25	0	176	0	0
T27	1105	0	0	0
T28	1442	0	0	0
T29	1120	2	0	0
T30	1939	0	0	0
T31	1946	0	0	0
T85	0	27	0	0