Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16228	0	0
TransStop_A	2147483647	8305	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16228	0	0
T1	800744	0	0	0
T2	0	19	0	0
T4	316420	0	0	0
T5	728492	0	0	0
T6	350744	132	0	0
T9	88216	60	0	0
T12	0	397	0	0
T13	0	73	0	0
T14	0	34	0	0
T22	0	14	0	0
T24	0	17	0	0
T27	18436	5	0	0
T28	6068	0	0	0
T29	18688	0	0	0
T30	96988	35	0	0
T31	32448	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8305	0	0
T1	800744	0	0	0
T2	0	10	0	0
T4	316420	0	0	0
T5	728492	0	0	0
T6	350744	81	0	0
T9	88216	30	0	0
T12	0	217	0	0
T13	0	45	0	0
T14	0	80	0	0
T16	0	39	0	0
T22	0	11	0	0
T24	0	6	0	0
T27	18436	0	0	0
T28	6068	0	0	0
T29	18688	0	0	0
T30	96988	17	0	0
T31	32448	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	634227977	4084	0	0
TransStop_A	634227977	2097	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227977	4084	0	0
T1	200186	0	0	0
T2	0	5	0	0
T4	79105	0	0	0
T5	182123	0	0	0
T6	87686	31	0	0
T9	22054	14	0	0
T12	0	101	0	0
T13	0	19	0	0
T22	0	4	0	0
T24	0	7	0	0
T27	4609	2	0	0
T28	1517	0	0	0
T29	4672	0	0	0
T30	24247	8	0	0
T31	8112	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227977	2097	0	0
T1	200186	0	0	0
T2	0	3	0	0
T4	79105	0	0	0
T5	182123	0	0	0
T6	87686	18	0	0
T9	22054	6	0	0
T12	0	59	0	0
T13	0	14	0	0
T14	0	21	0	0
T22	0	3	0	0
T24	0	3	0	0
T27	4609	0	0	0
T28	1517	0	0	0
T29	4672	0	0	0
T30	24247	3	0	0
T31	8112	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	634227977	4106	0	0
TransStop_A	634227977	2108	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227977	4106	0	0
T1	200186	0	0	0
T2	0	4	0	0
T4	79105	0	0	0
T5	182123	0	0	0
T6	87686	33	0	0
T9	22054	12	0	0
T12	0	100	0	0
T13	0	22	0	0
T22	0	2	0	0
T24	0	5	0	0
T27	4609	1	0	0
T28	1517	0	0	0
T29	4672	0	0	0
T30	24247	9	0	0
T31	8112	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227977	2108	0	0
T1	200186	0	0	0
T2	0	2	0	0
T4	79105	0	0	0
T5	182123	0	0	0
T6	87686	20	0	0
T9	22054	6	0	0
T12	0	53	0	0
T13	0	13	0	0
T14	0	25	0	0
T22	0	1	0	0
T24	0	2	0	0
T27	4609	0	0	0
T28	1517	0	0	0
T29	4672	0	0	0
T30	24247	5	0	0
T31	8112	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	634227977	4012	0	0
TransStop_A	634227977	2016	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227977	4012	0	0
T1	200186	0	0	0
T2	0	4	0	0
T4	79105	0	0	0
T5	182123	0	0	0
T6	87686	32	0	0
T9	22054	18	0	0
T12	0	104	0	0
T13	0	13	0	0
T14	0	34	0	0
T22	0	4	0	0
T24	0	3	0	0
T27	4609	0	0	0
T28	1517	0	0	0
T29	4672	0	0	0
T30	24247	9	0	0
T31	8112	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227977	2016	0	0
T1	200186	0	0	0
T2	0	2	0	0
T4	79105	0	0	0
T5	182123	0	0	0
T6	87686	21	0	0
T9	22054	9	0	0
T12	0	58	0	0
T13	0	6	0	0
T14	0	19	0	0
T22	0	4	0	0
T24	0	1	0	0
T27	4609	0	0	0
T28	1517	0	0	0
T29	4672	0	0	0
T30	24247	5	0	0
T31	8112	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	634227977	4026	0	0
TransStop_A	634227977	2084	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227977	4026	0	0
T1	200186	0	0	0
T2	0	6	0	0
T4	79105	0	0	0
T5	182123	0	0	0
T6	87686	36	0	0
T9	22054	16	0	0
T12	0	92	0	0
T13	0	19	0	0
T22	0	4	0	0
T24	0	2	0	0
T27	4609	2	0	0
T28	1517	0	0	0
T29	4672	0	0	0
T30	24247	9	0	0
T31	8112	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227977	2084	0	0
T1	200186	0	0	0
T2	0	3	0	0
T4	79105	0	0	0
T5	182123	0	0	0
T6	87686	22	0	0
T9	22054	9	0	0
T12	0	47	0	0
T13	0	12	0	0
T14	0	15	0	0
T16	0	39	0	0
T22	0	3	0	0
T27	4609	0	0	0
T28	1517	0	0	0
T29	4672	0	0	0
T30	24247	4	0	0
T31	8112	1	0	0