Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	161000762	21624071	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161000762	21624071	0	58
T1	178164	33128	0	1
T2	162016	26738	0	1
T3	0	18173	0	1
T12	0	91089	0	0
T13	0	22452	0	1
T14	0	27843	0	0
T15	0	12782	0	1
T16	0	479050	0	0
T17	0	111035	0	0
T19	1631	0	0	0
T20	1783	0	0	0
T21	38253	0	0	0
T22	5027	0	0	0
T23	18975	0	0	0
T24	1751	0	0	0
T25	2111	0	0	0
T26	43613	0	0	0
T32	0	867	0	1
T33	0	0	0	1
T129	0	0	0	1
T130	0	0	0	1
T131	0	0	0	1