Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	162042127	5398788	0	0
clk_enables_rd_A	162042127	52585	0	0
clk_hints_rd_A	162042127	45935	0	0
extclk_ctrl_rd_A	162042127	56776	0	0
extclk_ctrl_regwen_rd_A	162042127	44407	0	0
jitter_enable_rd_A	162042127	64570	0	0
jitter_regwen_rd_A	162042127	49802	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162042127	5398788	0	0
T12	208161	104484	0	0
T13	130443	0	0	0
T14	150583	74758	0	0
T16	0	235951	0	0
T17	0	112985	0	0
T32	4073	0	0	0
T41	1351	0	0	0
T42	1792	0	0	0
T43	1745	0	0	0
T76	0	18480	0	0
T77	0	140732	0	0
T78	0	57016	0	0
T79	0	209654	0	0
T80	0	38229	0	0
T81	0	118766	0	0
T82	1478	0	0	0
T83	1483	0	0	0
T84	2469	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162042127	52585	0	0
T1	178164	0	0	0
T2	162016	0	0	0
T5	176664	0	0	0
T6	40336	0	0	0
T19	1631	0	0	0
T20	1783	0	0	0
T21	38253	0	0	0
T22	5027	0	0	0
T23	18975	0	0	0
T31	1946	5	0	0
T52	0	2288	0	0
T77	0	5776	0	0
T80	0	788	0	0
T104	0	4	0	0
T152	0	2425	0	0
T153	0	7	0	0
T154	0	9	0	0
T155	0	4	0	0
T156	0	1909	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162042127	45935	0	0
T1	178164	0	0	0
T2	162016	0	0	0
T5	176664	0	0	0
T6	40336	0	0	0
T19	1631	0	0	0
T20	1783	0	0	0
T21	38253	0	0	0
T22	5027	0	0	0
T23	18975	0	0	0
T31	1946	2	0	0
T52	0	2196	0	0
T77	0	4937	0	0
T80	0	797	0	0
T152	0	1876	0	0
T153	0	10	0	0
T154	0	3	0	0
T155	0	3	0	0
T157	0	5	0	0
T158	0	4	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162042127	56776	0	0
T4	36388	0	0	0
T5	176664	0	0	0
T6	40336	0	0	0
T8	2550	47	0	0
T9	15877	0	0	0
T27	1105	0	0	0
T28	1442	0	0	0
T29	1120	21	0	0
T30	1939	0	0	0
T31	1946	0	0	0
T83	0	7	0	0
T85	0	54	0	0
T88	0	58	0	0
T99	0	20	0	0
T103	0	27	0	0
T105	0	22	0	0
T159	0	10	0	0
T160	0	19	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162042127	44407	0	0
T36	1064	0	0	0
T52	0	1859	0	0
T77	0	4894	0	0
T80	0	681	0	0
T88	40262	38	0	0
T96	1944	0	0	0
T97	997	0	0	0
T98	1923	0	0	0
T99	1593	0	0	0
T100	27742	0	0	0
T101	1619	0	0	0
T102	2168	0	0	0
T152	0	1942	0	0
T156	0	1524	0	0
T160	0	14	0	0
T161	0	18	0	0
T162	0	33	0	0
T163	0	5	0	0
T164	2355	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162042127	64570	0	0
T1	178164	0	0	0
T2	162016	0	0	0
T5	176664	0	0	0
T6	40336	0	0	0
T19	1631	0	0	0
T20	1783	0	0	0
T21	38253	0	0	0
T22	5027	0	0	0
T23	18975	0	0	0
T31	1946	128	0	0
T52	0	3785	0	0
T77	0	6228	0	0
T80	0	923	0	0
T104	0	85	0	0
T152	0	2611	0	0
T153	0	182	0	0
T154	0	104	0	0
T155	0	126	0	0
T157	0	57	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162042127	49802	0	0
T40	0	2883	0	0
T52	0	2259	0	0
T77	481021	5277	0	0
T80	0	866	0	0
T152	0	2445	0	0
T156	0	1745	0	0
T165	0	4854	0	0
T166	0	2155	0	0
T167	0	4877	0	0
T168	0	594	0	0
T169	1731	0	0	0
T170	1617	0	0	0
T171	1647	0	0	0
T172	1981	0	0	0
T173	31739	0	0	0
T174	5347	0	0	0
T175	133953	0	0	0
T176	2350	0	0	0
T177	90665	0	0	0