Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T6
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	49293	0	0
CgEnOn_A	2147483647	39729	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49293	0	0
T4	187429	39	0	0
T5	407413	3	0	0
T6	87685	31	0	0
T7	4790	3	0	0
T8	4550	3	0	0
T9	59038	141	0	0
T13	1175210	0	0	0
T14	1324356	5	0	0
T27	12289	5	0	0
T28	4047	23	0	0
T29	12482	3	0	0
T30	64878	11	0	0
T31	21712	7	0	0
T32	54909	0	0	0
T41	3096	24	0	0
T42	3739	30	0	0
T43	3415	20	0	0
T77	0	5	0	0
T83	3234	0	0	0
T84	5472	0	0	0
T87	404734	0	0	0
T98	0	30	0	0
T178	0	10	0	0
T179	0	5	0	0
T180	0	30	0	0
T181	0	20	0	0
T184	13977	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39729	0	0
T1	1233083	0	0	0
T2	0	39	0	0
T4	462712	0	0	0
T5	1032559	0	0	0
T6	497454	34	0	0
T9	135782	123	0	0
T12	0	356	0	0
T13	2262252	114	0	0
T14	2568426	337	0	0
T22	0	7	0	0
T27	28325	2	0	0
T28	9326	20	0	0
T29	28737	0	0	0
T30	149255	8	0	0
T31	49941	4	0	0
T32	105827	0	0	0
T41	6260	36	0	0
T42	7179	30	0	0
T43	6837	20	0	0
T77	0	4	0	0
T83	6230	0	0	0
T84	10410	0	0	0
T87	827544	0	0	0
T98	0	30	0	0
T178	0	10	0	0
T179	0	5	0	0
T180	0	30	0	0
T181	0	20	0	0
T182	0	1	0	0
T184	26133	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T6
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	298180680	154	0	0
CgEnOn_A	298180680	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298180680	154	0	0
T13	261382	0	0	0
T14	294301	1	0	0
T32	12187	0	0	0
T41	679	4	0	0
T42	804	6	0	0
T43	732	4	0	0
T77	0	1	0	0
T83	720	0	0	0
T84	1244	0	0	0
T87	89933	0	0	0
T98	0	6	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	6	0	0
T181	0	4	0	0
T184	3260	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298180680	154	0	0
T13	261382	0	0	0
T14	294301	1	0	0
T32	12187	0	0	0
T41	679	4	0	0
T42	804	6	0	0
T43	732	4	0	0
T77	0	1	0	0
T83	720	0	0	0
T84	1244	0	0	0
T87	89933	0	0	0
T98	0	6	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	6	0	0
T181	0	4	0	0
T184	3260	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T6
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	149089732	154	0	0
CgEnOn_A	149089732	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149089732	154	0	0
T13	130688	0	0	0
T14	147150	1	0	0
T32	6094	0	0	0
T41	340	4	0	0
T42	402	6	0	0
T43	366	4	0	0
T77	0	1	0	0
T83	359	0	0	0
T84	619	0	0	0
T87	44966	0	0	0
T98	0	6	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	6	0	0
T181	0	4	0	0
T184	1628	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149089732	154	0	0
T13	130688	0	0	0
T14	147150	1	0	0
T32	6094	0	0	0
T41	340	4	0	0
T42	402	6	0	0
T43	366	4	0	0
T77	0	1	0	0
T83	359	0	0	0
T84	619	0	0	0
T87	44966	0	0	0
T98	0	6	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	6	0	0
T181	0	4	0	0
T184	1628	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T6
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	597834691	154	0	0
CgEnOn_A	597834691	148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597834691	154	0	0
T13	521764	0	0	0
T14	588605	1	0	0
T32	24440	0	0	0
T41	1397	4	0	0
T42	1729	6	0	0
T43	1585	4	0	0
T77	0	1	0	0
T83	1437	0	0	0
T84	2371	0	0	0
T87	179903	0	0	0
T98	0	6	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	6	0	0
T181	0	4	0	0
T184	5833	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597834691	148	0	0
T13	521764	0	0	0
T14	588605	1	0	0
T32	24440	0	0	0
T41	1397	4	0	0
T42	1729	6	0	0
T43	1585	4	0	0
T83	1437	0	0	0
T84	2371	0	0	0
T87	179903	0	0	0
T98	0	6	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	6	0	0
T181	0	4	0	0
T182	0	1	0	0
T184	5833	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T6
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	634227531	146	0	0
CgEnOn_A	634227531	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227531	146	0	0
T13	543521	0	0	0
T14	622035	0	0	0
T32	25459	0	0	0
T41	1582	4	0	0
T42	1720	4	0	0
T43	1711	4	0	0
T83	1498	0	0	0
T84	2469	0	0	0
T87	211405	0	0	0
T98	0	6	0	0
T178	0	4	0	0
T180	0	6	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	4	0	0
T184	6078	0	0	0
T185	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227531	144	0	0
T13	543521	0	0	0
T14	622035	0	0	0
T32	25459	0	0	0
T41	1582	4	0	0
T42	1720	4	0	0
T43	1711	4	0	0
T83	1498	0	0	0
T84	2469	0	0	0
T87	211405	0	0	0
T98	0	6	0	0
T178	0	4	0	0
T180	0	6	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	4	0	0
T184	6078	0	0	0
T185	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T6
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	149089732	154	0	0
CgEnOn_A	149089732	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149089732	154	0	0
T13	130688	0	0	0
T14	147150	1	0	0
T32	6094	0	0	0
T41	340	4	0	0
T42	402	6	0	0
T43	366	4	0	0
T77	0	1	0	0
T83	359	0	0	0
T84	619	0	0	0
T87	44966	0	0	0
T98	0	6	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	6	0	0
T181	0	4	0	0
T184	1628	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149089732	154	0	0
T13	130688	0	0	0
T14	147150	1	0	0
T32	6094	0	0	0
T41	340	4	0	0
T42	402	6	0	0
T43	366	4	0	0
T77	0	1	0	0
T83	359	0	0	0
T84	619	0	0	0
T87	44966	0	0	0
T98	0	6	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	6	0	0
T181	0	4	0	0
T184	1628	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T6
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	634227531	146	0	0
CgEnOn_A	634227531	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227531	146	0	0
T13	543521	0	0	0
T14	622035	0	0	0
T32	25459	0	0	0
T41	1582	4	0	0
T42	1720	4	0	0
T43	1711	4	0	0
T83	1498	0	0	0
T84	2469	0	0	0
T87	211405	0	0	0
T98	0	6	0	0
T178	0	4	0	0
T180	0	6	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	4	0	0
T184	6078	0	0	0
T185	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227531	144	0	0
T13	543521	0	0	0
T14	622035	0	0	0
T32	25459	0	0	0
T41	1582	4	0	0
T42	1720	4	0	0
T43	1711	4	0	0
T83	1498	0	0	0
T84	2469	0	0	0
T87	211405	0	0	0
T98	0	6	0	0
T178	0	4	0	0
T180	0	6	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	4	0	0
T184	6078	0	0	0
T185	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T6
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	149089732	154	0	0
CgEnOn_A	149089732	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149089732	154	0	0
T13	130688	0	0	0
T14	147150	1	0	0
T32	6094	0	0	0
T41	340	4	0	0
T42	402	6	0	0
T43	366	4	0	0
T77	0	1	0	0
T83	359	0	0	0
T84	619	0	0	0
T87	44966	0	0	0
T98	0	6	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	6	0	0
T181	0	4	0	0
T184	1628	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149089732	154	0	0
T13	130688	0	0	0
T14	147150	1	0	0
T32	6094	0	0	0
T41	340	4	0	0
T42	402	6	0	0
T43	366	4	0	0
T77	0	1	0	0
T83	359	0	0	0
T84	619	0	0	0
T87	44966	0	0	0
T98	0	6	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	6	0	0
T181	0	4	0	0
T184	1628	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	298180680	7868	0	0
CgEnOn_A	298180680	5485	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298180680	7868	0	0
T4	21592	13	0	0
T5	64358	1	0	0
T7	1377	1	0	0
T8	1353	1	0	0
T9	10544	41	0	0
T27	2172	1	0	0
T28	716	7	0	0
T29	2218	1	0	0
T30	11571	1	0	0
T31	3875	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298180680	5485	0	0
T1	96053	0	0	0
T2	0	11	0	0
T4	21592	0	0	0
T5	64358	0	0	0
T6	30915	1	0	0
T9	10544	35	0	0
T12	0	87	0	0
T13	0	36	0	0
T14	0	111	0	0
T22	0	1	0	0
T27	2172	0	0	0
T28	716	6	0	0
T29	2218	0	0	0
T30	11571	0	0	0
T31	3875	1	0	0
T41	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	149089732	7842	0	0
CgEnOn_A	149089732	5459	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149089732	7842	0	0
T4	10795	13	0	0
T5	32179	1	0	0
T7	688	1	0	0
T8	674	1	0	0
T9	5271	42	0	0
T27	1086	1	0	0
T28	358	9	0	0
T29	1109	1	0	0
T30	5785	1	0	0
T31	1937	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149089732	5459	0	0
T1	48027	0	0	0
T2	0	12	0	0
T4	10795	0	0	0
T5	32179	0	0	0
T6	15454	1	0	0
T9	5271	36	0	0
T12	0	82	0	0
T13	0	39	0	0
T14	0	112	0	0
T22	0	1	0	0
T27	1086	0	0	0
T28	358	8	0	0
T29	1109	0	0	0
T30	5785	0	0	0
T31	1937	1	0	0
T41	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	597834691	7848	0	0
CgEnOn_A	597834691	5459	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597834691	7848	0	0
T4	75938	13	0	0
T5	128754	1	0	0
T7	2725	1	0	0
T8	2523	1	0	0
T9	21170	44	0	0
T27	4423	1	0	0
T28	1456	7	0	0
T29	4484	1	0	0
T30	23276	1	0	0
T31	7788	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597834691	5459	0	0
T1	192172	0	0	0
T2	0	11	0	0
T4	75938	0	0	0
T5	128754	0	0	0
T6	61136	1	0	0
T9	21170	38	0	0
T12	0	86	0	0
T13	0	39	0	0
T14	0	109	0	0
T22	0	1	0	0
T27	4423	0	0	0
T28	1456	6	0	0
T29	4484	0	0	0
T30	23276	0	0	0
T31	7788	1	0	0
T41	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	304286759	7861	0	0
CgEnOn_A	304286759	5470	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304286759	7861	0	0
T4	37971	13	0	0
T5	78780	1	0	0
T7	1363	1	0	0
T8	1262	1	0	0
T9	10585	45	0	0
T27	2212	1	0	0
T28	728	7	0	0
T29	2242	1	0	0
T30	11639	1	0	0
T31	3893	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304286759	5470	0	0
T1	96091	0	0	0
T2	0	11	0	0
T4	37971	0	0	0
T5	78780	0	0	0
T6	39209	1	0	0
T9	10585	39	0	0
T12	0	81	0	0
T13	0	41	0	0
T14	0	110	0	0
T22	0	1	0	0
T27	2212	0	0	0
T28	728	6	0	0
T29	2242	0	0	0
T30	11639	0	0	0
T31	3893	1	0	0
T41	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T6
1	0	Covered	T9,T27,T30
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	634227531	4230	0	0
CgEnOn_A	634227531	4228	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227531	4230	0	0
T1	200185	0	0	0
T2	0	5	0	0
T4	79104	0	0	0
T5	182122	0	0	0
T6	87685	31	0	0
T9	22053	14	0	0
T12	0	101	0	0
T22	0	4	0	0
T24	0	7	0	0
T27	4608	2	0	0
T28	1517	0	0	0
T29	4671	0	0	0
T30	24246	8	0	0
T31	8112	1	0	0
T41	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227531	4228	0	0
T1	200185	0	0	0
T2	0	5	0	0
T4	79104	0	0	0
T5	182122	0	0	0
T6	87685	31	0	0
T9	22053	14	0	0
T12	0	101	0	0
T22	0	4	0	0
T24	0	7	0	0
T27	4608	2	0	0
T28	1517	0	0	0
T29	4671	0	0	0
T30	24246	8	0	0
T31	8112	1	0	0
T41	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T6
1	0	Covered	T9,T27,T30
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	634227531	4252	0	0
CgEnOn_A	634227531	4250	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227531	4252	0	0
T1	200185	0	0	0
T2	0	4	0	0
T4	79104	0	0	0
T5	182122	0	0	0
T6	87685	33	0	0
T9	22053	12	0	0
T12	0	100	0	0
T22	0	2	0	0
T24	0	5	0	0
T27	4608	1	0	0
T28	1517	0	0	0
T29	4671	0	0	0
T30	24246	9	0	0
T31	8112	1	0	0
T41	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227531	4250	0	0
T1	200185	0	0	0
T2	0	4	0	0
T4	79104	0	0	0
T5	182122	0	0	0
T6	87685	33	0	0
T9	22053	12	0	0
T12	0	100	0	0
T22	0	2	0	0
T24	0	5	0	0
T27	4608	1	0	0
T28	1517	0	0	0
T29	4671	0	0	0
T30	24246	9	0	0
T31	8112	1	0	0
T41	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T6
1	0	Covered	T9,T30,T31
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	634227531	4158	0	0
CgEnOn_A	634227531	4156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227531	4158	0	0
T1	200185	0	0	0
T2	0	4	0	0
T4	79104	0	0	0
T5	182122	0	0	0
T6	87685	32	0	0
T9	22053	18	0	0
T12	0	104	0	0
T13	0	13	0	0
T22	0	4	0	0
T24	0	3	0	0
T27	4608	0	0	0
T28	1517	0	0	0
T29	4671	0	0	0
T30	24246	9	0	0
T31	8112	1	0	0
T41	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227531	4156	0	0
T1	200185	0	0	0
T2	0	4	0	0
T4	79104	0	0	0
T5	182122	0	0	0
T6	87685	32	0	0
T9	22053	18	0	0
T12	0	104	0	0
T13	0	13	0	0
T22	0	4	0	0
T24	0	3	0	0
T27	4608	0	0	0
T28	1517	0	0	0
T29	4671	0	0	0
T30	24246	9	0	0
T31	8112	1	0	0
T41	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T6
1	0	Covered	T9,T27,T30
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	634227531	4172	0	0
CgEnOn_A	634227531	4170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227531	4172	0	0
T1	200185	0	0	0
T2	0	6	0	0
T4	79104	0	0	0
T5	182122	0	0	0
T6	87685	36	0	0
T9	22053	16	0	0
T12	0	92	0	0
T22	0	4	0	0
T24	0	2	0	0
T27	4608	2	0	0
T28	1517	0	0	0
T29	4671	0	0	0
T30	24246	9	0	0
T31	8112	1	0	0
T41	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634227531	4170	0	0
T1	200185	0	0	0
T2	0	6	0	0
T4	79104	0	0	0
T5	182122	0	0	0
T6	87685	36	0	0
T9	22053	16	0	0
T12	0	92	0	0
T22	0	4	0	0
T24	0	2	0	0
T27	4608	2	0	0
T28	1517	0	0	0
T29	4671	0	0	0
T30	24246	9	0	0
T31	8112	1	0	0
T41	0	4	0	0