Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T9,T28,T31
0	1	Covered	T9,T28,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T28,T31
1	0	Covered	T41,T42,T43
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1349393514	14115	0	0
GateOpen_A	1349393514	14115	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1349393514	14115	0	0
T1	432345	0	0	0
T2	0	30	0	0
T4	146297	0	0	0
T5	304073	0	0	0
T6	146716	4	0	0
T9	47573	109	0	0
T12	0	209	0	0
T13	0	95	0	0
T14	0	284	0	0
T22	0	4	0	0
T27	9895	0	0	0
T28	3259	19	0	0
T29	10056	0	0	0
T30	52273	0	0	0
T31	17495	4	0	0
T41	0	16	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1349393514	14115	0	0
T1	432345	0	0	0
T2	0	30	0	0
T4	146297	0	0	0
T5	304073	0	0	0
T6	146716	4	0	0
T9	47573	109	0	0
T12	0	209	0	0
T13	0	95	0	0
T14	0	284	0	0
T22	0	4	0	0
T27	9895	0	0	0
T28	3259	19	0	0
T29	10056	0	0	0
T30	52273	0	0	0
T31	17495	4	0	0
T41	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T9,T28,T31
0	1	Covered	T9,T28,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T28,T31
1	0	Covered	T41,T42,T43
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	149090155	3518	0	0
GateOpen_A	149090155	3518	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149090155	3518	0	0
T1	48027	0	0	0
T2	0	8	0	0
T4	10796	0	0	0
T5	32180	0	0	0
T6	15455	1	0	0
T9	5272	28	0	0
T12	0	50	0	0
T13	0	25	0	0
T14	0	77	0	0
T22	0	1	0	0
T27	1086	0	0	0
T28	358	5	0	0
T29	1110	0	0	0
T30	5786	0	0	0
T31	1938	1	0	0
T41	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149090155	3518	0	0
T1	48027	0	0	0
T2	0	8	0	0
T4	10796	0	0	0
T5	32180	0	0	0
T6	15455	1	0	0
T9	5272	28	0	0
T12	0	50	0	0
T13	0	25	0	0
T14	0	77	0	0
T22	0	1	0	0
T27	1086	0	0	0
T28	358	5	0	0
T29	1110	0	0	0
T30	5786	0	0	0
T31	1938	1	0	0
T41	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T9,T28,T31
0	1	Covered	T9,T28,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T28,T31
1	0	Covered	T41,T42,T43
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	298181082	3543	0	0
GateOpen_A	298181082	3543	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298181082	3543	0	0
T1	96054	0	0	0
T2	0	6	0	0
T4	21592	0	0	0
T5	64359	0	0	0
T6	30915	1	0	0
T9	10545	24	0	0
T12	0	53	0	0
T13	0	22	0	0
T14	0	69	0	0
T22	0	1	0	0
T27	2172	0	0	0
T28	716	4	0	0
T29	2219	0	0	0
T30	11571	0	0	0
T31	3875	1	0	0
T41	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	298181082	3543	0	0
T1	96054	0	0	0
T2	0	6	0	0
T4	21592	0	0	0
T5	64359	0	0	0
T6	30915	1	0	0
T9	10545	24	0	0
T12	0	53	0	0
T13	0	22	0	0
T14	0	69	0	0
T22	0	1	0	0
T27	2172	0	0	0
T28	716	4	0	0
T29	2219	0	0	0
T30	11571	0	0	0
T31	3875	1	0	0
T41	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T9,T28,T31
0	1	Covered	T9,T28,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T28,T31
1	0	Covered	T41,T42,T43
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	597835130	3536	0	0
GateOpen_A	597835130	3536	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597835130	3536	0	0
T1	192173	0	0	0
T2	0	8	0	0
T4	75938	0	0	0
T5	128754	0	0	0
T6	61136	1	0	0
T9	21170	28	0	0
T12	0	54	0	0
T13	0	23	0	0
T14	0	69	0	0
T22	0	1	0	0
T27	4424	0	0	0
T28	1457	4	0	0
T29	4484	0	0	0
T30	23277	0	0	0
T31	7788	1	0	0
T41	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597835130	3536	0	0
T1	192173	0	0	0
T2	0	8	0	0
T4	75938	0	0	0
T5	128754	0	0	0
T6	61136	1	0	0
T9	21170	28	0	0
T12	0	54	0	0
T13	0	23	0	0
T14	0	69	0	0
T22	0	1	0	0
T27	4424	0	0	0
T28	1457	4	0	0
T29	4484	0	0	0
T30	23277	0	0	0
T31	7788	1	0	0
T41	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T9,T28,T31
0	1	Covered	T9,T28,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T28,T31
1	0	Covered	T41,T42,T43
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	304287147	3518	0	0
GateOpen_A	304287147	3518	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304287147	3518	0	0
T1	96091	0	0	0
T2	0	8	0	0
T4	37971	0	0	0
T5	78780	0	0	0
T6	39210	1	0	0
T9	10586	29	0	0
T12	0	52	0	0
T13	0	25	0	0
T14	0	69	0	0
T22	0	1	0	0
T27	2213	0	0	0
T28	728	6	0	0
T29	2243	0	0	0
T30	11639	0	0	0
T31	3894	1	0	0
T41	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	304287147	3518	0	0
T1	96091	0	0	0
T2	0	8	0	0
T4	37971	0	0	0
T5	78780	0	0	0
T6	39210	1	0	0
T9	10586	29	0	0
T12	0	52	0	0
T13	0	25	0	0
T14	0	69	0	0
T22	0	1	0	0
T27	2213	0	0	0
T28	728	6	0	0
T29	2243	0	0	0
T30	11639	0	0	0
T31	3894	1	0	0
T41	0	4	0	0