Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	622458	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3601617

1

T6

2

T7

14

T4

62

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1034635	1			T6	1		T7	9		T4	6
values[0x0]	1467808	1			T6	1		T7	10		T4	62
values[0x1]	1721632	1			T6	2		T7	9		T4	65

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	344620	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3879455

1

T6

2

T7

15

T4

82

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17015	1			T4	3		T3	10		T12	2
valid_sources[0x01]	16675	1			T4	1		T10	2		T12	5
valid_sources[0x02]	16348	1			T4	1		T3	7		T13	426
valid_sources[0x03]	16487	1			T5	1		T23	1		T3	1
valid_sources[0x04]	19672	1			T25	1		T23	1		T12	5
valid_sources[0x05]	15248	1			T20	3		T10	1		T12	7
valid_sources[0x06]	15259	1			T4	1		T3	15		T38	1
valid_sources[0x07]	17276	1			T22	1		T10	1		T182	1
valid_sources[0x08]	17135	1			T22	1		T3	1		T38	1
valid_sources[0x09]	16624	1			T4	1		T25	1		T22	2
valid_sources[0x0a]	15187	1			T4	4		T3	3		T12	7
valid_sources[0x0b]	15817	1			T3	5		T12	5		T13	351
valid_sources[0x0c]	19926	1			T4	1		T3	2		T38	1
valid_sources[0x0d]	15688	1			T4	1		T5	1		T25	1
valid_sources[0x0e]	16097	1			T3	2		T10	4		T12	6
valid_sources[0x0f]	18678	1			T1	1441		T38	1		T10	3
valid_sources[0x10]	16019	1			T4	1		T12	7		T13	398
valid_sources[0x11]	16333	1			T4	1		T33	2		T10	2
valid_sources[0x12]	16086	1			T20	2		T3	10		T10	2
valid_sources[0x13]	16503	1			T4	1		T3	2		T38	2
valid_sources[0x14]	18134	1			T3	6		T38	4		T10	2
valid_sources[0x15]	19287	1			T7	1		T12	1		T13	394
valid_sources[0x16]	15273	1			T4	2		T20	2		T22	1
valid_sources[0x17]	18003	1			T25	1		T22	1		T10	3
valid_sources[0x18]	17053	1			T4	1		T2	472		T36	2
valid_sources[0x19]	14940	1			T25	1		T3	3		T12	12
valid_sources[0x1a]	15049	1			T4	2		T37	1		T38	1
valid_sources[0x1b]	17086	1			T20	1		T3	4		T10	1
valid_sources[0x1c]	16517	1			T3	3		T10	3		T12	8
valid_sources[0x1d]	15795	1			T4	1		T3	3		T10	1
valid_sources[0x1e]	19545	1			T3	4		T117	2		T11	1604
valid_sources[0x1f]	16225	1			T10	4		T117	1		T12	10
valid_sources[0x20]	16764	1			T24	2		T33	4		T10	1
valid_sources[0x21]	16612	1			T20	2		T22	1		T3	3
valid_sources[0x22]	17159	1			T3	1		T12	11		T128	1
valid_sources[0x23]	15887	1			T4	1		T24	2		T3	1
valid_sources[0x24]	16244	1			T4	2		T3	10		T10	1
valid_sources[0x25]	15055	1			T4	2		T22	1		T38	2
valid_sources[0x26]	16658	1			T20	1		T33	1		T3	3
valid_sources[0x27]	17182	1			T3	1		T38	1		T10	3
valid_sources[0x28]	14602	1			T4	1		T12	6		T13	387
valid_sources[0x29]	16103	1			T3	3		T10	2		T12	3
valid_sources[0x2a]	16108	1			T4	3		T3	5		T10	1
valid_sources[0x2b]	16650	1			T3	3		T10	1		T12	6
valid_sources[0x2c]	16466	1			T4	1		T10	2		T117	1
valid_sources[0x2d]	14951	1			T19	2		T30	1		T3	4
valid_sources[0x2e]	15438	1			T4	1		T24	1		T3	2
valid_sources[0x2f]	16731	1			T3	2		T10	1		T182	1
valid_sources[0x30]	16427	1			T7	2		T22	1		T3	2
valid_sources[0x31]	16690	1			T5	4		T25	1		T23	1
valid_sources[0x32]	17327	1			T4	2		T25	1		T33	1
valid_sources[0x33]	15738	1			T5	1		T3	1		T117	1
valid_sources[0x34]	16331	1			T3	3		T38	1		T10	3
valid_sources[0x35]	14365	1			T3	5		T12	9		T13	357
valid_sources[0x36]	15708	1			T4	1		T5	3		T3	1
valid_sources[0x37]	16354	1			T3	9		T36	1		T10	2
valid_sources[0x38]	16034	1			T4	1		T24	2		T3	1
valid_sources[0x39]	15133	1			T24	1		T10	1		T12	15
valid_sources[0x3a]	16527	1			T25	2		T33	2		T10	1
valid_sources[0x3b]	15732	1			T20	2		T22	1		T23	1
valid_sources[0x3c]	16204	1			T25	1		T10	2		T12	13
valid_sources[0x3d]	17110	1			T4	2		T38	1		T10	2
valid_sources[0x3e]	16412	1			T4	1		T19	3		T23	3
valid_sources[0x3f]	15862	1			T4	1		T25	1		T18	84
valid_sources[0x40]	16838	1			T3	3		T36	4		T10	2
valid_sources[0x41]	15795	1			T3	1		T10	1		T12	17
valid_sources[0x42]	15357	1			T19	1		T12	12		T13	380
valid_sources[0x43]	17620	1			T20	1		T3	1		T12	3
valid_sources[0x44]	16411	1			T22	1		T3	1		T10	4
valid_sources[0x45]	17077	1			T4	1		T5	8		T23	1
valid_sources[0x46]	16309	1			T20	1		T22	1		T12	8
valid_sources[0x47]	14907	1			T33	2		T10	2		T12	17
valid_sources[0x48]	16144	1			T3	1		T10	1		T12	9
valid_sources[0x49]	15304	1			T4	1		T3	1		T37	7
valid_sources[0x4a]	16305	1			T3	6		T10	1		T12	6
valid_sources[0x4b]	17114	1			T4	1		T3	2		T10	1
valid_sources[0x4c]	15767	1			T33	3		T3	2		T38	1
valid_sources[0x4d]	17079	1			T22	2		T38	2		T10	3
valid_sources[0x4e]	18729	1			T22	1		T3	1		T38	2
valid_sources[0x4f]	16550	1			T22	1		T3	2		T10	1
valid_sources[0x50]	16138	1			T30	2		T3	1		T10	1
valid_sources[0x51]	16251	1			T3	9		T38	1		T10	2
valid_sources[0x52]	15393	1			T4	1		T10	1		T12	22
valid_sources[0x53]	16556	1			T4	2		T25	1		T12	18
valid_sources[0x54]	17350	1			T22	2		T3	2		T10	1
valid_sources[0x55]	16182	1			T4	2		T21	7		T38	1
valid_sources[0x56]	15228	1			T20	1		T22	1		T10	1
valid_sources[0x57]	16740	1			T20	1		T10	2		T12	6
valid_sources[0x58]	16920	1			T20	1		T3	12		T10	2
valid_sources[0x59]	16918	1			T20	1		T3	5		T38	1
valid_sources[0x5a]	17100	1			T21	6		T23	1		T3	2
valid_sources[0x5b]	16963	1			T4	1		T23	1		T10	1
valid_sources[0x5c]	16425	1			T3	1		T10	3		T12	7
valid_sources[0x5d]	16263	1			T5	2		T24	1		T3	1
valid_sources[0x5e]	15720	1			T3	4		T10	2		T12	5
valid_sources[0x5f]	16658	1			T3	4		T38	2		T12	16
valid_sources[0x60]	17017	1			T23	1		T3	1		T38	1
valid_sources[0x61]	16325	1			T4	3		T3	1		T10	2
valid_sources[0x62]	17298	1			T10	1		T12	15		T13	343
valid_sources[0x63]	16931	1			T4	1		T3	3		T10	1
valid_sources[0x64]	17143	1			T22	2		T3	5		T12	6
valid_sources[0x65]	16045	1			T117	1		T12	11		T13	369
valid_sources[0x66]	16093	1			T4	2		T3	2		T10	2
valid_sources[0x67]	15595	1			T4	1		T25	1		T23	1
valid_sources[0x68]	15280	1			T3	2		T117	1		T12	12
valid_sources[0x69]	16691	1			T7	2		T4	3		T23	1
valid_sources[0x6a]	15406	1			T4	1		T5	1		T38	1
valid_sources[0x6b]	15752	1			T4	1		T19	3		T12	8
valid_sources[0x6c]	16339	1			T12	7		T13	364		T76	1
valid_sources[0x6d]	18133	1			T4	1		T3	2		T12	10
valid_sources[0x6e]	16764	1			T4	1		T5	10		T3	2
valid_sources[0x6f]	15340	1			T10	3		T12	10		T183	4
valid_sources[0x70]	16492	1			T5	5		T33	1		T182	2
valid_sources[0x71]	16688	1			T22	1		T3	1		T12	5
valid_sources[0x72]	17046	1			T36	1		T10	2		T182	1
valid_sources[0x73]	17492	1			T20	1		T23	1		T38	4
valid_sources[0x74]	14611	1			T21	15		T33	1		T3	6
valid_sources[0x75]	17174	1			T33	1		T38	1		T10	3
valid_sources[0x76]	16978	1			T3	4		T10	4		T12	19
valid_sources[0x77]	15084	1			T19	1		T38	1		T10	1
valid_sources[0x78]	17481	1			T10	1		T117	1		T12	7
valid_sources[0x79]	16849	1			T22	3		T33	1		T3	1
valid_sources[0x7a]	16259	1			T4	2		T3	2		T38	1
valid_sources[0x7b]	17216	1			T4	1		T25	2		T3	3
valid_sources[0x7c]	16539	1			T4	1		T20	1		T33	8
valid_sources[0x7d]	17208	1			T23	1		T38	1		T12	20
valid_sources[0x7e]	16067	1			T20	1		T12	17		T13	359
valid_sources[0x7f]	17061	1			T4	2		T3	1		T38	2
valid_sources[0x80]	16921	1			T20	1		T3	2		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

906877

1

T7

6

T4

1

T5

1

values[0x0]

all_enables

biggest_size

1371637

1

T7

5

T4

40

T5

26

values[0x1]

all_enables

biggest_size

1323103

1

T6

2

T7

3

T4

21