Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	788958440	76248	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	788958440	76248	0	0
T1	1436100	211	0	0
T2	605115	281	0	0
T3	0	245	0	0
T10	0	210	0	0
T11	0	85	0	0
T12	0	563	0	0
T13	0	267	0	0
T14	0	203	0	0
T15	0	479	0	0
T16	0	215	0	0
T17	4505	0	0	0
T18	124480	0	0	0
T19	5515	0	0	0
T20	8555	0	0	0
T21	7655	0	0	0
T22	11160	0	0	0
T23	7210	0	0	0
T24	3495	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157791688	11314	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157791688	11314	0	0
T1	287220	28	0	0
T2	121023	41	0	0
T3	0	40	0	0
T10	0	28	0	0
T11	0	11	0	0
T12	0	74	0	0
T13	0	50	0	0
T14	0	30	0	0
T15	0	70	0	0
T16	0	27	0	0
T17	901	0	0	0
T18	24896	0	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T23	1442	0	0	0
T24	699	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157791688	15316	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157791688	15316	0	0
T1	287220	43	0	0
T2	121023	56	0	0
T3	0	47	0	0
T10	0	40	0	0
T11	0	17	0	0
T12	0	115	0	0
T13	0	50	0	0
T14	0	41	0	0
T15	0	99	0	0
T16	0	44	0	0
T17	901	0	0	0
T18	24896	0	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T23	1442	0	0	0
T24	699	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157791688	22958	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157791688	22958	0	0
T1	287220	70	0	0
T2	121023	89	0	0
T3	0	71	0	0
T10	0	73	0	0
T11	0	29	0	0
T12	0	187	0	0
T13	0	66	0	0
T14	0	61	0	0
T15	0	156	0	0
T16	0	72	0	0
T17	901	0	0	0
T18	24896	0	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T23	1442	0	0	0
T24	699	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157791688	11209	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157791688	11209	0	0
T1	287220	26	0	0
T2	121023	39	0	0
T3	0	38	0	0
T10	0	26	0	0
T11	0	11	0	0
T12	0	73	0	0
T13	0	50	0	0
T14	0	30	0	0
T15	0	58	0	0
T16	0	30	0	0
T17	901	0	0	0
T18	24896	0	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T23	1442	0	0	0
T24	699	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157791688	15451	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157791688	15451	0	0
T1	287220	44	0	0
T2	121023	56	0	0
T3	0	49	0	0
T10	0	43	0	0
T11	0	17	0	0
T12	0	114	0	0
T13	0	51	0	0
T14	0	41	0	0
T15	0	96	0	0
T16	0	42	0	0
T17	901	0	0	0
T18	24896	0	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T23	1442	0	0	0
T24	699	0	0	0