Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Unreachable
1	0	Covered	T1,T34,T11

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	157791688	155580548	0	0
AllClkBypReqTrue_A	157791688	132853	0	0
IoClkBypReqFalse_A	157791688	155496365	0	2415
IoClkBypReqTrue_A	157791688	212632	0	0
LcClkBypAckFalse_A	157791688	155589294	0	0
LcClkBypAckTrue_A	157791688	124107	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157791688	155580548	0	0
T1	287220	283912	0	0
T4	18950	18909	0	0
T5	12731	12685	0	0
T6	1315	1260	0	0
T7	1284	1252	0	0
T17	901	851	0	0
T18	24896	24850	0	0
T19	1103	1031	0	0
T20	1711	1498	0	0
T25	1772	1621	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157791688	132853	0	0
T1	287220	749	0	0
T17	901	0	0	0
T18	24896	0	0	0
T19	1103	33	0	0
T20	1711	0	0	0
T21	1531	69	0	0
T22	2232	171	0	0
T23	1442	142	0	0
T24	699	0	0	0
T25	1772	75	0	0
T30	0	10	0	0
T31	0	48	0	0
T36	0	85	0	0
T37	0	40	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157791688	155496365	0	2415
T1	287220	283359	0	3
T4	18950	18907	0	3
T5	12731	12683	0	3
T6	1315	1226	0	3
T7	1284	1040	0	3
T17	901	849	0	3
T18	24896	24848	0	3
T19	1103	934	0	3
T20	1711	1496	0	3
T25	1772	1661	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157791688	212632	0	0
T1	287220	1274	0	0
T4	18950	0	0	0
T5	12731	0	0	0
T6	1315	32	0	0
T7	1284	210	0	0
T17	901	0	0	0
T18	24896	0	0	0
T19	1103	128	0	0
T20	1711	0	0	0
T21	0	46	0	0
T22	0	336	0	0
T23	0	224	0	0
T25	1772	33	0	0
T31	0	117	0	0
T36	0	89	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157791688	155589294	0	0
T1	287220	284086	0	0
T4	18950	18909	0	0
T5	12731	12685	0	0
T6	1315	1232	0	0
T7	1284	1202	0	0
T17	901	851	0	0
T18	24896	24850	0	0
T19	1103	1024	0	0
T20	1711	1498	0	0
T25	1772	1690	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157791688	124107	0	0
T1	287220	575	0	0
T4	18950	0	0	0
T5	12731	0	0	0
T6	1315	28	0	0
T7	1284	50	0	0
T17	901	0	0	0
T18	24896	0	0	0
T19	1103	40	0	0
T20	1711	0	0	0
T21	0	42	0	0
T22	0	250	0	0
T23	0	134	0	0
T25	1772	6	0	0
T31	0	17	0	0
T36	0	78	0	0