Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16013	0	0
TransStop_A	2147483647	8089	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16013	0	0
T1	1030176	50	0	0
T2	949216	0	0	0
T11	0	4	0	0
T12	0	60	0	0
T13	0	191	0	0
T15	0	18	0	0
T17	14424	0	0	0
T18	473932	0	0	0
T19	17664	0	0	0
T20	6848	0	0	0
T21	40848	0	0	0
T22	9112	0	0	0
T23	24048	0	0	0
T24	55984	0	0	0
T33	0	4	0	0
T38	0	4	0	0
T76	0	4	0	0
T78	0	33	0	0
T80	0	4	0	0
T128	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8089	0	0
T1	1030176	32	0	0
T2	949216	0	0	0
T11	0	4	0	0
T12	0	36	0	0
T13	0	93	0	0
T15	0	9	0	0
T17	14424	0	0	0
T18	473932	0	0	0
T19	17664	0	0	0
T20	6848	0	0	0
T21	40848	0	0	0
T22	9112	0	0	0
T23	24048	0	0	0
T24	55984	0	0	0
T33	0	4	0	0
T38	0	4	0	0
T76	0	4	0	0
T78	0	11	0	0
T80	0	4	0	0
T128	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	555623000	3960	0	0
TransStop_A	555623000	2008	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555623000	3960	0	0
T1	257544	11	0	0
T2	237304	0	0	0
T11	0	1	0	0
T12	0	14	0	0
T13	0	44	0	0
T17	3606	0	0	0
T18	118483	0	0	0
T19	4416	0	0	0
T20	1712	0	0	0
T21	10212	0	0	0
T22	2278	0	0	0
T23	6012	0	0	0
T24	13996	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T78	0	9	0	0
T80	0	1	0	0
T128	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555623000	2008	0	0
T1	257544	9	0	0
T2	237304	0	0	0
T11	0	1	0	0
T12	0	8	0	0
T13	0	20	0	0
T17	3606	0	0	0
T18	118483	0	0	0
T19	4416	0	0	0
T20	1712	0	0	0
T21	10212	0	0	0
T22	2278	0	0	0
T23	6012	0	0	0
T24	13996	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T78	0	2	0	0
T80	0	1	0	0
T128	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	555623000	4006	0	0
TransStop_A	555623000	2002	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555623000	4006	0	0
T1	257544	14	0	0
T2	237304	0	0	0
T11	0	1	0	0
T12	0	17	0	0
T13	0	55	0	0
T15	0	18	0	0
T17	3606	0	0	0
T18	118483	0	0	0
T19	4416	0	0	0
T20	1712	0	0	0
T21	10212	0	0	0
T22	2278	0	0	0
T23	6012	0	0	0
T24	13996	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T78	0	7	0	0
T80	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555623000	2002	0	0
T1	257544	7	0	0
T2	237304	0	0	0
T11	0	1	0	0
T12	0	11	0	0
T13	0	29	0	0
T15	0	9	0	0
T17	3606	0	0	0
T18	118483	0	0	0
T19	4416	0	0	0
T20	1712	0	0	0
T21	10212	0	0	0
T22	2278	0	0	0
T23	6012	0	0	0
T24	13996	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T78	0	3	0	0
T80	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	555623000	4033	0	0
TransStop_A	555623000	2036	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555623000	4033	0	0
T1	257544	14	0	0
T2	237304	0	0	0
T11	0	1	0	0
T12	0	16	0	0
T13	0	41	0	0
T17	3606	0	0	0
T18	118483	0	0	0
T19	4416	0	0	0
T20	1712	0	0	0
T21	10212	0	0	0
T22	2278	0	0	0
T23	6012	0	0	0
T24	13996	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T78	0	8	0	0
T80	0	1	0	0
T128	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555623000	2036	0	0
T1	257544	9	0	0
T2	237304	0	0	0
T11	0	1	0	0
T12	0	9	0	0
T13	0	19	0	0
T17	3606	0	0	0
T18	118483	0	0	0
T19	4416	0	0	0
T20	1712	0	0	0
T21	10212	0	0	0
T22	2278	0	0	0
T23	6012	0	0	0
T24	13996	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T78	0	3	0	0
T80	0	1	0	0
T128	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	555623000	4014	0	0
TransStop_A	555623000	2043	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555623000	4014	0	0
T1	257544	11	0	0
T2	237304	0	0	0
T11	0	1	0	0
T12	0	13	0	0
T13	0	51	0	0
T17	3606	0	0	0
T18	118483	0	0	0
T19	4416	0	0	0
T20	1712	0	0	0
T21	10212	0	0	0
T22	2278	0	0	0
T23	6012	0	0	0
T24	13996	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T78	0	9	0	0
T80	0	1	0	0
T128	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555623000	2043	0	0
T1	257544	7	0	0
T2	237304	0	0	0
T11	0	1	0	0
T12	0	8	0	0
T13	0	25	0	0
T17	3606	0	0	0
T18	118483	0	0	0
T19	4416	0	0	0
T20	1712	0	0	0
T21	10212	0	0	0
T22	2278	0	0	0
T23	6012	0	0	0
T24	13996	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T78	0	3	0	0
T80	0	1	0	0
T128	0	1	0	0