Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	157791688	20573850	0	60

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157791688	20573850	0	60
T1	287220	23140	0	0
T2	121023	25559	0	1
T3	0	18339	0	1
T10	0	24713	0	1
T11	0	12026	0	0
T12	0	74478	0	1
T13	0	916524	0	0
T14	0	18858	0	1
T15	0	61055	0	1
T16	0	25159	0	1
T17	901	0	0	0
T18	24896	0	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T23	1442	0	0	0
T24	699	0	0	0
T28	0	0	0	1
T87	0	0	0	1
T129	0	0	0	1