Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	158705469	5265285	0	0
clk_enables_rd_A	158705469	36534	0	0
clk_hints_rd_A	158705469	31204	0	0
extclk_ctrl_rd_A	158705469	40321	0	0
extclk_ctrl_regwen_rd_A	158705469	30634	0	0
jitter_enable_rd_A	158705469	46563	0	0
jitter_regwen_rd_A	158705469	34296	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	5265285	0	0
T13	251990	129208	0	0
T14	58090	0	0	0
T35	0	80164	0	0
T39	1298	0	0	0
T45	0	66013	0	0
T69	0	111259	0	0
T70	0	61281	0	0
T71	0	34287	0	0
T72	0	39553	0	0
T73	0	60667	0	0
T74	0	90172	0	0
T75	0	224394	0	0
T76	1056	0	0	0
T77	1250	0	0	0
T78	2357	0	0	0
T79	63427	0	0	0
T80	2012	0	0	0
T81	1386	0	0	0
T82	2647	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	36534	0	0
T1	287220	26	0	0
T2	121023	0	0	0
T17	901	0	0	0
T18	24896	0	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T23	1442	0	0	0
T24	699	0	0	0
T35	0	1899	0	0
T43	0	4022	0	0
T45	0	2628	0	0
T70	0	1124	0	0
T71	0	811	0	0
T73	0	2337	0	0
T74	0	3473	0	0
T151	0	2	0	0
T152	0	4	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	31204	0	0
T1	287220	23	0	0
T2	121023	0	0	0
T17	901	0	0	0
T18	24896	0	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T23	1442	0	0	0
T24	699	0	0	0
T35	0	1477	0	0
T43	0	3676	0	0
T45	0	2125	0	0
T70	0	1133	0	0
T71	0	537	0	0
T73	0	1901	0	0
T74	0	2983	0	0
T152	0	3	0	0
T153	0	6	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	40321	0	0
T1	287220	110	0	0
T2	121023	0	0	0
T17	901	0	0	0
T18	24896	0	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	35	0	0
T22	2232	0	0	0
T23	1442	0	0	0
T24	699	0	0	0
T35	0	1748	0	0
T45	0	2806	0	0
T82	0	51	0	0
T117	0	15	0	0
T154	0	7	0	0
T155	0	40	0	0
T156	0	70	0	0
T157	0	125	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	30634	0	0
T35	257287	1607	0	0
T43	0	3510	0	0
T45	231222	2525	0	0
T70	0	1207	0	0
T71	0	644	0	0
T73	0	1823	0	0
T74	0	2956	0	0
T127	30307	0	0	0
T157	0	71	0	0
T158	0	35	0	0
T159	0	32	0	0
T160	2187	0	0	0
T161	879	0	0	0
T162	2609	0	0	0
T163	1451	0	0	0
T164	2010	0	0	0
T165	1419	0	0	0
T166	2341	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	46563	0	0
T1	287220	747	0	0
T2	121023	0	0	0
T17	901	0	0	0
T18	24896	0	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T23	1442	0	0	0
T24	699	0	0	0
T35	0	1702	0	0
T43	0	5506	0	0
T45	0	2844	0	0
T70	0	1346	0	0
T71	0	970	0	0
T73	0	2965	0	0
T74	0	4239	0	0
T151	0	107	0	0
T152	0	125	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	34296	0	0
T35	257287	1662	0	0
T43	0	3979	0	0
T45	231222	2436	0	0
T70	0	1232	0	0
T71	0	710	0	0
T73	0	2516	0	0
T74	0	3512	0	0
T127	30307	0	0	0
T160	2187	0	0	0
T161	879	0	0	0
T162	2609	0	0	0
T163	1451	0	0	0
T164	2010	0	0	0
T165	1419	0	0	0
T166	2341	0	0	0
T167	0	383	0	0
T168	0	1058	0	0
T169	0	1980	0	0