Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T34,T13,T60
1	0	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1587054690	1400365	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1587054690	288861	0	0
SrcBusyKnown_A	1587054690	1565398290	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587054690	1400365	0	0
T1	2872200	3835	0	0
T2	0	2042	0	0
T3	0	1448	0	0
T4	189500	420	0	0
T5	127310	251	0	0
T10	0	1866	0	0
T11	0	8962	0	0
T12	0	13455	0	0
T17	9010	0	0	0
T18	248960	672	0	0
T19	11030	0	0	0
T20	17110	0	0	0
T21	15310	0	0	0
T22	22320	0	0	0
T25	17720	0	0	0
T34	0	94	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1767918	1752696	0	0
T4	422684	421654	0	0
T5	275628	274632	0	0
T6	8396	8088	0	0
T7	32706	32030	0	0
T17	22644	21538	0	0
T18	696794	695524	0	0
T19	28116	27176	0	0
T20	10714	9474	0	0
T25	12542	12074	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587054690	288861	0	0
T1	2872200	460	0	0
T2	0	400	0	0
T3	0	400	0	0
T4	189500	120	0	0
T5	127310	80	0	0
T10	0	240	0	0
T11	0	1180	0	0
T12	0	1680	0	0
T17	9010	0	0	0
T18	248960	200	0	0
T19	11030	0	0	0
T20	17110	0	0	0
T21	15310	0	0	0
T22	22320	0	0	0
T25	17720	0	0	0
T34	0	28	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1587054690	1565398290	0	0
T1	2872200	2846750	0	0
T4	189500	189100	0	0
T5	127310	126860	0	0
T6	13150	12610	0	0
T7	12840	12530	0	0
T17	9010	8520	0	0
T18	248960	248510	0	0
T19	11030	10650	0	0
T20	17110	14990	0	0
T25	17720	16970	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158705469	88955	0	0
DstReqKnown_A	525085692	520885068	0	0
SrcAckBusyChk_A	158705469	26269	0	0
SrcBusyKnown_A	158705469	156539829	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	88955	0	0
T1	287220	242	0	0
T2	0	146	0	0
T3	0	111	0	0
T4	18950	31	0	0
T5	12731	18	0	0
T10	0	116	0	0
T11	0	567	0	0
T12	0	844	0	0
T17	901	0	0	0
T18	24896	52	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	5	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525085692	520885068	0	0
T1	276034	273430	0	0
T4	64282	64120	0	0
T5	37371	37195	0	0
T6	1275	1222	0	0
T7	4934	4813	0	0
T17	3461	3271	0	0
T18	102219	102002	0	0
T19	4239	4091	0	0
T20	1643	1439	0	0
T25	1890	1810	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	26269	0	0
T1	287220	46	0	0
T2	0	40	0	0
T3	0	40	0	0
T4	18950	12	0	0
T5	12731	8	0	0
T10	0	24	0	0
T11	0	118	0	0
T12	0	168	0	0
T17	901	0	0	0
T18	24896	20	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	156539829	0	0
T1	287220	284675	0	0
T4	18950	18910	0	0
T5	12731	12686	0	0
T6	1315	1261	0	0
T7	1284	1253	0	0
T17	901	852	0	0
T18	24896	24851	0	0
T19	1103	1065	0	0
T20	1711	1499	0	0
T25	1772	1697	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158705469	126301	0	0
DstReqKnown_A	261848463	260773591	0	0
SrcAckBusyChk_A	158705469	26269	0	0
SrcBusyKnown_A	158705469	156539829	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	126301	0	0
T1	287220	386	0	0
T2	0	203	0	0
T3	0	146	0	0
T4	18950	43	0	0
T5	12731	26	0	0
T10	0	188	0	0
T11	0	898	0	0
T12	0	1348	0	0
T17	901	0	0	0
T18	24896	69	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	7	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261848463	260773591	0	0
T1	137734	137073	0	0
T4	32129	32060	0	0
T5	18632	18597	0	0
T6	639	625	0	0
T7	2541	2520	0	0
T17	1684	1636	0	0
T18	51056	51001	0	0
T19	2189	2127	0	0
T20	788	719	0	0
T25	979	958	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	26269	0	0
T1	287220	46	0	0
T2	0	40	0	0
T3	0	40	0	0
T4	18950	12	0	0
T5	12731	8	0	0
T10	0	24	0	0
T11	0	118	0	0
T12	0	168	0	0
T17	901	0	0	0
T18	24896	20	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	156539829	0	0
T1	287220	284675	0	0
T4	18950	18910	0	0
T5	12731	12686	0	0
T6	1315	1261	0	0
T7	1284	1253	0	0
T17	901	852	0	0
T18	24896	24851	0	0
T19	1103	1065	0	0
T20	1711	1499	0	0
T25	1772	1697	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158705469	199233	0	0
DstReqKnown_A	130923529	130386186	0	0
SrcAckBusyChk_A	158705469	26269	0	0
SrcBusyKnown_A	158705469	156539829	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	199233	0	0
T1	287220	680	0	0
T2	0	327	0	0
T3	0	216	0	0
T4	18950	62	0	0
T5	12731	37	0	0
T10	0	323	0	0
T11	0	1575	0	0
T12	0	2341	0	0
T17	901	0	0	0
T18	24896	95	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	10	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130923529	130386186	0	0
T1	68863	68532	0	0
T4	16064	16030	0	0
T5	9316	9299	0	0
T6	319	312	0	0
T7	1270	1260	0	0
T17	842	818	0	0
T18	25528	25500	0	0
T19	1095	1064	0	0
T20	394	360	0	0
T25	489	479	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	26269	0	0
T1	287220	46	0	0
T2	0	40	0	0
T3	0	40	0	0
T4	18950	12	0	0
T5	12731	8	0	0
T10	0	24	0	0
T11	0	118	0	0
T12	0	168	0	0
T17	901	0	0	0
T18	24896	20	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	156539829	0	0
T1	287220	284675	0	0
T4	18950	18910	0	0
T5	12731	12686	0	0
T6	1315	1261	0	0
T7	1284	1253	0	0
T17	901	852	0	0
T18	24896	24851	0	0
T19	1103	1065	0	0
T20	1711	1499	0	0
T25	1772	1697	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158705469	88115	0	0
DstReqKnown_A	558410496	553961406	0	0
SrcAckBusyChk_A	158705469	26269	0	0
SrcBusyKnown_A	158705469	156539829	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	88115	0	0
T1	287220	233	0	0
T2	0	138	0	0
T3	0	108	0	0
T4	18950	31	0	0
T5	12731	18	0	0
T10	0	114	0	0
T11	0	553	0	0
T12	0	825	0	0
T17	901	0	0	0
T18	24896	52	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	5	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558410496	553961406	0	0
T1	257544	254834	0	0
T4	60964	60795	0	0
T5	50929	50746	0	0
T6	1328	1274	0	0
T7	5141	5015	0	0
T17	3605	3408	0	0
T18	118482	118256	0	0
T19	4416	4261	0	0
T20	1711	1499	0	0
T25	1968	1885	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	26269	0	0
T1	287220	46	0	0
T2	0	40	0	0
T3	0	40	0	0
T4	18950	12	0	0
T5	12731	8	0	0
T10	0	24	0	0
T11	0	118	0	0
T12	0	168	0	0
T17	901	0	0	0
T18	24896	20	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	156539829	0	0
T1	287220	284675	0	0
T4	18950	18910	0	0
T5	12731	12686	0	0
T6	1315	1261	0	0
T7	1284	1253	0	0
T17	901	852	0	0
T18	24896	24851	0	0
T19	1103	1065	0	0
T20	1711	1499	0	0
T25	1772	1697	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158705469	125563	0	0
DstReqKnown_A	267804661	265674983	0	0
SrcAckBusyChk_A	158705469	25804	0	0
SrcBusyKnown_A	158705469	156539829	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	125563	0	0
T1	287220	380	0	0
T2	0	204	0	0
T3	0	150	0	0
T4	18950	43	0	0
T5	12731	26	0	0
T10	0	187	0	0
T11	0	897	0	0
T12	0	1353	0	0
T17	901	0	0	0
T18	24896	68	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	5	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267804661	265674983	0	0
T1	143784	142479	0	0
T4	37903	37822	0	0
T5	21566	21479	0	0
T6	637	611	0	0
T7	2467	2407	0	0
T17	1730	1636	0	0
T18	51112	51003	0	0
T19	2119	2045	0	0
T20	821	720	0	0
T25	945	905	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	25804	0	0
T1	287220	46	0	0
T2	0	40	0	0
T3	0	40	0	0
T4	18950	12	0	0
T5	12731	8	0	0
T10	0	24	0	0
T11	0	118	0	0
T12	0	168	0	0
T17	901	0	0	0
T18	24896	20	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	156539829	0	0
T1	287220	284675	0	0
T4	18950	18910	0	0
T5	12731	12686	0	0
T6	1315	1261	0	0
T7	1284	1253	0	0
T17	901	852	0	0
T18	24896	24851	0	0
T19	1103	1065	0	0
T20	1711	1499	0	0
T25	1772	1697	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T34,T13,T60
1	0	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158705469	108921	0	0
DstReqKnown_A	525085692	520885068	0	0
SrcAckBusyChk_A	158705469	31744	0	0
SrcBusyKnown_A	158705469	156539829	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	108921	0	0
T1	287220	243	0	0
T2	0	142	0	0
T3	0	111	0	0
T4	18950	31	0	0
T5	12731	18	0	0
T10	0	118	0	0
T11	0	563	0	0
T12	0	840	0	0
T17	901	0	0	0
T18	24896	52	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	9	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525085692	520885068	0	0
T1	276034	273430	0	0
T4	64282	64120	0	0
T5	37371	37195	0	0
T6	1275	1222	0	0
T7	4934	4813	0	0
T17	3461	3271	0	0
T18	102219	102002	0	0
T19	4239	4091	0	0
T20	1643	1439	0	0
T25	1890	1810	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	31744	0	0
T1	287220	46	0	0
T2	0	40	0	0
T3	0	40	0	0
T4	18950	12	0	0
T5	12731	8	0	0
T10	0	24	0	0
T11	0	118	0	0
T12	0	168	0	0
T17	901	0	0	0
T18	24896	20	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	156539829	0	0
T1	287220	284675	0	0
T4	18950	18910	0	0
T5	12731	12686	0	0
T6	1315	1261	0	0
T7	1284	1253	0	0
T17	901	852	0	0
T18	24896	24851	0	0
T19	1103	1065	0	0
T20	1711	1499	0	0
T25	1772	1697	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T34,T13,T60
1	0	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158705469	154463	0	0
DstReqKnown_A	261848463	260773591	0	0
SrcAckBusyChk_A	158705469	31644	0	0
SrcBusyKnown_A	158705469	156539829	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	154463	0	0
T1	287220	386	0	0
T2	0	205	0	0
T3	0	146	0	0
T4	18950	43	0	0
T5	12731	26	0	0
T10	0	192	0	0
T11	0	894	0	0
T12	0	1360	0	0
T17	901	0	0	0
T18	24896	71	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	13	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261848463	260773591	0	0
T1	137734	137073	0	0
T4	32129	32060	0	0
T5	18632	18597	0	0
T6	639	625	0	0
T7	2541	2520	0	0
T17	1684	1636	0	0
T18	51056	51001	0	0
T19	2189	2127	0	0
T20	788	719	0	0
T25	979	958	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	31644	0	0
T1	287220	46	0	0
T2	0	40	0	0
T3	0	40	0	0
T4	18950	12	0	0
T5	12731	8	0	0
T10	0	24	0	0
T11	0	118	0	0
T12	0	168	0	0
T17	901	0	0	0
T18	24896	20	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	156539829	0	0
T1	287220	284675	0	0
T4	18950	18910	0	0
T5	12731	12686	0	0
T6	1315	1261	0	0
T7	1284	1253	0	0
T17	901	852	0	0
T18	24896	24851	0	0
T19	1103	1065	0	0
T20	1711	1499	0	0
T25	1772	1697	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T34,T13,T60
1	0	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158705469	246083	0	0
DstReqKnown_A	130923529	130386186	0	0
SrcAckBusyChk_A	158705469	31679	0	0
SrcBusyKnown_A	158705469	156539829	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	246083	0	0
T1	287220	667	0	0
T2	0	334	0	0
T3	0	213	0	0
T4	18950	62	0	0
T5	12731	38	0	0
T10	0	327	0	0
T11	0	1567	0	0
T12	0	2368	0	0
T17	901	0	0	0
T18	24896	93	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	18	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130923529	130386186	0	0
T1	68863	68532	0	0
T4	16064	16030	0	0
T5	9316	9299	0	0
T6	319	312	0	0
T7	1270	1260	0	0
T17	842	818	0	0
T18	25528	25500	0	0
T19	1095	1064	0	0
T20	394	360	0	0
T25	489	479	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	31679	0	0
T1	287220	46	0	0
T2	0	40	0	0
T3	0	40	0	0
T4	18950	12	0	0
T5	12731	8	0	0
T10	0	24	0	0
T11	0	118	0	0
T12	0	168	0	0
T17	901	0	0	0
T18	24896	20	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	156539829	0	0
T1	287220	284675	0	0
T4	18950	18910	0	0
T5	12731	12686	0	0
T6	1315	1261	0	0
T7	1284	1253	0	0
T17	901	852	0	0
T18	24896	24851	0	0
T19	1103	1065	0	0
T20	1711	1499	0	0
T25	1772	1697	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T34,T13,T60
1	0	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158705469	107517	0	0
DstReqKnown_A	558410496	553961406	0	0
SrcAckBusyChk_A	158705469	31608	0	0
SrcBusyKnown_A	158705469	156539829	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	107517	0	0
T1	287220	236	0	0
T2	0	139	0	0
T3	0	102	0	0
T4	18950	31	0	0
T5	12731	18	0	0
T10	0	113	0	0
T11	0	548	0	0
T12	0	823	0	0
T17	901	0	0	0
T18	24896	52	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	9	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558410496	553961406	0	0
T1	257544	254834	0	0
T4	60964	60795	0	0
T5	50929	50746	0	0
T6	1328	1274	0	0
T7	5141	5015	0	0
T17	3605	3408	0	0
T18	118482	118256	0	0
T19	4416	4261	0	0
T20	1711	1499	0	0
T25	1968	1885	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	31608	0	0
T1	287220	46	0	0
T2	0	40	0	0
T3	0	40	0	0
T4	18950	12	0	0
T5	12731	8	0	0
T10	0	24	0	0
T11	0	118	0	0
T12	0	168	0	0
T17	901	0	0	0
T18	24896	20	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	156539829	0	0
T1	287220	284675	0	0
T4	18950	18910	0	0
T5	12731	12686	0	0
T6	1315	1261	0	0
T7	1284	1253	0	0
T17	901	852	0	0
T18	24896	24851	0	0
T19	1103	1065	0	0
T20	1711	1499	0	0
T25	1772	1697	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Covered	T34,T13,T60
1	0	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T4
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T4
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	158705469	155214	0	0
DstReqKnown_A	267804661	265674983	0	0
SrcAckBusyChk_A	158705469	31306	0	0
SrcBusyKnown_A	158705469	156539829	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	155214	0	0
T1	287220	382	0	0
T2	0	204	0	0
T3	0	145	0	0
T4	18950	43	0	0
T5	12731	26	0	0
T10	0	188	0	0
T11	0	900	0	0
T12	0	1353	0	0
T17	901	0	0	0
T18	24896	68	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	13	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267804661	265674983	0	0
T1	143784	142479	0	0
T4	37903	37822	0	0
T5	21566	21479	0	0
T6	637	611	0	0
T7	2467	2407	0	0
T17	1730	1636	0	0
T18	51112	51003	0	0
T19	2119	2045	0	0
T20	821	720	0	0
T25	945	905	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	31306	0	0
T1	287220	46	0	0
T2	0	40	0	0
T3	0	40	0	0
T4	18950	12	0	0
T5	12731	8	0	0
T10	0	24	0	0
T11	0	118	0	0
T12	0	168	0	0
T17	901	0	0	0
T18	24896	20	0	0
T19	1103	0	0	0
T20	1711	0	0	0
T21	1531	0	0	0
T22	2232	0	0	0
T25	1772	0	0	0
T34	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158705469	156539829	0	0
T1	287220	284675	0	0
T4	18950	18910	0	0
T5	12731	12686	0	0
T6	1315	1261	0	0
T7	1284	1253	0	0
T17	901	852	0	0
T18	24896	24851	0	0
T19	1103	1065	0	0
T20	1711	1499	0	0
T25	1772	1697	0	0