Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T32
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48348	0	0
CgEnOn_A	2147483647	39551	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48348	0	0
T1	740175	203	0	0
T3	533477	0	0	0
T4	112475	3	0	0
T5	65319	3	0	0
T6	2233	3	0	0
T7	8745	3	0	0
T10	301828	0	0	0
T17	9592	17	0	0
T18	297285	3	0	0
T19	11939	3	0	0
T20	4536	43	0	0
T21	10212	0	0	0
T25	3358	3	0	0
T29	6495	12	0	0
T30	10214	0	0	0
T31	9542	0	0	0
T32	4750	11	0	0
T33	11461	1	0	0
T36	6066	0	0	0
T37	7581	0	0	0
T38	12079	0	0	0
T44	0	20	0	0
T72	0	5	0	0
T170	0	20	0	0
T171	0	15	0	0
T172	0	5	0	0
T173	0	15	0	0
T174	0	10	0	0
T175	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39551	0	0
T1	1656591	161	0	0
T2	1461694	0	0	0
T3	1027497	0	0	0
T10	581366	0	0	0
T11	0	153	0	0
T12	0	121	0	0
T13	0	44	0	0
T17	22137	14	0	0
T18	703843	0	0	0
T19	27306	0	0	0
T20	10490	40	0	0
T21	63427	0	0	0
T22	14207	0	0	0
T23	37445	0	0	0
T24	86158	18	0	0
T29	12933	18	0	0
T30	19732	0	0	0
T31	18328	0	0	0
T32	9264	17	0	0
T33	22213	4	0	0
T36	11530	0	0	0
T37	14405	0	0	0
T38	23357	4	0	0
T44	0	20	0	0
T72	0	4	0	0
T128	0	2	0	0
T170	0	20	0	0
T171	0	15	0	0
T172	0	5	0	0
T173	0	15	0	0
T174	0	10	0	0
T175	0	15	0	0
T176	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T32
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	260553703	156	0	0
CgEnOn_A	260553703	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260553703	156	0	0
T3	118542	0	0	0
T10	67061	0	0	0
T29	1423	2	0	0
T30	2259	0	0	0
T31	2130	0	0	0
T32	1038	2	0	0
T33	2520	0	0	0
T36	1379	0	0	0
T37	1722	0	0	0
T38	2667	0	0	0
T44	0	4	0	0
T72	0	1	0	0
T170	0	4	0	0
T171	0	3	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	2	0	0
T175	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260553703	156	0	0
T3	118542	0	0	0
T10	67061	0	0	0
T29	1423	2	0	0
T30	2259	0	0	0
T31	2130	0	0	0
T32	1038	2	0	0
T33	2520	0	0	0
T36	1379	0	0	0
T37	1722	0	0	0
T38	2667	0	0	0
T44	0	4	0	0
T72	0	1	0	0
T170	0	4	0	0
T171	0	3	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	2	0	0
T175	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T32
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	130276147	156	0	0
CgEnOn_A	130276147	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130276147	156	0	0
T3	59271	0	0	0
T10	33531	0	0	0
T29	711	2	0	0
T30	1129	0	0	0
T31	1065	0	0	0
T32	519	2	0	0
T33	1260	0	0	0
T36	688	0	0	0
T37	861	0	0	0
T38	1333	0	0	0
T44	0	4	0	0
T72	0	1	0	0
T170	0	4	0	0
T171	0	3	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	2	0	0
T175	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130276147	156	0	0
T3	59271	0	0	0
T10	33531	0	0	0
T29	711	2	0	0
T30	1129	0	0	0
T31	1065	0	0	0
T32	519	2	0	0
T33	1260	0	0	0
T36	688	0	0	0
T37	861	0	0	0
T38	1333	0	0	0
T44	0	4	0	0
T72	0	1	0	0
T170	0	4	0	0
T171	0	3	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	2	0	0
T175	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T32
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	522409370	156	0	0
CgEnOn_A	522409370	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522409370	156	0	0
T3	237122	0	0	0
T10	134174	0	0	0
T29	2939	2	0	0
T30	4568	0	0	0
T31	4217	0	0	0
T32	2155	2	0	0
T33	5161	0	0	0
T36	2623	0	0	0
T37	3276	0	0	0
T38	5413	0	0	0
T44	0	4	0	0
T72	0	1	0	0
T170	0	4	0	0
T171	0	3	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	2	0	0
T175	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522409370	151	0	0
T3	237122	0	0	0
T10	134174	0	0	0
T29	2939	2	0	0
T30	4568	0	0	0
T31	4217	0	0	0
T32	2155	2	0	0
T33	5161	0	0	0
T36	2623	0	0	0
T37	3276	0	0	0
T38	5413	0	0	0
T44	0	4	0	0
T170	0	4	0	0
T171	0	3	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	2	0	0
T175	0	3	0	0
T176	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T32
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	555622550	123	0	0
CgEnOn_A	555622550	122	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555622550	123	0	0
T3	247010	0	0	0
T10	139769	0	0	0
T29	3219	2	0	0
T30	4759	0	0	0
T31	4393	0	0	0
T32	2257	1	0	0
T33	5376	0	0	0
T36	2732	0	0	0
T37	3412	0	0	0
T38	5639	0	0	0
T44	0	2	0	0
T170	0	5	0	0
T171	0	2	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0
T176	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555622550	122	0	0
T3	247010	0	0	0
T10	139769	0	0	0
T29	3219	2	0	0
T30	4759	0	0	0
T31	4393	0	0	0
T32	2257	1	0	0
T33	5376	0	0	0
T36	2732	0	0	0
T37	3412	0	0	0
T38	5639	0	0	0
T44	0	2	0	0
T170	0	5	0	0
T171	0	2	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0
T176	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T32
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	130276147	156	0	0
CgEnOn_A	130276147	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130276147	156	0	0
T3	59271	0	0	0
T10	33531	0	0	0
T29	711	2	0	0
T30	1129	0	0	0
T31	1065	0	0	0
T32	519	2	0	0
T33	1260	0	0	0
T36	688	0	0	0
T37	861	0	0	0
T38	1333	0	0	0
T44	0	4	0	0
T72	0	1	0	0
T170	0	4	0	0
T171	0	3	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	2	0	0
T175	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130276147	156	0	0
T3	59271	0	0	0
T10	33531	0	0	0
T29	711	2	0	0
T30	1129	0	0	0
T31	1065	0	0	0
T32	519	2	0	0
T33	1260	0	0	0
T36	688	0	0	0
T37	861	0	0	0
T38	1333	0	0	0
T44	0	4	0	0
T72	0	1	0	0
T170	0	4	0	0
T171	0	3	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	2	0	0
T175	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T32
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	555622550	123	0	0
CgEnOn_A	555622550	122	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555622550	123	0	0
T3	247010	0	0	0
T10	139769	0	0	0
T29	3219	2	0	0
T30	4759	0	0	0
T31	4393	0	0	0
T32	2257	1	0	0
T33	5376	0	0	0
T36	2732	0	0	0
T37	3412	0	0	0
T38	5639	0	0	0
T44	0	2	0	0
T170	0	5	0	0
T171	0	2	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0
T176	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555622550	122	0	0
T3	247010	0	0	0
T10	139769	0	0	0
T29	3219	2	0	0
T30	4759	0	0	0
T31	4393	0	0	0
T32	2257	1	0	0
T33	5376	0	0	0
T36	2732	0	0	0
T37	3412	0	0	0
T38	5639	0	0	0
T44	0	2	0	0
T170	0	5	0	0
T171	0	2	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0
T176	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T32
1	0	Unreachable
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	130276147	156	0	0
CgEnOn_A	130276147	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130276147	156	0	0
T3	59271	0	0	0
T10	33531	0	0	0
T29	711	2	0	0
T30	1129	0	0	0
T31	1065	0	0	0
T32	519	2	0	0
T33	1260	0	0	0
T36	688	0	0	0
T37	861	0	0	0
T38	1333	0	0	0
T44	0	4	0	0
T72	0	1	0	0
T170	0	4	0	0
T171	0	3	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	2	0	0
T175	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130276147	156	0	0
T3	59271	0	0	0
T10	33531	0	0	0
T29	711	2	0	0
T30	1129	0	0	0
T31	1065	0	0	0
T32	519	2	0	0
T33	1260	0	0	0
T36	688	0	0	0
T37	861	0	0	0
T38	1333	0	0	0
T44	0	4	0	0
T72	0	1	0	0
T170	0	4	0	0
T171	0	3	0	0
T172	0	1	0	0
T173	0	3	0	0
T174	0	2	0	0
T175	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T32,T44
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	260553703	7681	0	0
CgEnOn_A	260553703	5488	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260553703	7681	0	0
T1	137734	62	0	0
T4	32129	1	0	0
T5	18632	1	0	0
T6	639	1	0	0
T7	2541	1	0	0
T17	1684	6	0	0
T18	51056	1	0	0
T19	2189	1	0	0
T20	788	14	0	0
T25	979	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260553703	5488	0	0
T1	137734	48	0	0
T2	113848	0	0	0
T11	0	50	0	0
T12	0	37	0	0
T17	1684	5	0	0
T18	51056	0	0	0
T19	2189	0	0	0
T20	788	13	0	0
T21	5250	0	0	0
T22	1214	0	0	0
T23	3165	0	0	0
T24	6684	6	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T38	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T32,T44
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	130276147	7680	0	0
CgEnOn_A	130276147	5487	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130276147	7680	0	0
T1	68863	63	0	0
T4	16064	1	0	0
T5	9316	1	0	0
T6	319	1	0	0
T7	1270	1	0	0
T17	842	6	0	0
T18	25528	1	0	0
T19	1095	1	0	0
T20	394	15	0	0
T25	489	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130276147	5487	0	0
T1	68863	49	0	0
T2	56924	0	0	0
T11	0	46	0	0
T12	0	35	0	0
T17	842	5	0	0
T18	25528	0	0	0
T19	1095	0	0	0
T20	394	14	0	0
T21	2624	0	0	0
T22	607	0	0	0
T23	1581	0	0	0
T24	3342	6	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T38	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T32,T44
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	522409370	7714	0	0
CgEnOn_A	522409370	5516	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522409370	7714	0	0
T1	276034	67	0	0
T4	64282	1	0	0
T5	37371	1	0	0
T6	1275	1	0	0
T7	4934	1	0	0
T17	3461	5	0	0
T18	102219	1	0	0
T19	4239	1	0	0
T20	1643	14	0	0
T25	1890	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522409370	5516	0	0
T1	276034	53	0	0
T2	227803	0	0	0
T11	0	56	0	0
T12	0	35	0	0
T17	3461	4	0	0
T18	102219	0	0	0
T19	4239	0	0	0
T20	1643	13	0	0
T21	9803	0	0	0
T22	2186	0	0	0
T23	5770	0	0	0
T24	13435	6	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T38	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T32,T44
1	0	Covered	T6,T7,T4
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	266466481	7742	0	0
CgEnOn_A	266466481	5540	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266466481	7742	0	0
T1	143784	62	0	0
T4	37903	1	0	0
T5	21566	1	0	0
T6	637	1	0	0
T7	2467	1	0	0
T17	1730	7	0	0
T18	51112	1	0	0
T19	2119	1	0	0
T20	821	15	0	0
T25	945	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266466481	5540	0	0
T1	143784	48	0	0
T2	113907	0	0	0
T11	0	57	0	0
T12	0	38	0	0
T17	1730	6	0	0
T18	51112	0	0	0
T19	2119	0	0	0
T20	821	14	0	0
T21	4902	0	0	0
T22	1092	0	0	0
T23	2885	0	0	0
T24	6717	6	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T32
1	0	Covered	T1,T33,T38
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	555622550	4083	0	0
CgEnOn_A	555622550	4082	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555622550	4083	0	0
T1	257544	11	0	0
T2	237303	0	0	0
T11	0	1	0	0
T12	0	14	0	0
T13	0	44	0	0
T17	3605	0	0	0
T18	118482	0	0	0
T19	4416	0	0	0
T20	1711	0	0	0
T21	10212	0	0	0
T22	2277	0	0	0
T23	6011	0	0	0
T24	13995	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T128	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555622550	4082	0	0
T1	257544	11	0	0
T2	237303	0	0	0
T11	0	1	0	0
T12	0	14	0	0
T13	0	44	0	0
T17	3605	0	0	0
T18	118482	0	0	0
T19	4416	0	0	0
T20	1711	0	0	0
T21	10212	0	0	0
T22	2277	0	0	0
T23	6011	0	0	0
T24	13995	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T128	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T32
1	0	Covered	T1,T33,T38
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	555622550	4129	0	0
CgEnOn_A	555622550	4128	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555622550	4129	0	0
T1	257544	14	0	0
T2	237303	0	0	0
T11	0	1	0	0
T12	0	17	0	0
T13	0	55	0	0
T17	3605	0	0	0
T18	118482	0	0	0
T19	4416	0	0	0
T20	1711	0	0	0
T21	10212	0	0	0
T22	2277	0	0	0
T23	6011	0	0	0
T24	13995	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T78	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555622550	4128	0	0
T1	257544	14	0	0
T2	237303	0	0	0
T11	0	1	0	0
T12	0	17	0	0
T13	0	55	0	0
T17	3605	0	0	0
T18	118482	0	0	0
T19	4416	0	0	0
T20	1711	0	0	0
T21	10212	0	0	0
T22	2277	0	0	0
T23	6011	0	0	0
T24	13995	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T78	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T32
1	0	Covered	T1,T33,T38
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	555622550	4156	0	0
CgEnOn_A	555622550	4155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555622550	4156	0	0
T1	257544	14	0	0
T2	237303	0	0	0
T11	0	1	0	0
T12	0	16	0	0
T13	0	41	0	0
T17	3605	0	0	0
T18	118482	0	0	0
T19	4416	0	0	0
T20	1711	0	0	0
T21	10212	0	0	0
T22	2277	0	0	0
T23	6011	0	0	0
T24	13995	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T128	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555622550	4155	0	0
T1	257544	14	0	0
T2	237303	0	0	0
T11	0	1	0	0
T12	0	16	0	0
T13	0	41	0	0
T17	3605	0	0	0
T18	118482	0	0	0
T19	4416	0	0	0
T20	1711	0	0	0
T21	10212	0	0	0
T22	2277	0	0	0
T23	6011	0	0	0
T24	13995	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T128	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T32
1	0	Covered	T1,T33,T38
1	1	Covered	T6,T7,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	555622550	4137	0	0
CgEnOn_A	555622550	4136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555622550	4137	0	0
T1	257544	11	0	0
T2	237303	0	0	0
T11	0	1	0	0
T12	0	13	0	0
T13	0	51	0	0
T17	3605	0	0	0
T18	118482	0	0	0
T19	4416	0	0	0
T20	1711	0	0	0
T21	10212	0	0	0
T22	2277	0	0	0
T23	6011	0	0	0
T24	13995	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T128	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555622550	4136	0	0
T1	257544	11	0	0
T2	237303	0	0	0
T11	0	1	0	0
T12	0	13	0	0
T13	0	51	0	0
T17	3605	0	0	0
T18	118482	0	0	0
T19	4416	0	0	0
T20	1711	0	0	0
T21	10212	0	0	0
T22	2277	0	0	0
T23	6011	0	0	0
T24	13995	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T76	0	1	0	0
T128	0	1	0	0