Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T20
0	1	Covered	T1,T17,T20
1	0	Covered	T6,T7,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T20
1	0	Covered	T29,T32,T44
1	1	Covered	T6,T7,T5

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1179707387	14148	0	0
GateOpen_A	1179707387	14148	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1179707387	14148	0	0
T1	626416	121	0	0
T2	512485	0	0	0
T11	0	118	0	0
T12	0	111	0	0
T17	7719	4	0	0
T18	229918	0	0	0
T19	9643	0	0	0
T20	3648	26	0	0
T21	22581	0	0	0
T22	5100	0	0	0
T23	13403	0	0	0
T24	30182	13	0	0
T29	0	8	0	0
T32	0	7	0	0
T33	0	4	0	0
T38	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1179707387	14148	0	0
T1	626416	121	0	0
T2	512485	0	0	0
T11	0	118	0	0
T12	0	111	0	0
T17	7719	4	0	0
T18	229918	0	0	0
T19	9643	0	0	0
T20	3648	26	0	0
T21	22581	0	0	0
T22	5100	0	0	0
T23	13403	0	0	0
T24	30182	13	0	0
T29	0	8	0	0
T32	0	7	0	0
T33	0	4	0	0
T38	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T20
0	1	Covered	T1,T17,T20
1	0	Covered	T6,T7,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T20
1	0	Covered	T29,T32,T44
1	1	Covered	T6,T7,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	130276561	3520	0	0
GateOpen_A	130276561	3520	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130276561	3520	0	0
T1	68863	30	0	0
T2	56925	0	0	0
T11	0	27	0	0
T12	0	26	0	0
T17	842	1	0	0
T18	25529	0	0	0
T19	1095	0	0	0
T20	395	7	0	0
T21	2625	0	0	0
T22	607	0	0	0
T23	1582	0	0	0
T24	3343	3	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T38	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130276561	3520	0	0
T1	68863	30	0	0
T2	56925	0	0	0
T11	0	27	0	0
T12	0	26	0	0
T17	842	1	0	0
T18	25529	0	0	0
T19	1095	0	0	0
T20	395	7	0	0
T21	2625	0	0	0
T22	607	0	0	0
T23	1582	0	0	0
T24	3343	3	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T38	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T20
0	1	Covered	T1,T17,T20
1	0	Covered	T6,T7,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T20
1	0	Covered	T29,T32,T44
1	1	Covered	T6,T7,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	260554101	3523	0	0
GateOpen_A	260554101	3523	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260554101	3523	0	0
T1	137735	31	0	0
T2	113849	0	0	0
T11	0	27	0	0
T12	0	27	0	0
T17	1684	1	0	0
T18	51057	0	0	0
T19	2190	0	0	0
T20	789	7	0	0
T21	5251	0	0	0
T22	1214	0	0	0
T23	3165	0	0	0
T24	6685	3	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T38	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260554101	3523	0	0
T1	137735	31	0	0
T2	113849	0	0	0
T11	0	27	0	0
T12	0	27	0	0
T17	1684	1	0	0
T18	51057	0	0	0
T19	2190	0	0	0
T20	789	7	0	0
T21	5251	0	0	0
T22	1214	0	0	0
T23	3165	0	0	0
T24	6685	3	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T38	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T20
0	1	Covered	T1,T17,T20
1	0	Covered	T6,T7,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T20
1	0	Covered	T29,T32,T44
1	1	Covered	T6,T7,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	522409809	3530	0	0
GateOpen_A	522409809	3530	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522409809	3530	0	0
T1	276034	31	0	0
T2	227804	0	0	0
T11	0	33	0	0
T12	0	27	0	0
T17	3462	1	0	0
T18	102220	0	0	0
T19	4239	0	0	0
T20	1643	5	0	0
T21	9803	0	0	0
T22	2186	0	0	0
T23	5770	0	0	0
T24	13436	3	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T38	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522409809	3530	0	0
T1	276034	31	0	0
T2	227804	0	0	0
T11	0	33	0	0
T12	0	27	0	0
T17	3462	1	0	0
T18	102220	0	0	0
T19	4239	0	0	0
T20	1643	5	0	0
T21	9803	0	0	0
T22	2186	0	0	0
T23	5770	0	0	0
T24	13436	3	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T38	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T20
0	1	Covered	T1,T17,T20
1	0	Covered	T6,T7,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T20
1	0	Covered	T29,T32,T44
1	1	Covered	T6,T7,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	266466916	3575	0	0
GateOpen_A	266466916	3575	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266466916	3575	0	0
T1	143784	29	0	0
T2	113907	0	0	0
T11	0	31	0	0
T12	0	31	0	0
T17	1731	1	0	0
T18	51112	0	0	0
T19	2119	0	0	0
T20	821	7	0	0
T21	4902	0	0	0
T22	1093	0	0	0
T23	2886	0	0	0
T24	6718	4	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266466916	3575	0	0
T1	143784	29	0	0
T2	113907	0	0	0
T11	0	31	0	0
T12	0	31	0	0
T17	1731	1	0	0
T18	51112	0	0	0
T19	2119	0	0	0
T20	821	7	0	0
T21	4902	0	0	0
T22	1093	0	0	0
T23	2886	0	0	0
T24	6718	4	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0