Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	701573	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4266951

1

T6

26

T4

33

T7

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1211985	1			T6	42		T4	8		T7	24
values[0x0]	1726705	1			T6	21		T4	29		T7	11
values[0x1]	2029834	1			T6	18		T4	15		T7	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	379956	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4588568

1

T6

33

T4

40

T7

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19283	1			T1	447		T2	405		T24	2
valid_sources[0x01]	21386	1			T1	440		T5	1		T18	6
valid_sources[0x02]	18900	1			T1	473		T18	3		T2	448
valid_sources[0x03]	19795	1			T1	438		T5	2		T18	3
valid_sources[0x04]	19784	1			T1	477		T2	475		T24	2
valid_sources[0x05]	18877	1			T1	424		T5	2		T20	1
valid_sources[0x06]	18833	1			T1	432		T2	466		T70	1
valid_sources[0x07]	19659	1			T7	3		T1	441		T5	1
valid_sources[0x08]	18768	1			T25	1		T1	411		T18	1
valid_sources[0x09]	19285	1			T1	420		T5	3		T19	1
valid_sources[0x0a]	18158	1			T4	3		T1	449		T5	4
valid_sources[0x0b]	18957	1			T4	1		T1	409		T2	438
valid_sources[0x0c]	19669	1			T1	423		T2	433		T69	8
valid_sources[0x0d]	20281	1			T4	4		T25	2		T1	446
valid_sources[0x0e]	19806	1			T25	1		T26	14		T1	441
valid_sources[0x0f]	18528	1			T1	458		T5	3		T19	1
valid_sources[0x10]	18095	1			T1	451		T2	383		T70	1
valid_sources[0x11]	18780	1			T1	450		T19	1		T2	430
valid_sources[0x12]	19549	1			T25	3		T1	463		T2	432
valid_sources[0x13]	20496	1			T1	472		T5	2		T2	434
valid_sources[0x14]	18952	1			T1	464		T2	459		T70	1
valid_sources[0x15]	20039	1			T1	436		T2	463		T69	11
valid_sources[0x16]	19030	1			T4	1		T1	473		T2	460
valid_sources[0x17]	20429	1			T1	431		T2	506		T21	2
valid_sources[0x18]	18903	1			T1	413		T19	1		T2	444
valid_sources[0x19]	18267	1			T1	422		T2	442		T29	5
valid_sources[0x1a]	18300	1			T1	433		T2	452		T29	7
valid_sources[0x1b]	19487	1			T1	453		T2	429		T21	1
valid_sources[0x1c]	20788	1			T4	1		T1	440		T2	404
valid_sources[0x1d]	20098	1			T26	2		T1	449		T2	462
valid_sources[0x1e]	19091	1			T1	480		T2	379		T70	1
valid_sources[0x1f]	20338	1			T1	435		T2	503		T29	1
valid_sources[0x20]	18017	1			T1	456		T5	3		T18	2
valid_sources[0x21]	18188	1			T1	449		T5	1		T2	426
valid_sources[0x22]	19258	1			T1	444		T5	4		T18	2
valid_sources[0x23]	19486	1			T1	426		T2	463		T70	1
valid_sources[0x24]	18515	1			T1	462		T19	1		T2	464
valid_sources[0x25]	20063	1			T25	1		T1	484		T2	412
valid_sources[0x26]	19677	1			T1	391		T2	475		T24	1
valid_sources[0x27]	21267	1			T1	462		T18	2		T2	427
valid_sources[0x28]	19747	1			T1	452		T2	412		T29	3
valid_sources[0x29]	20009	1			T25	1		T1	444		T2	453
valid_sources[0x2a]	18956	1			T1	435		T2	428		T24	1
valid_sources[0x2b]	20943	1			T7	11		T25	2		T1	454
valid_sources[0x2c]	19794	1			T1	438		T2	472		T21	1
valid_sources[0x2d]	21201	1			T1	470		T5	1		T2	474
valid_sources[0x2e]	19116	1			T1	457		T2	432		T29	1
valid_sources[0x2f]	21174	1			T1	471		T18	2		T2	553
valid_sources[0x30]	20977	1			T7	2		T25	2		T26	3
valid_sources[0x31]	18675	1			T7	2		T1	435		T2	402
valid_sources[0x32]	19316	1			T1	466		T20	1		T2	411
valid_sources[0x33]	19142	1			T1	434		T18	3		T20	2
valid_sources[0x34]	17762	1			T1	408		T2	446		T24	3
valid_sources[0x35]	17257	1			T1	438		T5	2		T20	2
valid_sources[0x36]	18201	1			T7	1		T1	424		T18	2
valid_sources[0x37]	19986	1			T1	426		T2	531		T70	1
valid_sources[0x38]	19564	1			T1	429		T2	428		T22	29
valid_sources[0x39]	18690	1			T4	1		T1	435		T18	2
valid_sources[0x3a]	19865	1			T1	462		T5	4		T2	475
valid_sources[0x3b]	19557	1			T4	2		T1	440		T5	5
valid_sources[0x3c]	19539	1			T1	432		T5	1		T2	457
valid_sources[0x3d]	19222	1			T1	462		T5	2		T19	1
valid_sources[0x3e]	20029	1			T1	457		T18	2		T20	2
valid_sources[0x3f]	19420	1			T1	427		T5	1		T2	461
valid_sources[0x40]	19765	1			T1	426		T5	8		T2	444
valid_sources[0x41]	19754	1			T1	456		T5	2		T20	1
valid_sources[0x42]	18732	1			T25	3		T1	451		T2	403
valid_sources[0x43]	19317	1			T1	463		T5	1		T2	479
valid_sources[0x44]	18979	1			T1	433		T2	429		T24	2
valid_sources[0x45]	20323	1			T1	430		T2	456		T24	2
valid_sources[0x46]	19448	1			T1	470		T2	384		T21	2
valid_sources[0x47]	21089	1			T1	453		T20	1		T2	419
valid_sources[0x48]	20374	1			T4	1		T1	449		T19	1
valid_sources[0x49]	17831	1			T7	2		T25	2		T1	463
valid_sources[0x4a]	19551	1			T25	2		T1	436		T2	409
valid_sources[0x4b]	19126	1			T25	1		T1	418		T5	4
valid_sources[0x4c]	19355	1			T1	401		T2	460		T24	1
valid_sources[0x4d]	18607	1			T1	443		T2	424		T24	1
valid_sources[0x4e]	19748	1			T1	435		T2	427		T24	1
valid_sources[0x4f]	19777	1			T1	420		T19	1		T2	453
valid_sources[0x50]	17691	1			T1	423		T5	6		T2	414
valid_sources[0x51]	19489	1			T1	428		T2	468		T24	1
valid_sources[0x52]	19307	1			T25	2		T1	461		T19	3
valid_sources[0x53]	19935	1			T1	454		T2	417		T21	2
valid_sources[0x54]	19022	1			T4	2		T7	2		T1	434
valid_sources[0x55]	20084	1			T1	435		T2	382		T29	2
valid_sources[0x56]	18796	1			T1	412		T18	2		T2	410
valid_sources[0x57]	19887	1			T1	442		T5	1		T2	440
valid_sources[0x58]	18989	1			T1	435		T5	1		T20	1
valid_sources[0x59]	20626	1			T7	2		T1	452		T2	470
valid_sources[0x5a]	18732	1			T1	438		T2	464		T70	2
valid_sources[0x5b]	18849	1			T4	1		T1	416		T2	428
valid_sources[0x5c]	21184	1			T1	417		T5	8		T20	3
valid_sources[0x5d]	17830	1			T1	443		T2	429		T29	10
valid_sources[0x5e]	18833	1			T25	2		T1	465		T2	457
valid_sources[0x5f]	19717	1			T25	1		T1	417		T2	420
valid_sources[0x60]	18727	1			T1	440		T5	1		T20	1
valid_sources[0x61]	19411	1			T4	1		T1	415		T19	1
valid_sources[0x62]	20420	1			T1	451		T2	442		T21	3
valid_sources[0x63]	19080	1			T1	399		T18	9		T2	419
valid_sources[0x64]	18894	1			T1	417		T2	492		T24	1
valid_sources[0x65]	18751	1			T4	2		T1	418		T2	444
valid_sources[0x66]	18683	1			T1	446		T18	1		T2	459
valid_sources[0x67]	20067	1			T25	2		T1	468		T5	2
valid_sources[0x68]	19162	1			T1	440		T5	2		T2	457
valid_sources[0x69]	18949	1			T1	422		T5	1		T2	474
valid_sources[0x6a]	19249	1			T4	2		T1	419		T2	445
valid_sources[0x6b]	19049	1			T1	415		T5	2		T2	513
valid_sources[0x6c]	20060	1			T4	1		T1	410		T2	412
valid_sources[0x6d]	21031	1			T1	423		T2	415		T24	1
valid_sources[0x6e]	18348	1			T1	458		T2	500		T29	4
valid_sources[0x6f]	19550	1			T1	483		T5	2		T2	410
valid_sources[0x70]	18397	1			T1	389		T2	423		T11	117
valid_sources[0x71]	19626	1			T1	435		T2	424		T24	1
valid_sources[0x72]	19643	1			T1	447		T5	2		T18	2
valid_sources[0x73]	18597	1			T1	404		T5	2		T2	432
valid_sources[0x74]	19045	1			T7	4		T1	470		T2	449
valid_sources[0x75]	18896	1			T7	3		T1	435		T2	475
valid_sources[0x76]	19549	1			T25	4		T1	448		T19	1
valid_sources[0x77]	18469	1			T25	1		T1	423		T5	3
valid_sources[0x78]	19420	1			T1	447		T2	430		T24	2
valid_sources[0x79]	19411	1			T1	471		T2	509		T21	1
valid_sources[0x7a]	19174	1			T1	422		T5	3		T2	389
valid_sources[0x7b]	19115	1			T25	2		T1	437		T5	9
valid_sources[0x7c]	19438	1			T4	1		T25	2		T1	444
valid_sources[0x7d]	19290	1			T1	443		T2	482		T24	2
valid_sources[0x7e]	20240	1			T1	438		T5	1		T2	468
valid_sources[0x7f]	19008	1			T1	433		T2	445		T29	3
valid_sources[0x80]	18632	1			T25	8		T1	451		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1072344

1

T6

20

T4

7

T7

10

values[0x0]

all_enables

biggest_size

1622932

1

T6

6

T4

19

T7

6

values[0x1]

all_enables

biggest_size

1571675

1

T4

7

T7

1

T25

2