Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	919910550	80975	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	919910550	80975	0	0
T1	1556795	1399	0	0
T2	2203515	2286	0	0
T3	0	109	0	0
T5	64545	0	0	0
T11	0	712	0	0
T12	0	69	0	0
T13	0	340	0	0
T14	0	814	0	0
T15	0	759	0	0
T16	0	1609	0	0
T17	0	215	0	0
T18	10695	0	0	0
T19	9360	0	0	0
T20	10510	0	0	0
T21	10100	0	0	0
T22	6500	0	0	0
T23	4110	0	0	0
T24	476025	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	183982110	12179	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183982110	12179	0	0
T1	311359	219	0	0
T2	440703	295	0	0
T3	0	14	0	0
T5	12909	0	0	0
T11	0	112	0	0
T12	0	13	0	0
T13	0	45	0	0
T14	0	123	0	0
T15	0	96	0	0
T16	0	260	0	0
T17	0	35	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T21	2020	0	0	0
T22	1300	0	0	0
T23	822	0	0	0
T24	95205	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	183982110	16250	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183982110	16250	0	0
T1	311359	280	0	0
T2	440703	461	0	0
T3	0	23	0	0
T5	12909	0	0	0
T11	0	143	0	0
T12	0	13	0	0
T13	0	66	0	0
T14	0	162	0	0
T15	0	149	0	0
T16	0	325	0	0
T17	0	44	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T21	2020	0	0	0
T22	1300	0	0	0
T23	822	0	0	0
T24	95205	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	183982110	24204	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183982110	24204	0	0
T1	311359	404	0	0
T2	440703	748	0	0
T3	0	36	0	0
T5	12909	0	0	0
T11	0	203	0	0
T12	0	17	0	0
T13	0	115	0	0
T14	0	247	0	0
T15	0	253	0	0
T16	0	448	0	0
T17	0	57	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T21	2020	0	0	0
T22	1300	0	0	0
T23	822	0	0	0
T24	95205	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	183982110	12042	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183982110	12042	0	0
T1	311359	219	0	0
T2	440703	328	0	0
T3	0	14	0	0
T5	12909	0	0	0
T11	0	110	0	0
T12	0	13	0	0
T13	0	44	0	0
T14	0	121	0	0
T15	0	109	0	0
T16	0	253	0	0
T17	0	35	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T21	2020	0	0	0
T22	1300	0	0	0
T23	822	0	0	0
T24	95205	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	183982110	16300	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183982110	16300	0	0
T1	311359	277	0	0
T2	440703	454	0	0
T3	0	22	0	0
T5	12909	0	0	0
T11	0	144	0	0
T12	0	13	0	0
T13	0	70	0	0
T14	0	161	0	0
T15	0	152	0	0
T16	0	323	0	0
T17	0	44	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T21	2020	0	0	0
T22	1300	0	0	0
T23	822	0	0	0
T24	95205	0	0	0