Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T1,T5,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	183982110	181671665	0	0
AllClkBypReqTrue_A	183982110	145442	0	0
IoClkBypReqFalse_A	183982110	181586468	0	2415
IoClkBypReqTrue_A	183982110	226117	0	0
LcClkBypAckFalse_A	183982110	181685651	0	0
LcClkBypAckTrue_A	183982110	131456	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183982110	181671665	0	0
T1	311359	310937	0	0
T4	5453	5405	0	0
T5	12909	2243	0	0
T6	1168	1156	0	0
T7	1296	1250	0	0
T18	2139	1941	0	0
T19	1872	1631	0	0
T20	2102	1983	0	0
T25	2033	1921	0	0
T26	1797	1518	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183982110	145442	0	0
T1	311359	1964	0	0
T2	440703	1221	0	0
T3	0	380	0	0
T5	12909	0	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T21	2020	0	0	0
T22	1300	0	0	0
T23	822	4	0	0
T26	1797	247	0	0
T64	0	20	0	0
T68	0	305	0	0
T70	0	399	0	0
T84	0	137	0	0
T104	0	56	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183982110	181586468	0	2415
T1	311359	310799	0	3
T4	5453	5403	0	3
T5	12909	2233	0	3
T6	1168	1154	0	3
T7	1296	1248	0	3
T18	2139	1939	0	3
T19	1872	1629	0	3
T20	2102	1669	0	3
T25	2033	1919	0	3
T26	1797	1491	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183982110	226117	0	0
T1	311359	3333	0	0
T2	440703	1537	0	0
T3	0	683	0	0
T5	12909	0	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	312	0	0
T21	2020	398	0	0
T22	1300	0	0	0
T23	822	0	0	0
T26	1797	272	0	0
T64	0	334	0	0
T68	0	343	0	0
T70	0	669	0	0
T84	0	208	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183982110	181685651	0	0
T1	311359	310936	0	0
T4	5453	5405	0	0
T5	12909	2243	0	0
T6	1168	1156	0	0
T7	1296	1250	0	0
T18	2139	1941	0	0
T19	1872	1631	0	0
T20	2102	1797	0	0
T25	2033	1921	0	0
T26	1797	1695	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183982110	131456	0	0
T1	311359	1976	0	0
T2	440703	1062	0	0
T3	0	392	0	0
T5	12909	0	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	186	0	0
T21	2020	196	0	0
T22	1300	0	0	0
T23	822	0	0	0
T26	1797	70	0	0
T64	0	143	0	0
T68	0	168	0	0
T70	0	468	0	0
T84	0	112	0	0