Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16354	0	0
TransStop_A	2147483647	8391	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16354	0	0
T1	3636684	268	0	0
T2	0	453	0	0
T3	0	16	0	0
T4	90908	0	0	0
T5	107580	0	0	0
T6	77948	4	0	0
T7	20752	11	0	0
T11	0	144	0	0
T18	8560	4	0	0
T19	7492	0	0	0
T20	17160	0	0	0
T25	16596	4	0	0
T26	28768	0	0	0
T69	0	32	0	0
T71	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8391	0	0
T1	3636684	162	0	0
T2	0	209	0	0
T3	0	12	0	0
T4	90908	0	0	0
T5	107580	0	0	0
T6	77948	4	0	0
T7	20752	6	0	0
T11	0	75	0	0
T18	8560	4	0	0
T19	7492	0	0	0
T20	17160	0	0	0
T25	16596	4	0	0
T26	28768	0	0	0
T69	0	18	0	0
T71	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	707120644	4060	0	0
TransStop_A	707120644	2088	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120644	4060	0	0
T1	909171	65	0	0
T2	0	108	0	0
T3	0	4	0	0
T4	22727	0	0	0
T5	26895	0	0	0
T6	19487	1	0	0
T7	5188	2	0	0
T11	0	33	0	0
T18	2140	1	0	0
T19	1873	0	0	0
T20	4290	0	0	0
T25	4149	1	0	0
T26	7192	0	0	0
T69	0	6	0	0
T71	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120644	2088	0	0
T1	909171	38	0	0
T2	0	50	0	0
T3	0	3	0	0
T4	22727	0	0	0
T5	26895	0	0	0
T6	19487	1	0	0
T7	5188	1	0	0
T11	0	20	0	0
T18	2140	1	0	0
T19	1873	0	0	0
T20	4290	0	0	0
T25	4149	1	0	0
T26	7192	0	0	0
T69	0	3	0	0
T71	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	707120644	4033	0	0
TransStop_A	707120644	2112	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120644	4033	0	0
T1	909171	67	0	0
T2	0	123	0	0
T3	0	4	0	0
T4	22727	0	0	0
T5	26895	0	0	0
T6	19487	1	0	0
T7	5188	5	0	0
T11	0	37	0	0
T18	2140	1	0	0
T19	1873	0	0	0
T20	4290	0	0	0
T25	4149	1	0	0
T26	7192	0	0	0
T69	0	7	0	0
T71	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120644	2112	0	0
T1	909171	42	0	0
T2	0	54	0	0
T3	0	3	0	0
T4	22727	0	0	0
T5	26895	0	0	0
T6	19487	1	0	0
T7	5188	3	0	0
T11	0	18	0	0
T18	2140	1	0	0
T19	1873	0	0	0
T20	4290	0	0	0
T25	4149	1	0	0
T26	7192	0	0	0
T69	0	5	0	0
T71	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	707120644	4168	0	0
TransStop_A	707120644	2101	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120644	4168	0	0
T1	909171	69	0	0
T2	0	108	0	0
T3	0	4	0	0
T4	22727	0	0	0
T5	26895	0	0	0
T6	19487	1	0	0
T7	5188	3	0	0
T11	0	38	0	0
T18	2140	1	0	0
T19	1873	0	0	0
T20	4290	0	0	0
T25	4149	1	0	0
T26	7192	0	0	0
T69	0	6	0	0
T71	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120644	2101	0	0
T1	909171	42	0	0
T2	0	50	0	0
T3	0	3	0	0
T4	22727	0	0	0
T5	26895	0	0	0
T6	19487	1	0	0
T7	5188	1	0	0
T11	0	19	0	0
T18	2140	1	0	0
T19	1873	0	0	0
T20	4290	0	0	0
T25	4149	1	0	0
T26	7192	0	0	0
T69	0	2	0	0
T71	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	707120644	4093	0	0
TransStop_A	707120644	2090	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120644	4093	0	0
T1	909171	67	0	0
T2	0	114	0	0
T3	0	4	0	0
T4	22727	0	0	0
T5	26895	0	0	0
T6	19487	1	0	0
T7	5188	1	0	0
T11	0	36	0	0
T18	2140	1	0	0
T19	1873	0	0	0
T20	4290	0	0	0
T25	4149	1	0	0
T26	7192	0	0	0
T69	0	13	0	0
T71	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120644	2090	0	0
T1	909171	40	0	0
T2	0	55	0	0
T3	0	3	0	0
T4	22727	0	0	0
T5	26895	0	0	0
T6	19487	1	0	0
T7	5188	1	0	0
T11	0	18	0	0
T18	2140	1	0	0
T19	1873	0	0	0
T20	4290	0	0	0
T25	4149	1	0	0
T26	7192	0	0	0
T69	0	8	0	0
T71	0	1	0	0