Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	183982110	27498123	0	55

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183982110	27498123	0	55
T1	311359	109732	0	0
T2	440703	441227	0	0
T3	0	12622	0	0
T4	5453	754	0	1
T5	12909	0	0	0
T7	1296	0	0	0
T11	0	54496	0	0
T12	0	3438	0	1
T13	0	36853	0	1
T14	0	591770	0	0
T15	0	84482	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T25	2033	0	0	0
T26	1797	0	0	0
T27	0	737	0	1
T31	0	0	0	1
T32	0	0	0	1
T36	0	0	0	1
T105	0	0	0	1
T106	0	0	0	1
T107	0	0	0	1