Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	184902954	6242855	0	0
clk_enables_rd_A	184902954	48582	0	0
clk_hints_rd_A	184902954	43636	0	0
extclk_ctrl_rd_A	184902954	51959	0	0
extclk_ctrl_regwen_rd_A	184902954	40878	0	0
jitter_enable_rd_A	184902954	55037	0	0
jitter_regwen_rd_A	184902954	46793	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	6242855	0	0
T1	311359	150238	0	0
T2	440703	153063	0	0
T5	12909	0	0	0
T11	0	33323	0	0
T14	0	72013	0	0
T16	0	211668	0	0
T17	0	49670	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T21	2020	0	0	0
T22	1300	0	0	0
T23	822	0	0	0
T24	95205	0	0	0
T33	0	155491	0	0
T65	0	75663	0	0
T66	0	143761	0	0
T67	0	91534	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	48582	0	0
T1	311359	0	0	0
T2	440703	0	0	0
T3	0	8	0	0
T5	12909	0	0	0
T11	0	1470	0	0
T14	0	1517	0	0
T17	0	2087	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T21	2020	0	0	0
T22	1300	0	0	0
T25	2033	2	0	0
T26	1797	0	0	0
T33	0	6093	0	0
T67	0	2169	0	0
T103	0	11	0	0
T122	0	3	0	0
T123	0	756	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	43636	0	0
T1	311359	0	0	0
T2	440703	0	0	0
T3	0	13	0	0
T5	12909	0	0	0
T11	0	1368	0	0
T14	0	1330	0	0
T17	0	1769	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T21	2020	0	0	0
T22	1300	0	0	0
T25	2033	1	0	0
T26	1797	0	0	0
T33	0	5224	0	0
T67	0	1720	0	0
T103	0	16	0	0
T122	0	2	0	0
T124	0	7	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	51959	0	0
T3	332000	73	0	0
T8	44374	0	0	0
T11	0	1489	0	0
T14	0	1578	0	0
T29	7269	0	0	0
T34	1930	0	0	0
T48	0	53	0	0
T64	2408	43	0	0
T68	2126	39	0	0
T69	2552	0	0	0
T70	2829	59	0	0
T71	1363	0	0	0
T72	0	39	0	0
T84	1541	0	0	0
T125	0	3	0	0
T126	0	10	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	40878	0	0
T11	117462	1141	0	0
T12	13616	0	0	0
T14	0	1414	0	0
T17	0	1851	0	0
T30	16799	0	0	0
T33	0	5095	0	0
T39	1097	0	0	0
T67	0	1795	0	0
T73	0	3	0	0
T74	0	30	0	0
T125	1130	0	0	0
T127	0	50	0	0
T128	0	40	0	0
T129	0	42	0	0
T130	2024	0	0	0
T131	2461	0	0	0
T132	1524	0	0	0
T133	965	0	0	0
T134	1073	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	55037	0	0
T1	311359	0	0	0
T2	440703	0	0	0
T3	0	234	0	0
T5	12909	0	0	0
T11	0	1503	0	0
T14	0	1914	0	0
T17	0	2009	0	0
T18	2139	0	0	0
T19	1872	0	0	0
T20	2102	0	0	0
T21	2020	0	0	0
T22	1300	0	0	0
T25	2033	103	0	0
T26	1797	0	0	0
T33	0	6414	0	0
T103	0	466	0	0
T122	0	129	0	0
T124	0	156	0	0
T135	0	85	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184902954	46793	0	0
T11	117462	1433	0	0
T12	13616	0	0	0
T14	0	1508	0	0
T17	0	2044	0	0
T30	16799	0	0	0
T33	0	6141	0	0
T39	1097	0	0	0
T67	0	1926	0	0
T123	0	759	0	0
T125	1130	0	0	0
T130	2024	0	0	0
T131	2461	0	0	0
T132	1524	0	0	0
T133	965	0	0	0
T134	1073	0	0	0
T136	0	3565	0	0
T137	0	1367	0	0
T138	0	3510	0	0
T139	0	4217	0	0