Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T26
1	0	Covered	T26,T1,T20
1	1	Covered	T26,T1,T20

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	667038212	5000	0	0
g_div2.Div2Whole_A	667038212	5830	0	0
g_div4.Div4Stepped_A	332829454	4901	0	0
g_div4.Div4Whole_A	332829454	5590	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667038212	5000	0	0
T1	852041	89	0	0
T2	405782	32	0	0
T3	0	10	0	0
T5	25818	0	0	0
T18	2055	0	0	0
T19	1799	0	0	0
T20	4119	8	0	0
T21	8084	10	0	0
T22	5678	0	0	0
T23	2923	0	0	0
T26	6904	6	0	0
T64	0	4	0	0
T68	0	4	0	0
T70	0	14	0	0
T84	0	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667038212	5830	0	0
T1	852041	111	0	0
T2	405782	41	0	0
T3	0	17	0	0
T5	25818	0	0	0
T18	2055	0	0	0
T19	1799	0	0	0
T20	4119	9	0	0
T21	8084	12	0	0
T22	5678	0	0	0
T23	2923	0	0	0
T26	6904	7	0	0
T64	0	5	0	0
T68	0	6	0	0
T70	0	14	0	0
T84	0	7	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332829454	4901	0	0
T1	426342	88	0	0
T2	202427	31	0	0
T3	0	9	0	0
T5	8318	0	0	0
T18	988	0	0	0
T19	839	0	0	0
T20	2204	8	0	0
T21	4440	10	0	0
T22	2772	0	0	0
T23	1449	0	0	0
T26	3894	6	0	0
T64	0	4	0	0
T68	0	4	0	0
T70	0	14	0	0
T84	0	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332829454	5590	0	0
T1	426342	111	0	0
T2	202427	35	0	0
T3	0	15	0	0
T5	8318	0	0	0
T18	988	0	0	0
T19	839	0	0	0
T20	2204	9	0	0
T21	4440	12	0	0
T22	2772	0	0	0
T23	1449	0	0	0
T26	3894	6	0	0
T64	0	5	0	0
T68	0	5	0	0
T70	0	13	0	0
T84	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T26
1	0	Covered	T26,T1,T20
1	1	Covered	T26,T1,T20

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	667038212	5000	0	0
g_div2.Div2Whole_A	667038212	5830	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667038212	5000	0	0
T1	852041	89	0	0
T2	405782	32	0	0
T3	0	10	0	0
T5	25818	0	0	0
T18	2055	0	0	0
T19	1799	0	0	0
T20	4119	8	0	0
T21	8084	10	0	0
T22	5678	0	0	0
T23	2923	0	0	0
T26	6904	6	0	0
T64	0	4	0	0
T68	0	4	0	0
T70	0	14	0	0
T84	0	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667038212	5830	0	0
T1	852041	111	0	0
T2	405782	41	0	0
T3	0	17	0	0
T5	25818	0	0	0
T18	2055	0	0	0
T19	1799	0	0	0
T20	4119	9	0	0
T21	8084	12	0	0
T22	5678	0	0	0
T23	2923	0	0	0
T26	6904	7	0	0
T64	0	5	0	0
T68	0	6	0	0
T70	0	14	0	0
T84	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T26
1	0	Covered	T26,T1,T20
1	1	Covered	T26,T1,T20

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	332829454	4901	0	0
g_div4.Div4Whole_A	332829454	5590	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332829454	4901	0	0
T1	426342	88	0	0
T2	202427	31	0	0
T3	0	9	0	0
T5	8318	0	0	0
T18	988	0	0	0
T19	839	0	0	0
T20	2204	8	0	0
T21	4440	10	0	0
T22	2772	0	0	0
T23	1449	0	0	0
T26	3894	6	0	0
T64	0	4	0	0
T68	0	4	0	0
T70	0	14	0	0
T84	0	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332829454	5590	0	0
T1	426342	111	0	0
T2	202427	35	0	0
T3	0	15	0	0
T5	8318	0	0	0
T18	988	0	0	0
T19	839	0	0	0
T20	2204	9	0	0
T21	4440	12	0	0
T22	2772	0	0	0
T23	1449	0	0	0
T26	3894	6	0	0
T64	0	5	0	0
T68	0	5	0	0
T70	0	13	0	0
T84	0	7	0	0