Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	49735	0	0
CgEnOn_A	2147483647	40694	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49735	0	0
T1	3309895	368	0	0
T2	0	108	0	0
T4	83570	3	0	0
T5	92082	15	0	0
T6	71659	7	0	0
T7	19052	5	0	0
T11	466986	0	0	0
T12	430138	0	0	0
T18	7813	7	0	0
T19	6800	43	0	0
T20	16000	3	0	0
T25	15164	7	0	0
T26	27127	3	0	0
T30	134430	0	0	0
T39	6775	5	0	0
T40	0	20	0	0
T41	0	15	0	0
T67	0	10	0	0
T126	9376	0	0	0
T131	7887	0	0	0
T132	4909	0	0	0
T133	12641	0	0	0
T134	15278	0	0	0
T140	0	15	0	0
T141	0	5	0	0
T142	0	5	0	0
T143	0	10	0	0
T144	0	5	0	0
T145	0	15	0	0
T147	19542	0	0	0
T148	8919	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40694	0	0
T1	3309895	353	0	0
T2	0	526	0	0
T3	0	31	0	0
T4	83570	0	0	0
T5	92082	0	0	0
T6	71659	4	0	0
T7	19052	2	0	0
T11	466986	137	0	0
T12	430138	0	0	0
T18	7813	4	0	0
T19	6800	40	0	0
T20	16000	0	0	0
T25	15164	4	0	0
T26	27127	0	0	0
T30	134430	0	0	0
T39	6775	8	0	0
T40	0	20	0	0
T41	0	15	0	0
T67	0	9	0	0
T69	0	6	0	0
T71	0	4	0	0
T126	9376	0	0	0
T131	7887	0	0	0
T132	4909	0	0	0
T133	12641	0	0	0
T134	15278	0	0	0
T140	0	15	0	0
T141	0	5	0	0
T142	0	5	0	0
T143	0	10	0	0
T144	0	5	0	0
T145	0	15	0	0
T147	19542	0	0	0
T148	8919	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	332829027	151	0	0
CgEnOn_A	332829027	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332829027	151	0	0
T12	65299	0	0	0
T30	13862	0	0	0
T39	1029	1	0	0
T40	0	4	0	0
T41	0	3	0	0
T67	0	2	0	0
T126	2110	0	0	0
T131	1186	0	0	0
T132	720	0	0	0
T133	1900	0	0	0
T134	2283	0	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	3	0	0
T147	4334	0	0	0
T148	1961	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332829027	151	0	0
T12	65299	0	0	0
T30	13862	0	0	0
T39	1029	1	0	0
T40	0	4	0	0
T41	0	3	0	0
T67	0	2	0	0
T126	2110	0	0	0
T131	1186	0	0	0
T132	720	0	0	0
T133	1900	0	0	0
T134	2283	0	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	3	0	0
T147	4334	0	0	0
T148	1961	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	166413837	151	0	0
CgEnOn_A	166413837	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166413837	151	0	0
T12	32650	0	0	0
T30	6932	0	0	0
T39	514	1	0	0
T40	0	4	0	0
T41	0	3	0	0
T67	0	2	0	0
T126	1054	0	0	0
T131	593	0	0	0
T132	359	0	0	0
T133	950	0	0	0
T134	1142	0	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	3	0	0
T147	2167	0	0	0
T148	981	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166413837	151	0	0
T12	32650	0	0	0
T30	6932	0	0	0
T39	514	1	0	0
T40	0	4	0	0
T41	0	3	0	0
T67	0	2	0	0
T126	1054	0	0	0
T131	593	0	0	0
T132	359	0	0	0
T133	950	0	0	0
T134	1142	0	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	3	0	0
T147	2167	0	0	0
T148	981	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	667037787	151	0	0
CgEnOn_A	667037787	145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667037787	151	0	0
T12	130719	0	0	0
T30	48867	0	0	0
T39	2082	1	0	0
T40	0	4	0	0
T41	0	3	0	0
T67	0	2	0	0
T126	4104	0	0	0
T131	2411	0	0	0
T132	1524	0	0	0
T133	3865	0	0	0
T134	4687	0	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	3	0	0
T147	8707	0	0	0
T148	4015	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667037787	145	0	0
T12	130719	0	0	0
T30	48867	0	0	0
T39	2082	1	0	0
T40	0	4	0	0
T41	0	3	0	0
T67	0	1	0	0
T126	4104	0	0	0
T131	2411	0	0	0
T132	1524	0	0	0
T133	3865	0	0	0
T134	4687	0	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	3	0	0
T147	8707	0	0	0
T148	4015	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	707120195	151	0	0
CgEnOn_A	707120195	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120195	151	0	0
T11	466986	1	0	0
T12	136170	0	0	0
T30	50905	0	0	0
T39	2122	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T65	0	1	0	0
T125	2897	0	0	0
T130	2024	0	0	0
T131	2511	0	0	0
T132	1588	0	0	0
T133	4026	0	0	0
T134	4882	0	0	0
T140	0	5	0	0
T141	0	5	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120195	149	0	0
T11	466986	1	0	0
T12	136170	0	0	0
T30	50905	0	0	0
T39	2122	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T125	2897	0	0	0
T130	2024	0	0	0
T131	2511	0	0	0
T132	1588	0	0	0
T133	4026	0	0	0
T134	4882	0	0	0
T140	0	5	0	0
T141	0	5	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	166413837	151	0	0
CgEnOn_A	166413837	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166413837	151	0	0
T12	32650	0	0	0
T30	6932	0	0	0
T39	514	1	0	0
T40	0	4	0	0
T41	0	3	0	0
T67	0	2	0	0
T126	1054	0	0	0
T131	593	0	0	0
T132	359	0	0	0
T133	950	0	0	0
T134	1142	0	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	3	0	0
T147	2167	0	0	0
T148	981	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166413837	151	0	0
T12	32650	0	0	0
T30	6932	0	0	0
T39	514	1	0	0
T40	0	4	0	0
T41	0	3	0	0
T67	0	2	0	0
T126	1054	0	0	0
T131	593	0	0	0
T132	359	0	0	0
T133	950	0	0	0
T134	1142	0	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	3	0	0
T147	2167	0	0	0
T148	981	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	707120195	151	0	0
CgEnOn_A	707120195	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120195	151	0	0
T11	466986	1	0	0
T12	136170	0	0	0
T30	50905	0	0	0
T39	2122	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T65	0	1	0	0
T125	2897	0	0	0
T130	2024	0	0	0
T131	2511	0	0	0
T132	1588	0	0	0
T133	4026	0	0	0
T134	4882	0	0	0
T140	0	5	0	0
T141	0	5	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120195	149	0	0
T11	466986	1	0	0
T12	136170	0	0	0
T30	50905	0	0	0
T39	2122	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T125	2897	0	0	0
T130	2024	0	0	0
T131	2511	0	0	0
T132	1588	0	0	0
T133	4026	0	0	0
T134	4882	0	0	0
T140	0	5	0	0
T141	0	5	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	166413837	151	0	0
CgEnOn_A	166413837	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166413837	151	0	0
T12	32650	0	0	0
T30	6932	0	0	0
T39	514	1	0	0
T40	0	4	0	0
T41	0	3	0	0
T67	0	2	0	0
T126	1054	0	0	0
T131	593	0	0	0
T132	359	0	0	0
T133	950	0	0	0
T134	1142	0	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	3	0	0
T147	2167	0	0	0
T148	981	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166413837	151	0	0
T12	32650	0	0	0
T30	6932	0	0	0
T39	514	1	0	0
T40	0	4	0	0
T41	0	3	0	0
T67	0	2	0	0
T126	1054	0	0	0
T131	593	0	0	0
T132	359	0	0	0
T133	950	0	0	0
T134	1142	0	0	0
T140	0	3	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	3	0	0
T147	2167	0	0	0
T148	981	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	332829027	7934	0	0
CgEnOn_A	332829027	5682	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332829027	7934	0	0
T1	426342	102	0	0
T4	10868	1	0	0
T5	8317	5	0	0
T6	9320	2	0	0
T7	2464	1	0	0
T18	987	2	0	0
T19	839	14	0	0
T20	2203	1	0	0
T25	1924	2	0	0
T26	3893	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332829027	5682	0	0
T1	426342	97	0	0
T2	0	141	0	0
T3	0	8	0	0
T4	10868	0	0	0
T5	8317	0	0	0
T6	9320	1	0	0
T7	2464	0	0	0
T11	0	36	0	0
T18	987	1	0	0
T19	839	13	0	0
T20	2203	0	0	0
T25	1924	1	0	0
T26	3893	0	0	0
T39	0	1	0	0
T71	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	166413837	7899	0	0
CgEnOn_A	166413837	5647	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166413837	7899	0	0
T1	213170	101	0	0
T4	5434	1	0	0
T5	4159	5	0	0
T6	4660	2	0	0
T7	1232	1	0	0
T18	494	2	0	0
T19	419	14	0	0
T20	1101	1	0	0
T25	962	2	0	0
T26	1946	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166413837	5647	0	0
T1	213170	96	0	0
T2	0	137	0	0
T3	0	9	0	0
T4	5434	0	0	0
T5	4159	0	0	0
T6	4660	1	0	0
T7	1232	0	0	0
T11	0	34	0	0
T18	494	1	0	0
T19	419	13	0	0
T20	1101	0	0	0
T25	962	1	0	0
T26	1946	0	0	0
T39	0	1	0	0
T71	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	667037787	7952	0	0
CgEnOn_A	667037787	5694	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667037787	7952	0	0
T1	852041	100	0	0
T4	21816	1	0	0
T5	25818	5	0	0
T6	18707	2	0	0
T7	4980	1	0	0
T18	2054	2	0	0
T19	1798	15	0	0
T20	4118	1	0	0
T25	3982	2	0	0
T26	6904	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667037787	5694	0	0
T1	852041	95	0	0
T2	0	140	0	0
T3	0	10	0	0
T4	21816	0	0	0
T5	25818	0	0	0
T6	18707	1	0	0
T7	4980	0	0	0
T11	0	33	0	0
T18	2054	1	0	0
T19	1798	14	0	0
T20	4118	0	0	0
T25	3982	1	0	0
T26	6904	0	0	0
T39	0	1	0	0
T71	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	339727317	7935	0	0
CgEnOn_A	339727317	5674	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339727317	7935	0	0
T1	436121	100	0	0
T4	10908	1	0	0
T5	12909	5	0	0
T6	9353	2	0	0
T7	2490	1	0	0
T18	1026	2	0	0
T19	899	15	0	0
T20	2059	1	0	0
T25	1991	2	0	0
T26	3452	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339727317	5674	0	0
T1	436121	95	0	0
T2	0	136	0	0
T3	0	8	0	0
T4	10908	0	0	0
T5	12909	0	0	0
T6	9353	1	0	0
T7	2490	0	0	0
T11	0	34	0	0
T18	1026	1	0	0
T19	899	14	0	0
T20	2059	0	0	0
T25	1991	1	0	0
T26	3452	0	0	0
T39	0	2	0	0
T71	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T6,T7,T25
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	707120195	4211	0	0
CgEnOn_A	707120195	4209	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120195	4211	0	0
T1	909171	65	0	0
T2	0	108	0	0
T3	0	4	0	0
T4	22726	0	0	0
T5	26894	0	0	0
T6	19486	1	0	0
T7	5188	2	0	0
T11	0	34	0	0
T18	2139	1	0	0
T19	1872	0	0	0
T20	4289	0	0	0
T25	4148	1	0	0
T26	7192	0	0	0
T69	0	6	0	0
T71	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120195	4209	0	0
T1	909171	65	0	0
T2	0	108	0	0
T3	0	4	0	0
T4	22726	0	0	0
T5	26894	0	0	0
T6	19486	1	0	0
T7	5188	2	0	0
T11	0	34	0	0
T18	2139	1	0	0
T19	1872	0	0	0
T20	4289	0	0	0
T25	4148	1	0	0
T26	7192	0	0	0
T69	0	6	0	0
T71	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T6,T7,T25
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	707120195	4184	0	0
CgEnOn_A	707120195	4182	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120195	4184	0	0
T1	909171	67	0	0
T2	0	123	0	0
T3	0	4	0	0
T4	22726	0	0	0
T5	26894	0	0	0
T6	19486	1	0	0
T7	5188	5	0	0
T11	0	38	0	0
T18	2139	1	0	0
T19	1872	0	0	0
T20	4289	0	0	0
T25	4148	1	0	0
T26	7192	0	0	0
T69	0	7	0	0
T71	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120195	4182	0	0
T1	909171	67	0	0
T2	0	123	0	0
T3	0	4	0	0
T4	22726	0	0	0
T5	26894	0	0	0
T6	19486	1	0	0
T7	5188	5	0	0
T11	0	38	0	0
T18	2139	1	0	0
T19	1872	0	0	0
T20	4289	0	0	0
T25	4148	1	0	0
T26	7192	0	0	0
T69	0	7	0	0
T71	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T6,T7,T25
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	707120195	4319	0	0
CgEnOn_A	707120195	4317	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120195	4319	0	0
T1	909171	69	0	0
T2	0	108	0	0
T3	0	4	0	0
T4	22726	0	0	0
T5	26894	0	0	0
T6	19486	1	0	0
T7	5188	3	0	0
T11	0	39	0	0
T18	2139	1	0	0
T19	1872	0	0	0
T20	4289	0	0	0
T25	4148	1	0	0
T26	7192	0	0	0
T69	0	6	0	0
T71	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120195	4317	0	0
T1	909171	69	0	0
T2	0	108	0	0
T3	0	4	0	0
T4	22726	0	0	0
T5	26894	0	0	0
T6	19486	1	0	0
T7	5188	3	0	0
T11	0	39	0	0
T18	2139	1	0	0
T19	1872	0	0	0
T20	4289	0	0	0
T25	4148	1	0	0
T26	7192	0	0	0
T69	0	6	0	0
T71	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T6,T7,T25
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	707120195	4244	0	0
CgEnOn_A	707120195	4242	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120195	4244	0	0
T1	909171	67	0	0
T2	0	114	0	0
T3	0	4	0	0
T4	22726	0	0	0
T5	26894	0	0	0
T6	19486	1	0	0
T7	5188	1	0	0
T11	0	37	0	0
T18	2139	1	0	0
T19	1872	0	0	0
T20	4289	0	0	0
T25	4148	1	0	0
T26	7192	0	0	0
T69	0	13	0	0
T71	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707120195	4242	0	0
T1	909171	67	0	0
T2	0	114	0	0
T3	0	4	0	0
T4	22726	0	0	0
T5	26894	0	0	0
T6	19486	1	0	0
T7	5188	1	0	0
T11	0	37	0	0
T18	2139	1	0	0
T19	1872	0	0	0
T20	4289	0	0	0
T25	4148	1	0	0
T26	7192	0	0	0
T69	0	13	0	0
T71	0	1	0	0