Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T25,T1
0	1	Covered	T1,T19,T2
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T25,T1
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T4,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1506009628	14546	0	0
GateOpen_A	1506009628	14546	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506009628	14546	0	0
T1	1927674	264	0	0
T2	0	398	0	0
T3	0	30	0	0
T4	49030	0	0	0
T5	51204	0	0	0
T6	42043	4	0	0
T7	11168	0	0	0
T11	0	108	0	0
T18	4564	4	0	0
T19	3957	35	0	0
T20	9484	0	0	0
T25	8859	4	0	0
T26	16196	0	0	0
T39	0	5	0	0
T71	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1506009628	14546	0	0
T1	1927674	264	0	0
T2	0	398	0	0
T3	0	30	0	0
T4	49030	0	0	0
T5	51204	0	0	0
T6	42043	4	0	0
T7	11168	0	0	0
T11	0	108	0	0
T18	4564	4	0	0
T19	3957	35	0	0
T20	9484	0	0	0
T25	8859	4	0	0
T26	16196	0	0	0
T39	0	5	0	0
T71	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T25,T1
0	1	Covered	T1,T19,T2
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T25,T1
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	166414225	3602	0	0
GateOpen_A	166414225	3602	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166414225	3602	0	0
T1	213170	64	0	0
T2	0	97	0	0
T3	0	8	0	0
T4	5435	0	0	0
T5	4159	0	0	0
T6	4661	1	0	0
T7	1233	0	0	0
T11	0	25	0	0
T18	494	1	0	0
T19	420	9	0	0
T20	1101	0	0	0
T25	962	1	0	0
T26	1946	0	0	0
T39	0	1	0	0
T71	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166414225	3602	0	0
T1	213170	64	0	0
T2	0	97	0	0
T3	0	8	0	0
T4	5435	0	0	0
T5	4159	0	0	0
T6	4661	1	0	0
T7	1233	0	0	0
T11	0	25	0	0
T18	494	1	0	0
T19	420	9	0	0
T20	1101	0	0	0
T25	962	1	0	0
T26	1946	0	0	0
T39	0	1	0	0
T71	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T25,T1
0	1	Covered	T1,T19,T2
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T25,T1
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	332829454	3640	0	0
GateOpen_A	332829454	3640	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332829454	3640	0	0
T1	426342	68	0	0
T2	0	101	0	0
T3	0	8	0	0
T4	10869	0	0	0
T5	8318	0	0	0
T6	9321	1	0	0
T7	2465	0	0	0
T11	0	27	0	0
T18	988	1	0	0
T19	839	8	0	0
T20	2204	0	0	0
T25	1924	1	0	0
T26	3894	0	0	0
T39	0	1	0	0
T71	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332829454	3640	0	0
T1	426342	68	0	0
T2	0	101	0	0
T3	0	8	0	0
T4	10869	0	0	0
T5	8318	0	0	0
T6	9321	1	0	0
T7	2465	0	0	0
T11	0	27	0	0
T18	988	1	0	0
T19	839	8	0	0
T20	2204	0	0	0
T25	1924	1	0	0
T26	3894	0	0	0
T39	0	1	0	0
T71	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T25,T1
0	1	Covered	T1,T19,T2
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T25,T1
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	667038212	3676	0	0
GateOpen_A	667038212	3676	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667038212	3676	0	0
T1	852041	66	0	0
T2	0	103	0	0
T3	0	8	0	0
T4	21817	0	0	0
T5	25818	0	0	0
T6	18707	1	0	0
T7	4980	0	0	0
T11	0	27	0	0
T18	2055	1	0	0
T19	1799	9	0	0
T20	4119	0	0	0
T25	3982	1	0	0
T26	6904	0	0	0
T39	0	1	0	0
T71	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667038212	3676	0	0
T1	852041	66	0	0
T2	0	103	0	0
T3	0	8	0	0
T4	21817	0	0	0
T5	25818	0	0	0
T6	18707	1	0	0
T7	4980	0	0	0
T11	0	27	0	0
T18	2055	1	0	0
T19	1799	9	0	0
T20	4119	0	0	0
T25	3982	1	0	0
T26	6904	0	0	0
T39	0	1	0	0
T71	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T25,T1
0	1	Covered	T1,T19,T2
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T25,T1
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	339727737	3628	0	0
GateOpen_A	339727737	3628	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339727737	3628	0	0
T1	436121	66	0	0
T2	0	97	0	0
T3	0	6	0	0
T4	10909	0	0	0
T5	12909	0	0	0
T6	9354	1	0	0
T7	2490	0	0	0
T11	0	29	0	0
T18	1027	1	0	0
T19	899	9	0	0
T20	2060	0	0	0
T25	1991	1	0	0
T26	3452	0	0	0
T39	0	2	0	0
T71	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339727737	3628	0	0
T1	436121	66	0	0
T2	0	97	0	0
T3	0	6	0	0
T4	10909	0	0	0
T5	12909	0	0	0
T6	9354	1	0	0
T7	2490	0	0	0
T11	0	29	0	0
T18	1027	1	0	0
T19	899	9	0	0
T20	2060	0	0	0
T25	1991	1	0	0
T26	3452	0	0	0
T39	0	2	0	0
T71	0	1	0	0