Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

276179546

1

T5

2232

T6

2492

T1

79914

auto[1]

361376

1

T5

112

T6

160

T22

564

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

276170444

1

T5

2204

T6

2416

T1

79914

auto[1]

370478

1

T5

140

T6

236

T19

448

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

276078304

1

T5

2334

T6

2416

T1

79914

auto[1]

462618

1

T5

10

T6

236

T19

578

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

259837264

1

T5

2344

T6

382

T1

79914

auto[1]

16703658

1

T6

2270

T19

3346

T20

268

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158309804

1

T5

2134

T6

2328

T1

79886

auto[1]

118231118

1

T5

210

T6

324

T1

28

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

145942792

1

T5

2072

T6

58

T1

79886

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

113554996

1

T5

130

T6

216

T1

28

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

26556

1

T22

156

T104

6

T113

22

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6092

1

T5

2

T6

72

T9

50

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

11812570

1

T6

2070

T19

2914

T20

178

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

4577546

1

T104

84

T113

158

T3

228

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43314

1

T40

76

T104

78

T113

28

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11206

1

T113

16

T3

68

T9

174

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

53854

1

T5

18

T22

30

T9

34

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

920

1

T5

2

T9

38

T10

34

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

11194

1

T5

44

T9

280

T144

84

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2934

1

T5

66

T9

40

T10

84

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

8820

1

T19

84

T20

32

T104

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2862

1

T113

4

T3

8

T9

22

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

17872

1

T104

50

T113

70

T73

56

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4776

1

T113

84

T3

40

T9

46

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

65620

1

T19

90

T22

54

T40

14

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3636

1

T20

30

T22

38

T9

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

29916

1

T22

112

T40

56

T104

62

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6702

1

T9

150

T78

80

T10

62

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

23050

1

T19

124

T104

36

T113

20

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5594

1

T113

22

T3

2

T9

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

49320

1

T104

96

T113

78

T3

154

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

11534

1

T113

70

T3

56

T9

216

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

76118

1

T19

108

T22

152

T104

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5040

1

T5

10

T6

36

T19

32

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

40832

1

T22

296

T104

62

T9

724

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10062

1

T9

36

T172

36

T173

80

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

37328

1

T6

112

T19

224

T20

58

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8800

1

T104

10

T9

112

T76

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

70648

1

T6

88

T40

44

T104

142

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

18418

1

T104

64

T9

392

T76

82