Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	581533	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3380983

1

T7

4

T8

22

T5

173

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	976111	1			T7	5		T8	42		T5	15
values[0x0]	1370803	1			T7	8		T8	17		T5	151
values[0x1]	1615602	1			T7	3		T8	22		T5	165

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	318891	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3643625

1

T7

6

T8

31

T5

222

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15176	1			T4	564		T1	164		T109	1
valid_sources[0x01]	14697	1			T1	142		T2	2		T3	4
valid_sources[0x02]	14898	1			T6	2		T1	147		T2	14
valid_sources[0x03]	14087	1			T28	7		T1	150		T21	1
valid_sources[0x04]	15232	1			T1	163		T2	3		T77	1
valid_sources[0x05]	16571	1			T1	145		T25	2		T2	1
valid_sources[0x06]	16535	1			T6	4		T1	146		T2	6
valid_sources[0x07]	16250	1			T1	151		T2	4		T3	212
valid_sources[0x08]	14590	1			T1	162		T25	1		T11	285
valid_sources[0x09]	16676	1			T1	161		T2	8		T77	1
valid_sources[0x0a]	16899	1			T1	158		T2	9		T77	3
valid_sources[0x0b]	16162	1			T1	151		T2	2		T111	4
valid_sources[0x0c]	15194	1			T1	149		T2	1		T35	1
valid_sources[0x0d]	14955	1			T29	1		T1	166		T2	3
valid_sources[0x0e]	15321	1			T1	117		T21	1		T2	5
valid_sources[0x0f]	14350	1			T1	146		T21	1		T25	1
valid_sources[0x10]	14743	1			T1	160		T2	6		T111	2
valid_sources[0x11]	17065	1			T29	1		T1	115		T2	1
valid_sources[0x12]	15078	1			T1	148		T2	1		T109	1
valid_sources[0x13]	15323	1			T27	1		T1	145		T21	1
valid_sources[0x14]	15085	1			T1	177		T22	6		T25	2
valid_sources[0x15]	15425	1			T27	1		T33	1		T1	143
valid_sources[0x16]	16347	1			T1	151		T23	2		T2	3
valid_sources[0x17]	13895	1			T29	4		T1	166		T2	7
valid_sources[0x18]	15600	1			T1	129		T2	6		T109	1
valid_sources[0x19]	16208	1			T1	159		T21	1		T23	2
valid_sources[0x1a]	15338	1			T33	5		T1	147		T19	2
valid_sources[0x1b]	16878	1			T26	14		T29	15		T6	9
valid_sources[0x1c]	15948	1			T1	126		T2	2		T111	9
valid_sources[0x1d]	14276	1			T26	9		T29	1		T1	145
valid_sources[0x1e]	16567	1			T6	5		T1	139		T21	1
valid_sources[0x1f]	14333	1			T1	134		T2	2		T3	15
valid_sources[0x20]	16151	1			T27	5		T1	140		T2	5
valid_sources[0x21]	16006	1			T30	36		T1	149		T2	4
valid_sources[0x22]	15516	1			T26	4		T1	128		T2	9
valid_sources[0x23]	14603	1			T1	161		T21	1		T2	2
valid_sources[0x24]	16771	1			T1	173		T21	2		T2	1
valid_sources[0x25]	15969	1			T1	149		T11	349		T179	1
valid_sources[0x26]	15279	1			T1	164		T2	1		T11	299
valid_sources[0x27]	15222	1			T1	148		T2	4		T111	2
valid_sources[0x28]	15169	1			T1	127		T21	1		T2	4
valid_sources[0x29]	14737	1			T29	6		T1	148		T2	4
valid_sources[0x2a]	16112	1			T27	1		T6	13		T1	166
valid_sources[0x2b]	15625	1			T1	150		T21	1		T2	2
valid_sources[0x2c]	14414	1			T1	148		T2	3		T46	1
valid_sources[0x2d]	13883	1			T6	4		T1	145		T2	4
valid_sources[0x2e]	14865	1			T1	145		T21	1		T2	3
valid_sources[0x2f]	16276	1			T1	145		T21	1		T2	1
valid_sources[0x30]	14004	1			T6	6		T1	143		T21	1
valid_sources[0x31]	17029	1			T1	136		T2	4		T109	1
valid_sources[0x32]	15359	1			T1	130		T23	1		T2	4
valid_sources[0x33]	14959	1			T33	4		T1	118		T23	1
valid_sources[0x34]	15689	1			T33	3		T1	141		T2	7
valid_sources[0x35]	15574	1			T27	1		T6	4		T1	150
valid_sources[0x36]	14548	1			T1	170		T23	1		T2	3
valid_sources[0x37]	16113	1			T1	145		T2	1		T3	164
valid_sources[0x38]	14830	1			T1	145		T21	1		T2	8
valid_sources[0x39]	15136	1			T1	158		T2	3		T46	1
valid_sources[0x3a]	14585	1			T1	152		T21	1		T3	139
valid_sources[0x3b]	16067	1			T1	163		T22	3		T23	3
valid_sources[0x3c]	15906	1			T6	2		T1	143		T2	1
valid_sources[0x3d]	14590	1			T6	1		T33	2		T1	132
valid_sources[0x3e]	15525	1			T6	2		T1	160		T18	2
valid_sources[0x3f]	16420	1			T1	129		T2	9		T46	2
valid_sources[0x40]	15701	1			T29	4		T1	146		T18	1
valid_sources[0x41]	14449	1			T28	5		T29	6		T33	2
valid_sources[0x42]	15010	1			T33	5		T1	159		T2	3
valid_sources[0x43]	14461	1			T6	2		T1	150		T2	2
valid_sources[0x44]	15061	1			T27	2		T28	2		T33	1
valid_sources[0x45]	18961	1			T27	1		T1	155		T2	7
valid_sources[0x46]	16581	1			T6	2		T1	148		T21	1
valid_sources[0x47]	16601	1			T1	163		T2	4		T109	1
valid_sources[0x48]	16193	1			T29	7		T1	141		T19	1
valid_sources[0x49]	15627	1			T6	2		T1	140		T23	2
valid_sources[0x4a]	14566	1			T1	149		T2	5		T11	258
valid_sources[0x4b]	14890	1			T1	148		T2	4		T46	1
valid_sources[0x4c]	15633	1			T1	152		T2	7		T38	1
valid_sources[0x4d]	15852	1			T1	135		T20	6		T23	9
valid_sources[0x4e]	15176	1			T29	2		T6	2		T1	136
valid_sources[0x4f]	15185	1			T1	177		T2	11		T109	4
valid_sources[0x50]	16306	1			T27	3		T29	2		T1	153
valid_sources[0x51]	14655	1			T1	146		T25	1		T2	9
valid_sources[0x52]	16116	1			T26	7		T6	2		T1	136
valid_sources[0x53]	15900	1			T6	3		T1	139		T23	2
valid_sources[0x54]	15096	1			T27	2		T1	141		T3	284
valid_sources[0x55]	14843	1			T1	153		T2	1		T77	1
valid_sources[0x56]	14546	1			T1	147		T2	3		T46	2
valid_sources[0x57]	15039	1			T29	2		T1	151		T21	1
valid_sources[0x58]	14255	1			T1	156		T2	8		T3	27
valid_sources[0x59]	15907	1			T33	1		T1	169		T25	1
valid_sources[0x5a]	13126	1			T27	1		T1	149		T2	5
valid_sources[0x5b]	14311	1			T1	136		T111	1		T11	287
valid_sources[0x5c]	15221	1			T27	3		T1	142		T2	5
valid_sources[0x5d]	16504	1			T29	2		T6	1		T1	169
valid_sources[0x5e]	13975	1			T6	2		T1	156		T19	1
valid_sources[0x5f]	14340	1			T1	135		T23	3		T2	14
valid_sources[0x60]	14774	1			T1	123		T21	1		T23	1
valid_sources[0x61]	15996	1			T29	2		T6	3		T1	130
valid_sources[0x62]	14653	1			T1	160		T21	1		T23	1
valid_sources[0x63]	15354	1			T6	7		T1	159		T23	1
valid_sources[0x64]	13704	1			T27	4		T1	118		T21	1
valid_sources[0x65]	17316	1			T27	3		T1	146		T2	9
valid_sources[0x66]	16758	1			T27	2		T33	2		T1	172
valid_sources[0x67]	14811	1			T27	3		T29	7		T6	1
valid_sources[0x68]	16497	1			T1	131		T25	1		T2	6
valid_sources[0x69]	16625	1			T8	81		T1	134		T2	4
valid_sources[0x6a]	15958	1			T29	2		T1	170		T2	1
valid_sources[0x6b]	15018	1			T1	147		T2	1		T35	2
valid_sources[0x6c]	15976	1			T28	1		T1	161		T2	13
valid_sources[0x6d]	17075	1			T1	138		T2	3		T109	1
valid_sources[0x6e]	15500	1			T1	128		T2	5		T11	311
valid_sources[0x6f]	14757	1			T1	154		T2	6		T11	285
valid_sources[0x70]	14853	1			T29	1		T6	4		T1	156
valid_sources[0x71]	15671	1			T1	143		T25	1		T2	8
valid_sources[0x72]	15205	1			T1	136		T21	1		T25	1
valid_sources[0x73]	14990	1			T1	166		T2	3		T109	1
valid_sources[0x74]	14904	1			T27	3		T1	141		T2	4
valid_sources[0x75]	16019	1			T1	159		T2	1		T3	66
valid_sources[0x76]	15368	1			T28	1		T1	150		T22	2
valid_sources[0x77]	15607	1			T1	140		T25	2		T2	4
valid_sources[0x78]	15143	1			T1	148		T21	3		T23	1
valid_sources[0x79]	15402	1			T6	3		T1	151		T23	1
valid_sources[0x7a]	16852	1			T1	164		T23	3		T2	3
valid_sources[0x7b]	14880	1			T1	143		T3	18		T35	2
valid_sources[0x7c]	14800	1			T1	142		T2	3		T3	1
valid_sources[0x7d]	14861	1			T28	12		T6	4		T1	156
valid_sources[0x7e]	14762	1			T1	178		T2	6		T11	310
valid_sources[0x7f]	14749	1			T33	2		T1	143		T25	1
valid_sources[0x80]	16476	1			T1	142		T21	1		T2	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

853880

1

T7

2

T8

13

T5

9

values[0x0]

all_enables

biggest_size

1284188

1

T7

1

T8

6

T5

97

values[0x1]

all_enables

biggest_size

1242915

1

T7

1

T8

3

T5

67