Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	763239090	85975	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763239090	85975	0	0
T1	506975	691	0	0
T2	429945	84	0	0
T3	0	498	0	0
T11	0	1798	0	0
T12	0	87	0	0
T13	0	55	0	0
T14	0	142	0	0
T15	0	579	0	0
T16	0	421	0	0
T17	0	226	0	0
T18	9080	0	0	0
T19	8095	0	0	0
T20	4015	0	0	0
T21	15230	0	0	0
T22	6465	0	0	0
T23	176520	0	0	0
T24	3530	0	0	0
T25	8540	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152647818	12146	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152647818	12146	0	0
T1	101395	112	0	0
T2	85989	14	0	0
T3	0	92	0	0
T11	0	240	0	0
T12	0	14	0	0
T13	0	9	0	0
T14	0	22	0	0
T15	0	78	0	0
T16	0	67	0	0
T17	0	35	0	0
T18	1816	0	0	0
T19	1619	0	0	0
T20	803	0	0	0
T21	3046	0	0	0
T22	1293	0	0	0
T23	35304	0	0	0
T24	706	0	0	0
T25	1708	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152647818	17270	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152647818	17270	0	0
T1	101395	141	0	0
T2	85989	17	0	0
T3	0	96	0	0
T11	0	362	0	0
T12	0	17	0	0
T13	0	11	0	0
T14	0	28	0	0
T15	0	116	0	0
T16	0	85	0	0
T17	0	46	0	0
T18	1816	0	0	0
T19	1619	0	0	0
T20	803	0	0	0
T21	3046	0	0	0
T22	1293	0	0	0
T23	35304	0	0	0
T24	706	0	0	0
T25	1708	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152647818	27241	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152647818	27241	0	0
T1	101395	190	0	0
T2	85989	22	0	0
T3	0	122	0	0
T11	0	601	0	0
T12	0	26	0	0
T13	0	15	0	0
T14	0	40	0	0
T15	0	196	0	0
T16	0	119	0	0
T17	0	67	0	0
T18	1816	0	0	0
T19	1619	0	0	0
T20	803	0	0	0
T21	3046	0	0	0
T22	1293	0	0	0
T23	35304	0	0	0
T24	706	0	0	0
T25	1708	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152647818	11902	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152647818	11902	0	0
T1	101395	109	0	0
T2	85989	14	0	0
T3	0	92	0	0
T11	0	229	0	0
T12	0	13	0	0
T13	0	9	0	0
T14	0	23	0	0
T15	0	74	0	0
T16	0	65	0	0
T17	0	33	0	0
T18	1816	0	0	0
T19	1619	0	0	0
T20	803	0	0	0
T21	3046	0	0	0
T22	1293	0	0	0
T23	35304	0	0	0
T24	706	0	0	0
T25	1708	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152647818	17416	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152647818	17416	0	0
T1	101395	139	0	0
T2	85989	17	0	0
T3	0	96	0	0
T11	0	366	0	0
T12	0	17	0	0
T13	0	11	0	0
T14	0	29	0	0
T15	0	115	0	0
T16	0	85	0	0
T17	0	45	0	0
T18	1816	0	0	0
T19	1619	0	0	0
T20	803	0	0	0
T21	3046	0	0	0
T22	1293	0	0	0
T23	35304	0	0	0
T24	706	0	0	0
T25	1708	0	0	0