Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T4,T1,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	152647818	149668683	0	0
AllClkBypReqTrue_A	152647818	117236	0	0
IoClkBypReqFalse_A	152647818	149596562	0	2415
IoClkBypReqTrue_A	152647818	184875	0	0
LcClkBypAckFalse_A	152647818	149677599	0	0
LcClkBypAckTrue_A	152647818	108320	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152647818	149668683	0	0
T4	23770	4882	0	0
T5	89586	89481	0	0
T6	105410	105343	0	0
T7	827	800	0	0
T8	2143	2045	0	0
T26	2315	2096	0	0
T27	2147	2044	0	0
T28	2215	1757	0	0
T29	2674	2607	0	0
T30	1340	1315	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152647818	117236	0	0
T1	0	742	0	0
T2	0	719	0	0
T4	23770	0	0	0
T5	89586	0	0	0
T6	105410	0	0	0
T7	827	13	0	0
T8	2143	0	0	0
T19	0	289	0	0
T20	0	24	0	0
T21	0	434	0	0
T26	2315	136	0	0
T27	2147	41	0	0
T28	2215	442	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	0	177	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152647818	149596562	0	2415
T4	23770	4856	0	3
T5	89586	89479	0	3
T6	105410	105341	0	3
T7	827	811	0	3
T8	2143	2043	0	3
T26	2315	1910	0	3
T27	2147	1703	0	3
T28	2215	1699	0	3
T29	2674	2605	0	3
T30	1340	1313	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152647818	184875	0	0
T1	101395	1159	0	0
T4	23770	0	0	0
T6	105410	0	0	0
T18	1816	0	0	0
T19	0	351	0	0
T20	0	25	0	0
T21	0	636	0	0
T22	0	219	0	0
T25	0	278	0	0
T26	2315	320	0	0
T27	2147	380	0	0
T28	2215	498	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	284	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152647818	149677599	0	0
T4	23770	4882	0	0
T5	89586	89481	0	0
T6	105410	105343	0	0
T7	827	813	0	0
T8	2143	2045	0	0
T26	2315	2081	0	0
T27	2147	1901	0	0
T28	2215	1892	0	0
T29	2674	2607	0	0
T30	1340	1315	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152647818	108320	0	0
T1	101395	730	0	0
T4	23770	0	0	0
T6	105410	0	0	0
T18	1816	0	0	0
T19	0	204	0	0
T20	0	20	0	0
T21	0	305	0	0
T22	0	84	0	0
T25	0	13	0	0
T26	2315	151	0	0
T27	2147	184	0	0
T28	2215	307	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T33	1743	149	0	0