Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1233737292	13811	0	0
TransStop_A	1233737292	7113	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233737292	13811	0	0
T1	0	135	0	0
T2	0	15	0	0
T4	396188	0	0	0
T5	659304	0	0	0
T6	391228	0	0	0
T8	8576	4	0	0
T18	0	8	0	0
T26	9448	0	0	0
T27	23864	0	0	0
T28	88652	0	0	0
T29	41152	31	0	0
T30	21448	16	0	0
T33	27900	0	0	0
T75	0	23	0	0
T76	0	18	0	0
T109	0	22	0	0
T110	0	25	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233737292	7113	0	0
T1	0	68	0	0
T2	0	10	0	0
T4	396188	0	0	0
T5	659304	0	0	0
T6	391228	0	0	0
T8	8576	4	0	0
T18	0	2	0	0
T26	9448	0	0	0
T27	23864	0	0	0
T28	88652	0	0	0
T29	41152	13	0	0
T30	21448	13	0	0
T33	27900	0	0	0
T75	0	18	0	0
T76	0	9	0	0
T109	0	12	0	0
T110	0	9	0	0
T111	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	308434323	3473	0	0
TransStop_A	308434323	1772	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308434323	3473	0	0
T1	0	31	0	0
T2	0	4	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2144	1	0	0
T18	0	2	0	0
T26	2362	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10288	7	0	0
T30	5362	2	0	0
T33	6975	0	0	0
T75	0	6	0	0
T76	0	6	0	0
T109	0	6	0	0
T110	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308434323	1772	0	0
T1	0	17	0	0
T2	0	3	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2144	1	0	0
T18	0	1	0	0
T26	2362	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10288	3	0	0
T30	5362	2	0	0
T33	6975	0	0	0
T75	0	5	0	0
T76	0	2	0	0
T109	0	4	0	0
T110	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	308434323	3430	0	0
TransStop_A	308434323	1761	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308434323	3430	0	0
T1	0	40	0	0
T2	0	2	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2144	1	0	0
T18	0	1	0	0
T26	2362	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10288	10	0	0
T30	5362	6	0	0
T33	6975	0	0	0
T75	0	5	0	0
T76	0	4	0	0
T109	0	2	0	0
T110	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308434323	1761	0	0
T1	0	18	0	0
T2	0	1	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2144	1	0	0
T26	2362	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10288	3	0	0
T30	5362	5	0	0
T33	6975	0	0	0
T75	0	3	0	0
T76	0	2	0	0
T109	0	1	0	0
T110	0	3	0	0
T111	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	308434323	3434	0	0
TransStop_A	308434323	1795	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308434323	3434	0	0
T1	0	29	0	0
T2	0	5	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2144	1	0	0
T18	0	2	0	0
T26	2362	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10288	5	0	0
T30	5362	4	0	0
T33	6975	0	0	0
T75	0	6	0	0
T76	0	4	0	0
T109	0	8	0	0
T110	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308434323	1795	0	0
T1	0	16	0	0
T2	0	4	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2144	1	0	0
T18	0	1	0	0
T26	2362	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10288	3	0	0
T30	5362	3	0	0
T33	6975	0	0	0
T75	0	4	0	0
T76	0	2	0	0
T109	0	3	0	0
T110	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	308434323	3474	0	0
TransStop_A	308434323	1785	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308434323	3474	0	0
T1	0	35	0	0
T2	0	4	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2144	1	0	0
T18	0	3	0	0
T26	2362	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10288	9	0	0
T30	5362	4	0	0
T33	6975	0	0	0
T75	0	6	0	0
T76	0	4	0	0
T109	0	6	0	0
T110	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308434323	1785	0	0
T1	0	17	0	0
T2	0	2	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2144	1	0	0
T26	2362	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10288	4	0	0
T30	5362	3	0	0
T33	6975	0	0	0
T75	0	6	0	0
T76	0	3	0	0
T109	0	4	0	0
T110	0	1	0	0
T111	0	2	0	0