Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	152647818	18344324	0	60

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152647818	18344324	0	60
T1	101395	295935	0	0
T2	85989	5587	0	0
T3	0	98959	0	0
T11	0	242090	0	0
T12	0	8551	0	0
T13	0	3731	0	1
T14	0	10308	0	1
T15	0	0	0	1
T17	0	0	0	1
T18	1816	0	0	0
T19	1619	0	0	0
T20	803	0	0	0
T21	3046	0	0	0
T22	1293	0	0	0
T23	35304	0	0	0
T24	706	0	0	0
T25	1708	0	0	0
T31	0	645	0	0
T32	0	1205	0	1
T36	0	723	0	1
T112	0	0	0	1
T113	0	0	0	1
T114	0	0	0	1
T115	0	0	0	1