Unified Coverage Report :: Module :: prim_subreg_arb

Module : prim_subreg_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_fatal_err_code_reg_intg.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_fatal_err_code_idle_cnt.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_fatal_err_code_shadow_storage_err.wr_en_data_arb	50.00	50.00
tb.dut.u_reg.u_recov_err_code_shadow_update_err.wr_en_data_arb	95.00	100.00	90.00
tb.dut.u_reg.u_extclk_ctrl_regwen.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_extclk_ctrl_sel.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_jitter_regwen.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_jitter_enable.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_enables_clk_io_peri_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_enables_clk_usb_peri_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_hints_clk_main_aes_hint.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_measure_ctrl_regwen.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_en.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb	100.00	100.00	100.00			100.00
tb.dut.u_reg.u_recov_err_code_io_measure_err.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_recov_err_code_io_div2_measure_err.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_recov_err_code_io_div4_measure_err.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_recov_err_code_main_measure_err.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_recov_err_code_usb_measure_err.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_recov_err_code_io_timeout_err.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_recov_err_code_io_div2_timeout_err.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_recov_err_code_io_div4_timeout_err.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_recov_err_code_main_timeout_err.wr_en_data_arb	100.00	100.00	100.00
tb.dut.u_reg.u_recov_err_code_usb_timeout_err.wr_en_data_arb	100.00	100.00	100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_extclk_ctrl_regwen.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_jitter_regwen.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_measure_ctrl_regwen.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=1 + DW=1,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=9,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_extclk_ctrl_sel.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_jitter_enable.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_clk_enables_clk_io_peri_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_clk_enables_clk_usb_peri_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_clk_hints_clk_main_aes_hint.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_en.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_fatal_err_code_reg_intg.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_fatal_err_code_idle_cnt.wr_en_data_arb

SCORE	LINE
50.00	50.00

tb.dut.u_reg.u_fatal_err_code_shadow_storage_err.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	1	1
44	1	1
51		unreachable
52		unreachable
53		unreachable

---

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :

SCORE	LINE
95.00	100.00

tb.dut.u_reg.u_recov_err_code_shadow_update_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_measure_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_div2_measure_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_div4_measure_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_recov_err_code_main_measure_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_recov_err_code_usb_measure_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_timeout_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_div2_timeout_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_div4_timeout_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_recov_err_code_main_timeout_err.wr_en_data_arb

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_recov_err_code_usb_timeout_err.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T5,T4,T6

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T5,T4,T6

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=9,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T5,T4,T6

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T5,T4,T6

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
95.00	90.00

tb.dut.u_reg.u_recov_err_code_shadow_update_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_measure_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_div2_measure_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_div4_measure_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_main_measure_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_usb_measure_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_timeout_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_div2_timeout_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_io_div4_timeout_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_main_timeout_err.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_recov_err_code_usb_timeout_err.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T6,T1
1	1	Covered	T1,T2,T3

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T1,T2,T3

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T5,T6,T1

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_enables_clk_io_div4_peri_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_enables_clk_io_div2_peri_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_enables_clk_io_peri_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_enables_clk_usb_peri_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_hints_clk_main_aes_hint.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_hints_clk_main_hmac_hint.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_hints_clk_main_kmac_hint.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_clk_hints_clk_main_otbn_hint.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T8,T29,T30

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T8,T29,T30

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T8,T29,T30

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_extclk_ctrl_sel.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_extclk_ctrl_hi_speed_sel.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_jitter_enable.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_meas_ctrl_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div2_meas_ctrl_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_main_meas_ctrl_en.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_usb_meas_ctrl_en.wr_en_data_arb

	Total	Covered	Percent
Conditions	7	7	100.00
Logical	7	7	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T5

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T7,T8,T5

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T7,T8,T5

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_extclk_ctrl_regwen.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_jitter_regwen.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_measure_ctrl_regwen.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T7,T8,T5
1	0	Covered	T7,T5,T26

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T35
1	0	Covered	T4,T1,T35
1	1	Covered	T7,T8,T5

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T7,T8,T5

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T7,T5,T26

---

Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.committed_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.staged_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.shadow_reg.wr_en_data_arb

SCORE	COND
100.00	100.00

tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.committed_reg.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T4,T6

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T5,T4,T6

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T7,T8,T5
1	Covered	T5,T4,T6

---

Branch Coverage for Module : prim_subreg_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T5
0	Covered	T7,T8,T5