Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	153576157	4999837	0	0
clk_enables_rd_A	153576157	34995	0	0
clk_hints_rd_A	153576157	30004	0	0
extclk_ctrl_rd_A	153576157	37053	0	0
extclk_ctrl_regwen_rd_A	153576157	29122	0	0
jitter_enable_rd_A	153576157	44666	0	0
jitter_regwen_rd_A	153576157	32748	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	4999837	0	0
T1	101395	47541	0	0
T2	85989	0	0	0
T3	0	32570	0	0
T11	0	102178	0	0
T16	0	62239	0	0
T18	1816	0	0	0
T19	1619	0	0	0
T20	803	0	0	0
T21	3046	0	0	0
T22	1293	0	0	0
T23	35304	0	0	0
T24	706	0	0	0
T25	1708	0	0	0
T69	0	113183	0	0
T70	0	115925	0	0
T71	0	177669	0	0
T72	0	118550	0	0
T73	0	44998	0	0
T74	0	132645	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	34995	0	0
T11	336252	3801	0	0
T12	115879	5	0	0
T31	0	12	0	0
T35	8218	0	0	0
T40	0	18	0	0
T41	0	5277	0	0
T43	1709	0	0	0
T44	952	0	0	0
T69	0	4037	0	0
T141	1734	9	0	0
T142	0	4	0	0
T143	0	4737	0	0
T144	0	1206	0	0
T145	786	0	0	0
T146	1248	0	0	0
T147	1653	0	0	0
T148	1256	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	30004	0	0
T11	336252	3164	0	0
T12	115879	11	0	0
T31	0	3	0	0
T35	8218	0	0	0
T40	0	14	0	0
T41	0	4289	0	0
T43	1709	0	0	0
T44	952	0	0	0
T69	0	3687	0	0
T141	1734	2	0	0
T142	0	8	0	0
T143	0	3628	0	0
T145	786	0	0	0
T146	1248	0	0	0
T147	1653	0	0	0
T148	1256	0	0	0
T149	0	3	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	37053	0	0
T1	101395	0	0	0
T2	0	129	0	0
T4	23770	0	0	0
T6	105410	0	0	0
T11	0	3994	0	0
T18	1816	0	0	0
T19	1619	40	0	0
T20	803	0	0	0
T21	0	42	0	0
T25	0	23	0	0
T28	2215	40	0	0
T29	2674	0	0	0
T30	1340	0	0	0
T31	0	80	0	0
T33	1743	0	0	0
T77	0	75	0	0
T149	0	78	0	0
T150	0	5	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	29122	0	0
T11	336252	3321	0	0
T12	115879	0	0	0
T13	48604	0	0	0
T36	27391	0	0	0
T41	0	4415	0	0
T44	952	0	0	0
T69	0	3697	0	0
T80	0	30	0	0
T143	0	3676	0	0
T144	0	1154	0	0
T145	786	0	0	0
T146	1248	0	0	0
T147	1653	0	0	0
T148	1256	0	0	0
T151	0	77	0	0
T152	0	29	0	0
T153	0	30	0	0
T154	0	22	0	0
T155	1111	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	44666	0	0
T11	336252	4511	0	0
T12	115879	314	0	0
T31	0	225	0	0
T35	8218	0	0	0
T40	0	405	0	0
T41	0	5859	0	0
T43	1709	0	0	0
T44	952	0	0	0
T69	0	6609	0	0
T141	1734	113	0	0
T142	0	78	0	0
T143	0	5275	0	0
T145	786	0	0	0
T146	1248	0	0	0
T147	1653	0	0	0
T148	1256	0	0	0
T149	0	235	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153576157	32748	0	0
T11	336252	3989	0	0
T12	115879	0	0	0
T13	48604	0	0	0
T36	27391	0	0	0
T41	0	4974	0	0
T44	952	0	0	0
T69	0	4370	0	0
T143	0	4549	0	0
T144	0	1371	0	0
T145	786	0	0	0
T146	1248	0	0	0
T147	1653	0	0	0
T148	1256	0	0	0
T155	1111	0	0	0
T156	0	2972	0	0
T157	0	1567	0	0
T158	0	1546	0	0
T159	0	2259	0	0
T160	0	2296	0	0