Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	44538	0	0
CgEnOn_A	2147483647	35584	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44538	0	0
T1	0	31	0	0
T3	1854596	5	0	0
T4	239483	39	0	0
T5	391265	3	0	0
T6	231858	3	0	0
T7	17461	3	0	0
T8	5715	7	0	0
T11	2673511	0	0	0
T12	961633	0	0	0
T26	6456	3	0	0
T27	16298	3	0	0
T28	62652	3	0	0
T29	27489	10	0	0
T30	14351	5	0	0
T33	6974	0	0	0
T35	28240	0	0	0
T43	3344	15	0	0
T44	7763	20	0	0
T45	0	20	0	0
T72	0	10	0	0
T141	14944	0	0	0
T145	6968	0	0	0
T146	2764	0	0	0
T147	16142	0	0	0
T161	0	10	0	0
T162	0	15	0	0
T163	0	10	0	0
T164	0	10	0	0
T165	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35584	0	0
T1	0	147	0	0
T3	1030346	205	0	0
T4	45354	0	0	0
T5	97011	0	0	0
T6	57440	0	0	0
T8	1515	4	0	0
T11	2673511	87	0	0
T12	961633	0	0	0
T18	0	2	0	0
T24	0	6	0	0
T26	1828	0	0	0
T27	4606	0	0	0
T28	19213	0	0	0
T29	7326	7	0	0
T30	3842	2	0	0
T33	5909	0	0	0
T35	28240	0	0	0
T43	3344	24	0	0
T44	7763	32	0	0
T45	0	20	0	0
T46	0	3	0	0
T72	0	9	0	0
T141	8281	3	0	0
T145	6968	43	0	0
T146	2764	0	0	0
T147	16142	0	0	0
T148	1256	0	0	0
T161	0	10	0	0
T162	0	15	0	0
T163	0	10	0	0
T164	0	10	0	0
T165	0	5	0	0
T166	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	143399245	162	0	0
CgEnOn_A	143399245	162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143399245	162	0	0
T3	412139	1	0	0
T11	148415	0	0	0
T12	213579	0	0	0
T35	4984	0	0	0
T43	723	3	0	0
T44	1711	4	0	0
T45	0	4	0	0
T72	0	2	0	0
T141	3313	0	0	0
T145	1528	0	0	0
T146	607	0	0	0
T147	3569	0	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143399245	162	0	0
T3	412139	1	0	0
T11	148415	0	0	0
T12	213579	0	0	0
T35	4984	0	0	0
T43	723	3	0	0
T44	1711	4	0	0
T45	0	4	0	0
T72	0	2	0	0
T141	3313	0	0	0
T145	1528	0	0	0
T146	607	0	0	0
T147	3569	0	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	71699037	162	0	0
CgEnOn_A	71699037	162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71699037	162	0	0
T3	206069	1	0	0
T11	742069	0	0	0
T12	106790	0	0	0
T35	2492	0	0	0
T43	361	3	0	0
T44	855	4	0	0
T45	0	4	0	0
T72	0	2	0	0
T141	1656	0	0	0
T145	764	0	0	0
T146	303	0	0	0
T147	1785	0	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71699037	162	0	0
T3	206069	1	0	0
T11	742069	0	0	0
T12	106790	0	0	0
T35	2492	0	0	0
T43	361	3	0	0
T44	855	4	0	0
T45	0	4	0	0
T72	0	2	0	0
T141	1656	0	0	0
T145	764	0	0	0
T146	303	0	0	0
T147	1785	0	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	286805371	162	0	0
CgEnOn_A	286805371	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286805371	162	0	0
T3	824250	1	0	0
T11	298889	0	0	0
T12	427684	0	0	0
T35	15780	0	0	0
T43	1538	3	0	0
T44	3487	4	0	0
T45	0	4	0	0
T72	0	2	0	0
T141	6663	0	0	0
T145	3148	0	0	0
T146	1248	0	0	0
T147	7218	0	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286805371	152	0	0
T11	298889	0	0	0
T12	427684	0	0	0
T35	15780	0	0	0
T36	53662	0	0	0
T43	1538	3	0	0
T44	3487	4	0	0
T45	0	4	0	0
T72	0	1	0	0
T145	3148	0	0	0
T146	1248	0	0	0
T147	7218	0	0	0
T148	1256	0	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	308433880	155	0	0
CgEnOn_A	308433880	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308433880	155	0	0
T11	337025	1	0	0
T12	451518	0	0	0
T35	16438	0	0	0
T36	55900	0	0	0
T43	1493	5	0	0
T44	3645	2	0	0
T45	0	4	0	0
T145	3279	0	0	0
T146	1301	0	0	0
T147	7519	0	0	0
T148	1308	0	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	1	0	0
T168	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308433880	153	0	0
T11	337025	0	0	0
T12	451518	0	0	0
T35	16438	0	0	0
T36	55900	0	0	0
T43	1493	5	0	0
T44	3645	2	0	0
T45	0	4	0	0
T145	3279	0	0	0
T146	1301	0	0	0
T147	7519	0	0	0
T148	1308	0	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	71699037	162	0	0
CgEnOn_A	71699037	162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71699037	162	0	0
T3	206069	1	0	0
T11	742069	0	0	0
T12	106790	0	0	0
T35	2492	0	0	0
T43	361	3	0	0
T44	855	4	0	0
T45	0	4	0	0
T72	0	2	0	0
T141	1656	0	0	0
T145	764	0	0	0
T146	303	0	0	0
T147	1785	0	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71699037	162	0	0
T3	206069	1	0	0
T11	742069	0	0	0
T12	106790	0	0	0
T35	2492	0	0	0
T43	361	3	0	0
T44	855	4	0	0
T45	0	4	0	0
T72	0	2	0	0
T141	1656	0	0	0
T145	764	0	0	0
T146	303	0	0	0
T147	1785	0	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	308433880	155	0	0
CgEnOn_A	308433880	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308433880	155	0	0
T11	337025	1	0	0
T12	451518	0	0	0
T35	16438	0	0	0
T36	55900	0	0	0
T43	1493	5	0	0
T44	3645	2	0	0
T45	0	4	0	0
T145	3279	0	0	0
T146	1301	0	0	0
T147	7519	0	0	0
T148	1308	0	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	1	0	0
T168	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308433880	153	0	0
T11	337025	0	0	0
T12	451518	0	0	0
T35	16438	0	0	0
T36	55900	0	0	0
T43	1493	5	0	0
T44	3645	2	0	0
T45	0	4	0	0
T145	3279	0	0	0
T146	1301	0	0	0
T147	7519	0	0	0
T148	1308	0	0	0
T161	0	3	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	4	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	71699037	162	0	0
CgEnOn_A	71699037	162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71699037	162	0	0
T3	206069	1	0	0
T11	742069	0	0	0
T12	106790	0	0	0
T35	2492	0	0	0
T43	361	3	0	0
T44	855	4	0	0
T45	0	4	0	0
T72	0	2	0	0
T141	1656	0	0	0
T145	764	0	0	0
T146	303	0	0	0
T147	1785	0	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71699037	162	0	0
T3	206069	1	0	0
T11	742069	0	0	0
T12	106790	0	0	0
T35	2492	0	0	0
T43	361	3	0	0
T44	855	4	0	0
T45	0	4	0	0
T72	0	2	0	0
T141	1656	0	0	0
T145	764	0	0	0
T146	303	0	0	0
T147	1785	0	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T43,T44,T45
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	143399245	7265	0	0
CgEnOn_A	143399245	5038	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143399245	7265	0	0
T4	30236	13	0	0
T5	64674	1	0	0
T6	38293	1	0	0
T7	5015	1	0	0
T8	1010	2	0	0
T26	1219	1	0	0
T27	3071	1	0	0
T28	12810	1	0	0
T29	4884	1	0	0
T30	2561	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143399245	5038	0	0
T1	0	38	0	0
T3	0	70	0	0
T4	30236	0	0	0
T5	64674	0	0	0
T6	38293	0	0	0
T8	1010	1	0	0
T11	0	29	0	0
T24	0	2	0	0
T26	1219	0	0	0
T27	3071	0	0	0
T28	12810	0	0	0
T29	4884	0	0	0
T30	2561	0	0	0
T33	3941	0	0	0
T43	0	3	0	0
T44	0	4	0	0
T46	0	1	0	0
T141	0	1	0	0
T145	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T43,T44,T45
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	71699037	7200	0	0
CgEnOn_A	71699037	4973	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71699037	7200	0	0
T4	15118	13	0	0
T5	32337	1	0	0
T6	19147	1	0	0
T7	2507	1	0	0
T8	505	2	0	0
T26	609	1	0	0
T27	1535	1	0	0
T28	6403	1	0	0
T29	2442	1	0	0
T30	1281	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71699037	4973	0	0
T1	0	40	0	0
T3	0	65	0	0
T4	15118	0	0	0
T5	32337	0	0	0
T6	19147	0	0	0
T8	505	1	0	0
T11	0	29	0	0
T24	0	2	0	0
T26	609	0	0	0
T27	1535	0	0	0
T28	6403	0	0	0
T29	2442	0	0	0
T30	1281	0	0	0
T33	1968	0	0	0
T43	0	3	0	0
T44	0	4	0	0
T46	0	1	0	0
T141	0	1	0	0
T145	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T43,T44,T45
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	286805371	7260	0	0
CgEnOn_A	286805371	5023	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286805371	7260	0	0
T4	95082	13	0	0
T5	129428	1	0	0
T6	76611	1	0	0
T7	9939	1	0	0
T8	2057	2	0	0
T26	2267	1	0	0
T27	5726	1	0	0
T28	21276	1	0	0
T29	9876	1	0	0
T30	5147	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286805371	5023	0	0
T1	0	38	0	0
T3	0	66	0	0
T4	95082	0	0	0
T5	129428	0	0	0
T6	76611	0	0	0
T8	2057	1	0	0
T11	0	29	0	0
T24	0	2	0	0
T26	2267	0	0	0
T27	5726	0	0	0
T28	21276	0	0	0
T29	9876	0	0	0
T30	5147	0	0	0
T33	6696	0	0	0
T43	0	3	0	0
T44	0	4	0	0
T46	0	1	0	0
T141	0	1	0	0
T145	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T43,T44,T45
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	148146453	7262	0	0
CgEnOn_A	148146453	5021	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148146453	7262	0	0
T4	47543	13	0	0
T5	84877	1	0	0
T6	46948	1	0	0
T7	4969	1	0	0
T8	1029	2	0	0
T26	1134	1	0	0
T27	2864	1	0	0
T28	10638	1	0	0
T29	4938	1	0	0
T30	2574	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148146453	5021	0	0
T1	0	40	0	0
T3	0	65	0	0
T4	47543	0	0	0
T5	84877	0	0	0
T6	46948	0	0	0
T8	1029	1	0	0
T11	0	32	0	0
T24	0	2	0	0
T26	1134	0	0	0
T27	2864	0	0	0
T28	10638	0	0	0
T29	4938	0	0	0
T30	2574	0	0	0
T33	3347	0	0	0
T43	0	6	0	0
T44	0	2	0	0
T46	0	1	0	0
T141	0	1	0	0
T145	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T8,T29,T30
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	308433880	3628	0	0
CgEnOn_A	308433880	3626	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308433880	3628	0	0
T1	0	31	0	0
T2	0	4	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2143	1	0	0
T18	0	2	0	0
T26	2361	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10287	7	0	0
T30	5362	2	0	0
T33	6974	0	0	0
T75	0	6	0	0
T76	0	6	0	0
T109	0	6	0	0
T110	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308433880	3626	0	0
T1	0	31	0	0
T2	0	4	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2143	1	0	0
T18	0	2	0	0
T26	2361	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10287	7	0	0
T30	5362	2	0	0
T33	6974	0	0	0
T75	0	6	0	0
T76	0	6	0	0
T109	0	6	0	0
T110	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T8,T29,T30
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	308433880	3585	0	0
CgEnOn_A	308433880	3583	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308433880	3585	0	0
T1	0	40	0	0
T2	0	2	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2143	1	0	0
T18	0	1	0	0
T26	2361	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10287	10	0	0
T30	5362	6	0	0
T33	6974	0	0	0
T75	0	5	0	0
T76	0	4	0	0
T109	0	2	0	0
T110	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308433880	3583	0	0
T1	0	40	0	0
T2	0	2	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2143	1	0	0
T18	0	1	0	0
T26	2361	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10287	10	0	0
T30	5362	6	0	0
T33	6974	0	0	0
T75	0	5	0	0
T76	0	4	0	0
T109	0	2	0	0
T110	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T8,T29,T30
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	308433880	3589	0	0
CgEnOn_A	308433880	3587	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308433880	3589	0	0
T1	0	29	0	0
T2	0	5	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2143	1	0	0
T18	0	2	0	0
T26	2361	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10287	5	0	0
T30	5362	4	0	0
T33	6974	0	0	0
T75	0	6	0	0
T76	0	4	0	0
T109	0	8	0	0
T110	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308433880	3587	0	0
T1	0	29	0	0
T2	0	5	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2143	1	0	0
T18	0	2	0	0
T26	2361	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10287	5	0	0
T30	5362	4	0	0
T33	6974	0	0	0
T75	0	6	0	0
T76	0	4	0	0
T109	0	8	0	0
T110	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T8,T29,T30
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	308433880	3629	0	0
CgEnOn_A	308433880	3627	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308433880	3629	0	0
T1	0	35	0	0
T2	0	4	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2143	1	0	0
T18	0	3	0	0
T26	2361	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10287	9	0	0
T30	5362	4	0	0
T33	6974	0	0	0
T75	0	6	0	0
T76	0	4	0	0
T109	0	6	0	0
T110	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	308433880	3627	0	0
T1	0	35	0	0
T2	0	4	0	0
T4	99047	0	0	0
T5	164826	0	0	0
T6	97807	0	0	0
T8	2143	1	0	0
T18	0	3	0	0
T26	2361	0	0	0
T27	5966	0	0	0
T28	22163	0	0	0
T29	10287	9	0	0
T30	5362	4	0	0
T33	6974	0	0	0
T75	0	6	0	0
T76	0	4	0	0
T109	0	6	0	0
T110	0	3	0	0