Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T1,T46
0	1	Covered	T1,T24,T3
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T24
1	0	Covered	T43,T44,T45
1	1	Covered	T7,T8,T5

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	650051748	13005	0	0
GateOpen_A	650051748	13005	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650051748	13005	0	0
T1	108929	109	0	0
T2	104055	0	0	0
T3	0	179	0	0
T4	172863	0	0	0
T5	278982	0	0	0
T6	161854	0	0	0
T8	4097	3	0	0
T11	0	73	0	0
T12	0	3	0	0
T18	424	0	0	0
T19	1897	0	0	0
T20	762	0	0	0
T21	828	0	0	0
T22	1635	0	0	0
T23	9028	0	0	0
T24	989	0	0	0
T25	1795	0	0	0
T26	4622	0	0	0
T27	11662	0	0	0
T28	44724	0	0	0
T29	19701	0	0	0
T30	10283	0	0	0
T33	13985	0	0	0
T43	0	15	0	0
T44	0	14	0	0
T46	0	4	0	0
T141	0	4	0	0
T145	0	35	0	0
T147	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650051748	13005	0	0
T1	108929	109	0	0
T2	104055	0	0	0
T3	0	179	0	0
T4	172863	0	0	0
T5	278982	0	0	0
T6	161854	0	0	0
T8	4097	3	0	0
T11	0	73	0	0
T12	0	3	0	0
T18	424	0	0	0
T19	1897	0	0	0
T20	762	0	0	0
T21	828	0	0	0
T22	1635	0	0	0
T23	9028	0	0	0
T24	989	0	0	0
T25	1795	0	0	0
T26	4622	0	0	0
T27	11662	0	0	0
T28	44724	0	0	0
T29	19701	0	0	0
T30	10283	0	0	0
T33	13985	0	0	0
T43	0	15	0	0
T44	0	14	0	0
T46	0	4	0	0
T141	0	4	0	0
T145	0	35	0	0
T147	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T1,T46
0	1	Covered	T1,T24,T3
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T24
1	0	Covered	T43,T44,T45
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	71699436	3206	0	0
GateOpen_A	71699436	3206	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71699436	3206	0	0
T1	108929	27	0	0
T2	104055	0	0	0
T3	0	46	0	0
T11	0	16	0	0
T12	0	3	0	0
T18	424	0	0	0
T19	1897	0	0	0
T20	762	0	0	0
T21	828	0	0	0
T22	1635	0	0	0
T23	9028	0	0	0
T24	989	0	0	0
T25	1795	0	0	0
T43	0	3	0	0
T44	0	4	0	0
T46	0	1	0	0
T141	0	1	0	0
T145	0	9	0	0
T147	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71699436	3206	0	0
T1	108929	27	0	0
T2	104055	0	0	0
T3	0	46	0	0
T11	0	16	0	0
T12	0	3	0	0
T18	424	0	0	0
T19	1897	0	0	0
T20	762	0	0	0
T21	828	0	0	0
T22	1635	0	0	0
T23	9028	0	0	0
T24	989	0	0	0
T25	1795	0	0	0
T43	0	3	0	0
T44	0	4	0	0
T46	0	1	0	0
T141	0	1	0	0
T145	0	9	0	0
T147	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T1,T46
0	1	Covered	T1,T24,T3
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T24
1	0	Covered	T43,T44,T45
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	143399646	3256	0	0
GateOpen_A	143399646	3256	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143399646	3256	0	0
T1	0	27	0	0
T3	0	43	0	0
T4	30237	0	0	0
T5	64675	0	0	0
T6	38294	0	0	0
T8	1010	1	0	0
T11	0	18	0	0
T26	1220	0	0	0
T27	3071	0	0	0
T28	12810	0	0	0
T29	4885	0	0	0
T30	2562	0	0	0
T33	3941	0	0	0
T43	0	3	0	0
T44	0	4	0	0
T46	0	1	0	0
T141	0	1	0	0
T145	0	8	0	0
T147	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143399646	3256	0	0
T1	0	27	0	0
T3	0	43	0	0
T4	30237	0	0	0
T5	64675	0	0	0
T6	38294	0	0	0
T8	1010	1	0	0
T11	0	18	0	0
T26	1220	0	0	0
T27	3071	0	0	0
T28	12810	0	0	0
T29	4885	0	0	0
T30	2562	0	0	0
T33	3941	0	0	0
T43	0	3	0	0
T44	0	4	0	0
T46	0	1	0	0
T141	0	1	0	0
T145	0	8	0	0
T147	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T1,T46
0	1	Covered	T1,T24,T3
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T24
1	0	Covered	T43,T44,T45
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	286805824	3283	0	0
GateOpen_A	286805824	3283	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286805824	3283	0	0
T1	0	28	0	0
T3	0	45	0	0
T4	95082	0	0	0
T5	129429	0	0	0
T6	76612	0	0	0
T8	2058	1	0	0
T11	0	18	0	0
T26	2268	0	0	0
T27	5727	0	0	0
T28	21276	0	0	0
T29	9877	0	0	0
T30	5147	0	0	0
T33	6696	0	0	0
T43	0	3	0	0
T44	0	4	0	0
T46	0	1	0	0
T141	0	1	0	0
T145	0	9	0	0
T147	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286805824	3283	0	0
T1	0	28	0	0
T3	0	45	0	0
T4	95082	0	0	0
T5	129429	0	0	0
T6	76612	0	0	0
T8	2058	1	0	0
T11	0	18	0	0
T26	2268	0	0	0
T27	5727	0	0	0
T28	21276	0	0	0
T29	9877	0	0	0
T30	5147	0	0	0
T33	6696	0	0	0
T43	0	3	0	0
T44	0	4	0	0
T46	0	1	0	0
T141	0	1	0	0
T145	0	9	0	0
T147	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T1,T46
0	1	Covered	T1,T24,T3
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T1,T24
1	0	Covered	T43,T44,T45
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	148146842	3260	0	0
GateOpen_A	148146842	3260	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148146842	3260	0	0
T1	0	27	0	0
T3	0	45	0	0
T4	47544	0	0	0
T5	84878	0	0	0
T6	46948	0	0	0
T8	1029	1	0	0
T11	0	21	0	0
T26	1134	0	0	0
T27	2864	0	0	0
T28	10638	0	0	0
T29	4939	0	0	0
T30	2574	0	0	0
T33	3348	0	0	0
T43	0	6	0	0
T44	0	2	0	0
T46	0	1	0	0
T141	0	1	0	0
T145	0	9	0	0
T147	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148146842	3260	0	0
T1	0	27	0	0
T3	0	45	0	0
T4	47544	0	0	0
T5	84878	0	0	0
T6	46948	0	0	0
T8	1029	1	0	0
T11	0	21	0	0
T26	1134	0	0	0
T27	2864	0	0	0
T28	10638	0	0	0
T29	4939	0	0	0
T30	2574	0	0	0
T33	3348	0	0	0
T43	0	6	0	0
T44	0	2	0	0
T46	0	1	0	0
T141	0	1	0	0
T145	0	9	0	0
T147	0	1	0	0