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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.51 99.15 95.79 100.00 100.00 98.81 97.01 98.80


Total test records in report: 1010
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T807 /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3688222390 Mar 26 12:39:14 PM PDT 24 Mar 26 12:39:15 PM PDT 24 98743418 ps
T808 /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.3483982612 Mar 26 12:38:59 PM PDT 24 Mar 26 12:39:00 PM PDT 24 172129547 ps
T809 /workspace/coverage/default/30.clkmgr_extclk.3932279419 Mar 26 12:38:40 PM PDT 24 Mar 26 12:38:41 PM PDT 24 69358440 ps
T810 /workspace/coverage/default/0.clkmgr_stress_all.521629650 Mar 26 12:37:23 PM PDT 24 Mar 26 12:37:24 PM PDT 24 31574398 ps
T811 /workspace/coverage/default/19.clkmgr_frequency.1424838911 Mar 26 12:38:12 PM PDT 24 Mar 26 12:38:19 PM PDT 24 1367708506 ps
T812 /workspace/coverage/default/35.clkmgr_peri.1422254147 Mar 26 12:38:45 PM PDT 24 Mar 26 12:38:46 PM PDT 24 14850216 ps
T813 /workspace/coverage/default/34.clkmgr_stress_all.3814287255 Mar 26 12:38:44 PM PDT 24 Mar 26 12:39:11 PM PDT 24 8264032984 ps
T814 /workspace/coverage/default/30.clkmgr_smoke.2053572987 Mar 26 12:38:44 PM PDT 24 Mar 26 12:38:45 PM PDT 24 28482972 ps
T815 /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.1250940394 Mar 26 12:38:59 PM PDT 24 Mar 26 12:39:00 PM PDT 24 22213976 ps
T816 /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.665510946 Mar 26 12:39:33 PM PDT 24 Mar 26 12:39:34 PM PDT 24 70410355 ps
T817 /workspace/coverage/default/26.clkmgr_stress_all.3327371385 Mar 26 12:38:34 PM PDT 24 Mar 26 12:38:48 PM PDT 24 2401525561 ps
T818 /workspace/coverage/default/39.clkmgr_smoke.1716083294 Mar 26 12:38:58 PM PDT 24 Mar 26 12:38:59 PM PDT 24 17688076 ps
T10 /workspace/coverage/default/34.clkmgr_regwen.2551418021 Mar 26 12:38:45 PM PDT 24 Mar 26 12:38:49 PM PDT 24 582966667 ps
T819 /workspace/coverage/default/45.clkmgr_extclk.1292456231 Mar 26 12:39:25 PM PDT 24 Mar 26 12:39:26 PM PDT 24 51294885 ps
T820 /workspace/coverage/default/24.clkmgr_peri.2919162150 Mar 26 12:38:26 PM PDT 24 Mar 26 12:38:27 PM PDT 24 64563760 ps
T821 /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.2869443201 Mar 26 12:37:45 PM PDT 24 Mar 26 12:37:48 PM PDT 24 578598928 ps
T822 /workspace/coverage/default/27.clkmgr_peri.1791850005 Mar 26 12:38:37 PM PDT 24 Mar 26 12:38:38 PM PDT 24 43391571 ps
T823 /workspace/coverage/default/38.clkmgr_div_intersig_mubi.4071832859 Mar 26 12:39:02 PM PDT 24 Mar 26 12:39:03 PM PDT 24 24890972 ps
T824 /workspace/coverage/default/48.clkmgr_frequency_timeout.2743105043 Mar 26 12:39:30 PM PDT 24 Mar 26 12:39:35 PM PDT 24 494341826 ps
T825 /workspace/coverage/default/0.clkmgr_div_intersig_mubi.919035462 Mar 26 12:37:19 PM PDT 24 Mar 26 12:37:20 PM PDT 24 21557001 ps
T826 /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.3899140316 Mar 26 12:37:35 PM PDT 24 Mar 26 12:37:36 PM PDT 24 16813166 ps
T827 /workspace/coverage/default/7.clkmgr_regwen.1558687070 Mar 26 12:37:45 PM PDT 24 Mar 26 12:37:47 PM PDT 24 243246004 ps
T828 /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.3058488225 Mar 26 12:37:45 PM PDT 24 Mar 26 12:37:46 PM PDT 24 152655754 ps
T829 /workspace/coverage/default/27.clkmgr_clk_status.1537723166 Mar 26 12:38:33 PM PDT 24 Mar 26 12:38:34 PM PDT 24 25153409 ps
T830 /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.1348202860 Mar 26 12:39:23 PM PDT 24 Mar 26 12:39:25 PM PDT 24 41304845 ps
T831 /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.3531558695 Mar 26 12:38:41 PM PDT 24 Mar 26 12:38:42 PM PDT 24 24335719 ps
T832 /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.328436578 Mar 26 12:38:54 PM PDT 24 Mar 26 12:38:55 PM PDT 24 31519366 ps
T833 /workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.4082196549 Mar 26 12:37:28 PM PDT 24 Mar 26 12:40:13 PM PDT 24 10531814154 ps
T834 /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.570324237 Mar 26 12:39:00 PM PDT 24 Mar 26 12:39:01 PM PDT 24 27832695 ps
T835 /workspace/coverage/default/18.clkmgr_extclk.44242625 Mar 26 12:38:12 PM PDT 24 Mar 26 12:38:13 PM PDT 24 41991077 ps
T836 /workspace/coverage/default/23.clkmgr_regwen.2261113780 Mar 26 12:38:26 PM PDT 24 Mar 26 12:38:29 PM PDT 24 528204419 ps
T837 /workspace/coverage/default/2.clkmgr_frequency_timeout.1528681622 Mar 26 12:37:32 PM PDT 24 Mar 26 12:37:34 PM PDT 24 142380465 ps
T838 /workspace/coverage/default/11.clkmgr_div_intersig_mubi.2048134660 Mar 26 12:37:53 PM PDT 24 Mar 26 12:37:54 PM PDT 24 13445857 ps
T839 /workspace/coverage/default/24.clkmgr_frequency_timeout.2785651689 Mar 26 12:38:31 PM PDT 24 Mar 26 12:38:39 PM PDT 24 1094467285 ps
T840 /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.1416017662 Mar 26 12:39:02 PM PDT 24 Mar 26 12:39:03 PM PDT 24 14732871 ps
T841 /workspace/coverage/default/49.clkmgr_regwen.3588696954 Mar 26 12:39:31 PM PDT 24 Mar 26 12:39:39 PM PDT 24 1233524425 ps
T842 /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.1075523464 Mar 26 12:39:27 PM PDT 24 Mar 26 12:39:28 PM PDT 24 26023203 ps
T843 /workspace/coverage/default/39.clkmgr_clk_status.1235207570 Mar 26 12:38:58 PM PDT 24 Mar 26 12:38:59 PM PDT 24 18084681 ps
T844 /workspace/coverage/default/44.clkmgr_alert_test.1210156340 Mar 26 12:39:22 PM PDT 24 Mar 26 12:39:23 PM PDT 24 44704077 ps
T845 /workspace/coverage/default/47.clkmgr_div_intersig_mubi.1196648556 Mar 26 12:39:30 PM PDT 24 Mar 26 12:39:32 PM PDT 24 75630061 ps
T846 /workspace/coverage/default/14.clkmgr_smoke.3756944810 Mar 26 12:38:04 PM PDT 24 Mar 26 12:38:05 PM PDT 24 16655166 ps
T847 /workspace/coverage/default/48.clkmgr_extclk.383286732 Mar 26 12:39:32 PM PDT 24 Mar 26 12:39:34 PM PDT 24 77224674 ps
T848 /workspace/coverage/default/42.clkmgr_regwen.198247898 Mar 26 12:39:16 PM PDT 24 Mar 26 12:39:19 PM PDT 24 597561055 ps
T849 /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.758160495 Mar 26 12:38:26 PM PDT 24 Mar 26 12:38:27 PM PDT 24 84637001 ps
T850 /workspace/coverage/default/3.clkmgr_div_intersig_mubi.3116432220 Mar 26 12:37:31 PM PDT 24 Mar 26 12:37:32 PM PDT 24 20967691 ps
T851 /workspace/coverage/default/13.clkmgr_div_intersig_mubi.843655521 Mar 26 12:37:58 PM PDT 24 Mar 26 12:37:59 PM PDT 24 39699358 ps
T852 /workspace/coverage/default/41.clkmgr_clk_status.2149000212 Mar 26 12:39:25 PM PDT 24 Mar 26 12:39:26 PM PDT 24 22890728 ps
T853 /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.3432551261 Mar 26 12:37:44 PM PDT 24 Mar 26 12:37:45 PM PDT 24 19883273 ps
T854 /workspace/coverage/default/7.clkmgr_frequency_timeout.2598375866 Mar 26 12:37:45 PM PDT 24 Mar 26 12:37:48 PM PDT 24 943390810 ps
T855 /workspace/coverage/default/42.clkmgr_clk_status.4113907820 Mar 26 12:39:27 PM PDT 24 Mar 26 12:39:29 PM PDT 24 15671970 ps
T856 /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.2819172990 Mar 26 12:39:21 PM PDT 24 Mar 26 12:39:23 PM PDT 24 73994647 ps
T857 /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1720518432 Mar 26 12:39:15 PM PDT 24 Mar 26 12:39:17 PM PDT 24 71082521 ps
T858 /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.1761655276 Mar 26 12:39:17 PM PDT 24 Mar 26 12:39:18 PM PDT 24 53306702 ps
T859 /workspace/coverage/default/15.clkmgr_extclk.3952032905 Mar 26 12:38:08 PM PDT 24 Mar 26 12:38:10 PM PDT 24 31144068 ps
T860 /workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.2024146869 Mar 26 12:37:48 PM PDT 24 Mar 26 12:53:49 PM PDT 24 136107416241 ps
T60 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.3806649895 Mar 26 01:11:17 PM PDT 24 Mar 26 01:11:19 PM PDT 24 114122193 ps
T861 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.1426902890 Mar 26 01:12:02 PM PDT 24 Mar 26 01:12:02 PM PDT 24 23458851 ps
T100 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1423522014 Mar 26 01:10:55 PM PDT 24 Mar 26 01:10:56 PM PDT 24 20466756 ps
T61 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3522147174 Mar 26 01:11:59 PM PDT 24 Mar 26 01:12:03 PM PDT 24 179372619 ps
T862 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.3885528991 Mar 26 01:11:49 PM PDT 24 Mar 26 01:11:50 PM PDT 24 23546513 ps
T863 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.2764200693 Mar 26 01:12:01 PM PDT 24 Mar 26 01:12:01 PM PDT 24 13819215 ps
T101 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2327735101 Mar 26 01:11:02 PM PDT 24 Mar 26 01:11:04 PM PDT 24 208883245 ps
T864 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.2930345533 Mar 26 01:11:58 PM PDT 24 Mar 26 01:11:59 PM PDT 24 12828542 ps
T82 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.2186771968 Mar 26 01:11:17 PM PDT 24 Mar 26 01:11:20 PM PDT 24 201141221 ps
T62 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3509281021 Mar 26 01:12:01 PM PDT 24 Mar 26 01:12:04 PM PDT 24 516937224 ps
T64 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.16951380 Mar 26 01:11:00 PM PDT 24 Mar 26 01:11:02 PM PDT 24 52545165 ps
T865 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.577981850 Mar 26 01:11:59 PM PDT 24 Mar 26 01:12:00 PM PDT 24 88308604 ps
T866 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.840312623 Mar 26 01:12:03 PM PDT 24 Mar 26 01:12:05 PM PDT 24 22519141 ps
T83 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3152231700 Mar 26 01:11:29 PM PDT 24 Mar 26 01:11:30 PM PDT 24 32459462 ps
T867 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.4199660535 Mar 26 01:12:04 PM PDT 24 Mar 26 01:12:05 PM PDT 24 15541285 ps
T868 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2818822942 Mar 26 01:12:03 PM PDT 24 Mar 26 01:12:05 PM PDT 24 20837539 ps
T869 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3320729139 Mar 26 01:11:03 PM PDT 24 Mar 26 01:11:12 PM PDT 24 696999995 ps
T66 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3710514820 Mar 26 01:11:43 PM PDT 24 Mar 26 01:11:47 PM PDT 24 71169338 ps
T870 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3580432212 Mar 26 01:11:17 PM PDT 24 Mar 26 01:11:18 PM PDT 24 18932562 ps
T84 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1860696581 Mar 26 01:11:32 PM PDT 24 Mar 26 01:11:33 PM PDT 24 54776444 ps
T85 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.2710845904 Mar 26 01:12:00 PM PDT 24 Mar 26 01:12:01 PM PDT 24 57500004 ps
T871 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.625044119 Mar 26 01:11:02 PM PDT 24 Mar 26 01:11:05 PM PDT 24 207660865 ps
T86 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3524401128 Mar 26 01:11:16 PM PDT 24 Mar 26 01:11:18 PM PDT 24 190223906 ps
T67 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.2767531263 Mar 26 01:11:44 PM PDT 24 Mar 26 01:11:49 PM PDT 24 455014948 ps
T872 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3776046366 Mar 26 01:10:53 PM PDT 24 Mar 26 01:10:53 PM PDT 24 21100594 ps
T873 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.2051259999 Mar 26 01:12:04 PM PDT 24 Mar 26 01:12:06 PM PDT 24 19227040 ps
T874 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.4142931747 Mar 26 01:11:45 PM PDT 24 Mar 26 01:11:46 PM PDT 24 27793781 ps
T875 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1514501906 Mar 26 01:11:28 PM PDT 24 Mar 26 01:11:30 PM PDT 24 54247359 ps
T876 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.3605677712 Mar 26 01:11:15 PM PDT 24 Mar 26 01:11:17 PM PDT 24 12143189 ps
T94 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1001081850 Mar 26 01:11:46 PM PDT 24 Mar 26 01:11:48 PM PDT 24 61885796 ps
T95 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1743366819 Mar 26 01:11:29 PM PDT 24 Mar 26 01:11:31 PM PDT 24 70385844 ps
T96 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1125812016 Mar 26 01:11:32 PM PDT 24 Mar 26 01:11:34 PM PDT 24 113530209 ps
T68 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.793372022 Mar 26 01:11:17 PM PDT 24 Mar 26 01:11:20 PM PDT 24 313432928 ps
T877 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3162357478 Mar 26 01:11:29 PM PDT 24 Mar 26 01:11:30 PM PDT 24 12349896 ps
T878 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.1405705240 Mar 26 01:12:02 PM PDT 24 Mar 26 01:12:03 PM PDT 24 166984471 ps
T879 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1122216892 Mar 26 01:11:49 PM PDT 24 Mar 26 01:11:50 PM PDT 24 38315203 ps
T880 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1001339942 Mar 26 01:12:01 PM PDT 24 Mar 26 01:12:02 PM PDT 24 15303487 ps
T881 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.357072232 Mar 26 01:12:02 PM PDT 24 Mar 26 01:12:03 PM PDT 24 91419870 ps
T65 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2158801327 Mar 26 01:11:29 PM PDT 24 Mar 26 01:11:31 PM PDT 24 216447591 ps
T882 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2649093527 Mar 26 01:11:45 PM PDT 24 Mar 26 01:11:47 PM PDT 24 33382990 ps
T883 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.4162870008 Mar 26 01:11:46 PM PDT 24 Mar 26 01:11:49 PM PDT 24 234484913 ps
T884 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.2207792800 Mar 26 01:11:31 PM PDT 24 Mar 26 01:11:32 PM PDT 24 11300116 ps
T107 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.988166282 Mar 26 01:11:59 PM PDT 24 Mar 26 01:12:02 PM PDT 24 194182983 ps
T885 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3570138138 Mar 26 01:12:02 PM PDT 24 Mar 26 01:12:03 PM PDT 24 28094581 ps
T886 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.2028643448 Mar 26 01:12:04 PM PDT 24 Mar 26 01:12:05 PM PDT 24 20715427 ps
T887 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.100482859 Mar 26 01:12:00 PM PDT 24 Mar 26 01:12:01 PM PDT 24 30153275 ps
T117 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.40974496 Mar 26 01:11:17 PM PDT 24 Mar 26 01:11:19 PM PDT 24 408815523 ps
T888 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.2907446965 Mar 26 01:12:14 PM PDT 24 Mar 26 01:12:15 PM PDT 24 14541650 ps
T889 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.3150063301 Mar 26 01:11:30 PM PDT 24 Mar 26 01:11:31 PM PDT 24 20019232 ps
T890 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.244504592 Mar 26 01:11:30 PM PDT 24 Mar 26 01:11:31 PM PDT 24 20734860 ps
T891 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.305789829 Mar 26 01:11:43 PM PDT 24 Mar 26 01:11:45 PM PDT 24 14929598 ps
T63 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1911961124 Mar 26 01:11:45 PM PDT 24 Mar 26 01:11:47 PM PDT 24 76206412 ps
T118 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3063426010 Mar 26 01:11:16 PM PDT 24 Mar 26 01:11:19 PM PDT 24 229903565 ps
T892 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1151950766 Mar 26 01:11:46 PM PDT 24 Mar 26 01:11:48 PM PDT 24 21074741 ps
T893 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.467686255 Mar 26 01:11:59 PM PDT 24 Mar 26 01:12:00 PM PDT 24 31782574 ps
T169 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.2545488827 Mar 26 01:11:00 PM PDT 24 Mar 26 01:11:02 PM PDT 24 69605935 ps
T131 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3072156431 Mar 26 01:11:35 PM PDT 24 Mar 26 01:11:37 PM PDT 24 137155137 ps
T894 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3555319300 Mar 26 01:11:27 PM PDT 24 Mar 26 01:11:29 PM PDT 24 18230834 ps
T895 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2268671764 Mar 26 01:12:01 PM PDT 24 Mar 26 01:12:01 PM PDT 24 13663829 ps
T119 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3677204244 Mar 26 01:11:46 PM PDT 24 Mar 26 01:11:49 PM PDT 24 107762436 ps
T102 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2942584897 Mar 26 01:11:17 PM PDT 24 Mar 26 01:11:19 PM PDT 24 56202258 ps
T896 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3034219314 Mar 26 01:12:05 PM PDT 24 Mar 26 01:12:06 PM PDT 24 41730712 ps
T139 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2810338465 Mar 26 01:11:35 PM PDT 24 Mar 26 01:11:38 PM PDT 24 173827012 ps
T897 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2534435958 Mar 26 01:11:16 PM PDT 24 Mar 26 01:11:17 PM PDT 24 37938205 ps
T898 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.288733383 Mar 26 01:11:46 PM PDT 24 Mar 26 01:11:49 PM PDT 24 279243415 ps
T899 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3993785763 Mar 26 01:11:31 PM PDT 24 Mar 26 01:11:32 PM PDT 24 11819793 ps
T900 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1490760782 Mar 26 01:10:51 PM PDT 24 Mar 26 01:10:55 PM PDT 24 347611720 ps
T170 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2631255922 Mar 26 01:11:30 PM PDT 24 Mar 26 01:11:32 PM PDT 24 110899718 ps
T901 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.930533828 Mar 26 01:11:17 PM PDT 24 Mar 26 01:11:19 PM PDT 24 127466295 ps
T902 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.2520785119 Mar 26 01:11:16 PM PDT 24 Mar 26 01:11:19 PM PDT 24 125601550 ps
T903 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.885818977 Mar 26 01:11:31 PM PDT 24 Mar 26 01:11:32 PM PDT 24 18867119 ps
T904 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.608692641 Mar 26 01:11:00 PM PDT 24 Mar 26 01:11:01 PM PDT 24 21321588 ps
T905 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.4268589458 Mar 26 01:11:45 PM PDT 24 Mar 26 01:11:47 PM PDT 24 36397423 ps
T906 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3733283247 Mar 26 01:12:03 PM PDT 24 Mar 26 01:12:05 PM PDT 24 65944240 ps
T907 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3140993230 Mar 26 01:11:35 PM PDT 24 Mar 26 01:11:37 PM PDT 24 54535057 ps
T908 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3530854212 Mar 26 01:11:32 PM PDT 24 Mar 26 01:11:33 PM PDT 24 44464160 ps
T132 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1402336708 Mar 26 01:11:30 PM PDT 24 Mar 26 01:11:33 PM PDT 24 603652050 ps
T120 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3803309337 Mar 26 01:11:45 PM PDT 24 Mar 26 01:11:47 PM PDT 24 109608144 ps
T909 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.2236393063 Mar 26 01:11:16 PM PDT 24 Mar 26 01:11:17 PM PDT 24 16801639 ps
T910 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.683516411 Mar 26 01:11:31 PM PDT 24 Mar 26 01:11:32 PM PDT 24 44750735 ps
T911 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2702873937 Mar 26 01:12:13 PM PDT 24 Mar 26 01:12:14 PM PDT 24 66189978 ps
T912 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.1029833924 Mar 26 01:11:17 PM PDT 24 Mar 26 01:11:25 PM PDT 24 419930387 ps
T913 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2962843878 Mar 26 01:11:48 PM PDT 24 Mar 26 01:11:49 PM PDT 24 69530572 ps
T125 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3090425476 Mar 26 01:10:52 PM PDT 24 Mar 26 01:10:56 PM PDT 24 173722992 ps
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T98 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3917390625 Mar 26 01:11:16 PM PDT 24 Mar 26 01:11:18 PM PDT 24 59443734 ps
T916 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2679255554 Mar 26 01:10:53 PM PDT 24 Mar 26 01:10:55 PM PDT 24 37406262 ps
T917 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.3780290944 Mar 26 01:12:01 PM PDT 24 Mar 26 01:12:01 PM PDT 24 12628748 ps
T918 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.78200796 Mar 26 01:11:15 PM PDT 24 Mar 26 01:11:21 PM PDT 24 514226452 ps
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T122 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2023971674 Mar 26 01:11:50 PM PDT 24 Mar 26 01:11:52 PM PDT 24 119664298 ps
T123 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.376639538 Mar 26 01:11:01 PM PDT 24 Mar 26 01:11:03 PM PDT 24 168892314 ps
T919 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2501469266 Mar 26 01:11:30 PM PDT 24 Mar 26 01:11:31 PM PDT 24 34291116 ps
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T921 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.842683550 Mar 26 01:12:00 PM PDT 24 Mar 26 01:12:01 PM PDT 24 16077246 ps
T171 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.3478784610 Mar 26 01:11:17 PM PDT 24 Mar 26 01:11:20 PM PDT 24 449369052 ps
T922 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2430887547 Mar 26 01:11:31 PM PDT 24 Mar 26 01:11:33 PM PDT 24 94937906 ps
T923 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.733754059 Mar 26 01:11:16 PM PDT 24 Mar 26 01:11:17 PM PDT 24 42756348 ps
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T926 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3082670739 Mar 26 01:11:28 PM PDT 24 Mar 26 01:11:31 PM PDT 24 198428079 ps
T99 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.509502797 Mar 26 01:11:31 PM PDT 24 Mar 26 01:11:34 PM PDT 24 122230760 ps
T927 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.776789357 Mar 26 01:11:46 PM PDT 24 Mar 26 01:11:48 PM PDT 24 44413674 ps
T928 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.433654903 Mar 26 01:11:59 PM PDT 24 Mar 26 01:12:00 PM PDT 24 169051969 ps
T929 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1828312159 Mar 26 01:11:35 PM PDT 24 Mar 26 01:11:36 PM PDT 24 16256720 ps
T137 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1697755072 Mar 26 01:11:14 PM PDT 24 Mar 26 01:11:15 PM PDT 24 117129607 ps
T930 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.187841384 Mar 26 01:11:18 PM PDT 24 Mar 26 01:11:19 PM PDT 24 33961401 ps
T931 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1703212032 Mar 26 01:11:29 PM PDT 24 Mar 26 01:11:30 PM PDT 24 82111383 ps
T932 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2940936837 Mar 26 01:12:01 PM PDT 24 Mar 26 01:12:02 PM PDT 24 13728330 ps
T933 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.1597469022 Mar 26 01:11:28 PM PDT 24 Mar 26 01:11:30 PM PDT 24 64863529 ps
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T103 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3689264958 Mar 26 01:10:59 PM PDT 24 Mar 26 01:11:01 PM PDT 24 117202058 ps
T934 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.2015011103 Mar 26 01:12:02 PM PDT 24 Mar 26 01:12:02 PM PDT 24 27610665 ps
T136 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.2941296256 Mar 26 01:10:53 PM PDT 24 Mar 26 01:10:56 PM PDT 24 580442915 ps
T935 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.2984396081 Mar 26 01:12:01 PM PDT 24 Mar 26 01:12:02 PM PDT 24 17389253 ps
T936 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.2067055411 Mar 26 01:11:45 PM PDT 24 Mar 26 01:11:47 PM PDT 24 15022247 ps
T937 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.4277189856 Mar 26 01:12:04 PM PDT 24 Mar 26 01:12:05 PM PDT 24 25983873 ps
T938 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1262926345 Mar 26 01:11:16 PM PDT 24 Mar 26 01:11:17 PM PDT 24 16246659 ps
T939 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2524835433 Mar 26 01:11:15 PM PDT 24 Mar 26 01:11:17 PM PDT 24 15040875 ps
T940 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3721554533 Mar 26 01:11:45 PM PDT 24 Mar 26 01:11:48 PM PDT 24 126159047 ps
T941 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.4166131152 Mar 26 01:11:05 PM PDT 24 Mar 26 01:11:07 PM PDT 24 37764174 ps
T942 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1000761270 Mar 26 01:11:29 PM PDT 24 Mar 26 01:11:30 PM PDT 24 33351027 ps
T943 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.1066182805 Mar 26 01:11:32 PM PDT 24 Mar 26 01:11:35 PM PDT 24 142892626 ps
T944 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.1562749515 Mar 26 01:11:29 PM PDT 24 Mar 26 01:11:30 PM PDT 24 18803653 ps
T945 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3399364257 Mar 26 01:11:46 PM PDT 24 Mar 26 01:11:48 PM PDT 24 106387123 ps
T946 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.957675674 Mar 26 01:11:29 PM PDT 24 Mar 26 01:11:31 PM PDT 24 175125166 ps
T947 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3920170837 Mar 26 01:11:48 PM PDT 24 Mar 26 01:11:50 PM PDT 24 73376850 ps
T948 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.70943581 Mar 26 01:12:17 PM PDT 24 Mar 26 01:12:18 PM PDT 24 18785668 ps
T949 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.122655891 Mar 26 01:12:01 PM PDT 24 Mar 26 01:12:02 PM PDT 24 13659285 ps
T124 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.65742098 Mar 26 01:12:04 PM PDT 24 Mar 26 01:12:06 PM PDT 24 191031147 ps
T950 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.2223948335 Mar 26 01:11:27 PM PDT 24 Mar 26 01:11:29 PM PDT 24 54534919 ps
T951 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.4152747029 Mar 26 01:11:01 PM PDT 24 Mar 26 01:11:02 PM PDT 24 95932132 ps
T952 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.1182783051 Mar 26 01:11:44 PM PDT 24 Mar 26 01:11:47 PM PDT 24 62062713 ps
T134 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3339173517 Mar 26 01:11:32 PM PDT 24 Mar 26 01:11:34 PM PDT 24 182729017 ps
T128 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2182679964 Mar 26 01:11:17 PM PDT 24 Mar 26 01:11:18 PM PDT 24 85622634 ps
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T954 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.849655878 Mar 26 01:11:44 PM PDT 24 Mar 26 01:11:47 PM PDT 24 121614436 ps
T138 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.4019313535 Mar 26 01:10:59 PM PDT 24 Mar 26 01:11:02 PM PDT 24 312460674 ps
T955 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.3099338234 Mar 26 01:11:01 PM PDT 24 Mar 26 01:11:02 PM PDT 24 23864779 ps
T956 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3396130061 Mar 26 01:11:59 PM PDT 24 Mar 26 01:12:00 PM PDT 24 17126813 ps
T957 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1600025132 Mar 26 01:11:47 PM PDT 24 Mar 26 01:11:48 PM PDT 24 27605403 ps
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T959 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.4044633260 Mar 26 01:12:01 PM PDT 24 Mar 26 01:12:02 PM PDT 24 88888135 ps
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T961 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.94714527 Mar 26 01:11:16 PM PDT 24 Mar 26 01:11:18 PM PDT 24 50202503 ps
T962 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.3067445273 Mar 26 01:12:00 PM PDT 24 Mar 26 01:12:01 PM PDT 24 14284102 ps
T963 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.3716010534 Mar 26 01:11:00 PM PDT 24 Mar 26 01:11:01 PM PDT 24 73193495 ps
T964 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3204397633 Mar 26 01:11:17 PM PDT 24 Mar 26 01:11:18 PM PDT 24 37761152 ps
T965 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2461063024 Mar 26 01:11:01 PM PDT 24 Mar 26 01:11:02 PM PDT 24 23714422 ps
T966 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2741769068 Mar 26 01:11:45 PM PDT 24 Mar 26 01:11:48 PM PDT 24 170985917 ps
T967 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1941058144 Mar 26 01:11:29 PM PDT 24 Mar 26 01:11:31 PM PDT 24 45508881 ps
T968 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.3068071910 Mar 26 01:11:59 PM PDT 24 Mar 26 01:12:00 PM PDT 24 15234134 ps
T969 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.805434177 Mar 26 01:10:52 PM PDT 24 Mar 26 01:10:56 PM PDT 24 144580874 ps
T970 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2029346378 Mar 26 01:11:27 PM PDT 24 Mar 26 01:11:30 PM PDT 24 175348515 ps
T971 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.3223736723 Mar 26 01:11:46 PM PDT 24 Mar 26 01:11:48 PM PDT 24 42531349 ps
T972 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3928464404 Mar 26 01:11:02 PM PDT 24 Mar 26 01:11:03 PM PDT 24 38086425 ps
T973 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1953647962 Mar 26 01:11:27 PM PDT 24 Mar 26 01:11:28 PM PDT 24 136165097 ps
T105 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.334382383 Mar 26 01:11:27 PM PDT 24 Mar 26 01:11:30 PM PDT 24 111606523 ps
T172 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.2306471252 Mar 26 01:11:59 PM PDT 24 Mar 26 01:12:06 PM PDT 24 1835858197 ps
T974 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.1031351684 Mar 26 01:11:31 PM PDT 24 Mar 26 01:11:33 PM PDT 24 58502825 ps
T975 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1862803927 Mar 26 01:11:29 PM PDT 24 Mar 26 01:11:30 PM PDT 24 19617461 ps
T976 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.37468226 Mar 26 01:11:15 PM PDT 24 Mar 26 01:11:17 PM PDT 24 75657400 ps
T977 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2104462070 Mar 26 01:11:43 PM PDT 24 Mar 26 01:11:46 PM PDT 24 111473229 ps
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T979 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.889180640 Mar 26 01:12:00 PM PDT 24 Mar 26 01:12:01 PM PDT 24 27791963 ps
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T981 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.623240345 Mar 26 01:11:58 PM PDT 24 Mar 26 01:11:59 PM PDT 24 37217991 ps
T982 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.3968611474 Mar 26 01:11:45 PM PDT 24 Mar 26 01:11:46 PM PDT 24 15443361 ps
T983 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.2875408018 Mar 26 01:11:28 PM PDT 24 Mar 26 01:11:31 PM PDT 24 90849455 ps
T984 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3060479677 Mar 26 01:12:00 PM PDT 24 Mar 26 01:12:02 PM PDT 24 62250588 ps
T985 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1665069376 Mar 26 01:11:45 PM PDT 24 Mar 26 01:11:48 PM PDT 24 42452882 ps
T986 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.2914606606 Mar 26 01:11:57 PM PDT 24 Mar 26 01:12:01 PM PDT 24 379206961 ps
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T990 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1361660708 Mar 26 01:11:03 PM PDT 24 Mar 26 01:11:04 PM PDT 24 61853199 ps
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T998 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1185337663 Mar 26 01:11:44 PM PDT 24 Mar 26 01:11:47 PM PDT 24 52626936 ps
T999 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.3540892871 Mar 26 01:11:45 PM PDT 24 Mar 26 01:11:47 PM PDT 24 79062971 ps
T106 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1372960365 Mar 26 01:11:29 PM PDT 24 Mar 26 01:11:31 PM PDT 24 98807678 ps
T104 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1477310398 Mar 26 01:11:16 PM PDT 24 Mar 26 01:11:19 PM PDT 24 111056230 ps
T129 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.884580424 Mar 26 01:11:29 PM PDT 24 Mar 26 01:11:31 PM PDT 24 176737797 ps
T1000 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.1945028755 Mar 26 01:12:00 PM PDT 24 Mar 26 01:12:01 PM PDT 24 42163407 ps
T1001 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2631078619 Mar 26 01:11:01 PM PDT 24 Mar 26 01:11:01 PM PDT 24 23581097 ps
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