Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.51	99.15	95.79	100.00	100.00	98.81	97.01	98.80

Total test records in report: 1010

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1002	/workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2866731786			Mar 26 01:11:18 PM PDT 24	Mar 26 01:11:18 PM PDT 24	17081447 ps
T1003	/workspace/coverage/cover_reg_top/2.clkmgr_intr_test.572876238			Mar 26 01:11:02 PM PDT 24	Mar 26 01:11:03 PM PDT 24	37829260 ps
T1004	/workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.891339255			Mar 26 01:11:16 PM PDT 24	Mar 26 01:11:18 PM PDT 24	59768401 ps
T1005	/workspace/coverage/cover_reg_top/30.clkmgr_intr_test.1446002407			Mar 26 01:11:59 PM PDT 24	Mar 26 01:12:00 PM PDT 24	34749386 ps
T1006	/workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.146818318			Mar 26 01:12:01 PM PDT 24	Mar 26 01:12:04 PM PDT 24	302216452 ps
T1007	/workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.2807433551			Mar 26 01:11:58 PM PDT 24	Mar 26 01:12:00 PM PDT 24	51591630 ps
T1008	/workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.261251664			Mar 26 01:11:16 PM PDT 24	Mar 26 01:11:19 PM PDT 24	224661470 ps
T1009	/workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3376584306			Mar 26 01:11:16 PM PDT 24	Mar 26 01:11:18 PM PDT 24	53052667 ps
T1010	/workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2973761075			Mar 26 01:11:44 PM PDT 24	Mar 26 01:11:48 PM PDT 24	528871813 ps
T130	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3163199253			Mar 26 01:12:04 PM PDT 24	Mar 26 01:12:08 PM PDT 24	974516296 ps

Test location	/workspace/coverage/default/3.clkmgr_frequency_timeout.4218566140
Short name	T5
Test name
Test status
Simulation time	1828281626 ps
CPU time	9.4 seconds
Started	Mar 26 12:37:29 PM PDT 24
Finished	Mar 26 12:37:39 PM PDT 24
Peak memory	200600 kb
Host	smart-c598f4d6-2a41-494e-97d9-daebec57fe8f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218566140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti meout.4218566140
Directory	/workspace/3.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.2583750757
Short name	T1
Test name
Test status
Simulation time	46089591287 ps
CPU time	289.43 seconds
Started	Mar 26 12:38:20 PM PDT 24
Finished	Mar 26 12:43:09 PM PDT 24
Peak memory	209176 kb
Host	smart-05a9ffdf-6504-4473-9e3f-8da41248efca
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2583750757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.2583750757
Directory	/workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.3806649895
Short name	T60
Test name
Test status
Simulation time	114122193 ps
CPU time	1.85 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:19 PM PDT 24
Peak memory	201404 kb
Host	smart-46094d9d-7337-46cd-ac04-5958fe7c0cb1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806649895 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 4.clkmgr_shadow_reg_errors.3806649895
Directory	/workspace/4.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/5.clkmgr_regwen.553657728
Short name	T4
Test name
Test status
Simulation time	990491699 ps
CPU time	3.78 seconds
Started	Mar 26 12:37:39 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200684 kb
Host	smart-774ef565-2584-4ebd-b1ed-162cde03dc69
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553657728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.553657728
Directory	/workspace/5.clkmgr_regwen/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_status.2655964677
Short name	T44
Test name
Test status
Simulation time	39727447 ps
CPU time	0.79 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:38:00 PM PDT 24
Peak memory	200496 kb
Host	smart-d7c6182b-a031-4f3d-ab3d-ebf264eebbd1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655964677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.2655964677
Directory	/workspace/13.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/0.clkmgr_sec_cm.2815184785
Short name	T47
Test name
Test status
Simulation time	206912461 ps
CPU time	1.94 seconds
Started	Mar 26 12:37:19 PM PDT 24
Finished	Mar 26 12:37:21 PM PDT 24
Peak memory	219964 kb
Host	smart-bd1eb797-7217-4130-b9be-1bbe6763b809
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815184785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg r_sec_cm.2815184785
Directory	/workspace/0.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/31.clkmgr_idle_intersig_mubi.1586607136
Short name	T110
Test name
Test status
Simulation time	80025919 ps
CPU time	1.08 seconds
Started	Mar 26 12:38:36 PM PDT 24
Finished	Mar 26 12:38:37 PM PDT 24
Peak memory	200628 kb
Host	smart-6181d662-a06b-40c0-816d-6dcb1ed62171
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586607136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.1586607136
Directory	/workspace/31.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.961511156
Short name	T28
Test name
Test status
Simulation time	221650342 ps
CPU time	1.45 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:26 PM PDT 24
Peak memory	200664 kb
Host	smart-68161f85-e8c8-4ba6-a2e0-d23e951cd32d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961511156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.961511156
Directory	/workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_alert_test.2064841831
Short name	T239
Test name
Test status
Simulation time	14836984 ps
CPU time	0.75 seconds
Started	Mar 26 12:37:55 PM PDT 24
Finished	Mar 26 12:37:55 PM PDT 24
Peak memory	200624 kb
Host	smart-a0f39f2e-c424-4ecf-b1bc-1d7e39fd8a27
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064841831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk mgr_alert_test.2064841831
Directory	/workspace/14.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all.3992821119
Short name	T31
Test name
Test status
Simulation time	2570641806 ps
CPU time	19.5 seconds
Started	Mar 26 12:37:43 PM PDT 24
Finished	Mar 26 12:38:03 PM PDT 24
Peak memory	200824 kb
Host	smart-aedeba38-9b65-49f0-bf58-4c6afd58724c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992821119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.3992821119
Directory	/workspace/9.clkmgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.988166282
Short name	T107
Test name
Test status
Simulation time	194182983 ps
CPU time	2.83 seconds
Started	Mar 26 01:11:59 PM PDT 24
Finished	Mar 26 01:12:02 PM PDT 24
Peak memory	201112 kb
Host	smart-74b9ec44-63c1-4177-8aa2-a7378da6ffb5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988166282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 17.clkmgr_tl_intg_err.988166282
Directory	/workspace/17.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1911961124
Short name	T63
Test name
Test status
Simulation time	76206412 ps
CPU time	1.25 seconds
Started	Mar 26 01:11:45 PM PDT 24
Finished	Mar 26 01:11:47 PM PDT 24
Peak memory	201172 kb
Host	smart-3edcab97-e5de-494c-84a6-c579fcab76f7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911961124 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.clkmgr_shadow_reg_errors.1911961124
Directory	/workspace/13.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.3828972319
Short name	T16
Test name
Test status
Simulation time	54217884579 ps
CPU time	363.99 seconds
Started	Mar 26 12:37:55 PM PDT 24
Finished	Mar 26 12:43:59 PM PDT 24
Peak memory	217312 kb
Host	smart-55502f77-4010-40ff-8873-7a35433e4836
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3828972319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.3828972319
Directory	/workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all.60779025
Short name	T2
Test name
Test status
Simulation time	4777262975 ps
CPU time	18.48 seconds
Started	Mar 26 12:38:21 PM PDT 24
Finished	Mar 26 12:38:40 PM PDT 24
Peak memory	200872 kb
Host	smart-d6f3c9f1-121d-4043-a11d-652de35d9b9f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60779025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_ TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.clkmgr_stress_all.60779025
Directory	/workspace/21.clkmgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3522147174
Short name	T61
Test name
Test status
Simulation time	179372619 ps
CPU time	3.25 seconds
Started	Mar 26 01:11:59 PM PDT 24
Finished	Mar 26 01:12:03 PM PDT 24
Peak memory	201724 kb
Host	smart-1e8ae60e-e7ac-4178-b09d-ff5b205abb56
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522147174 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.3522147174
Directory	/workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/25.clkmgr_regwen.1628098119
Short name	T9
Test name
Test status
Simulation time	1348648449 ps
CPU time	7.32 seconds
Started	Mar 26 12:38:25 PM PDT 24
Finished	Mar 26 12:38:33 PM PDT 24
Peak memory	200660 kb
Host	smart-37114fa3-0485-4456-ab5e-d660c2b3df85
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628098119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.1628098119
Directory	/workspace/25.clkmgr_regwen/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.2732285753
Short name	T41
Test name
Test status
Simulation time	48655930067 ps
CPU time	688.73 seconds
Started	Mar 26 12:39:14 PM PDT 24
Finished	Mar 26 12:50:43 PM PDT 24
Peak memory	217368 kb
Host	smart-75b71d2a-8374-4cf0-98bf-cfb02fc5daed
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2732285753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.2732285753
Directory	/workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3677204244
Short name	T119
Test name
Test status
Simulation time	107762436 ps
CPU time	1.93 seconds
Started	Mar 26 01:11:46 PM PDT 24
Finished	Mar 26 01:11:49 PM PDT 24
Peak memory	201384 kb
Host	smart-a5ca71df-951f-44b4-a8b6-8ec1aa30f61f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677204244 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.clkmgr_shadow_reg_errors.3677204244
Directory	/workspace/17.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1372960365
Short name	T106
Test name
Test status
Simulation time	98807678 ps
CPU time	2.44 seconds
Started	Mar 26 01:11:29 PM PDT 24
Finished	Mar 26 01:11:31 PM PDT 24
Peak memory	201032 kb
Host	smart-8213c8d8-8d4e-4666-aaf9-caf8c3c3ea8b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372960365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 7.clkmgr_tl_intg_err.1372960365
Directory	/workspace/7.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3163199253
Short name	T130
Test name
Test status
Simulation time	974516296 ps
CPU time	3.88 seconds
Started	Mar 26 01:12:04 PM PDT 24
Finished	Mar 26 01:12:08 PM PDT 24
Peak memory	217508 kb
Host	smart-bfd5370d-e077-46d5-93d7-a3e39b9b0cb6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163199253 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 18.clkmgr_shadow_reg_errors.3163199253
Directory	/workspace/18.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency.3347170438
Short name	T15
Test name
Test status
Simulation time	2122941339 ps
CPU time	16.15 seconds
Started	Mar 26 12:38:15 PM PDT 24
Finished	Mar 26 12:38:31 PM PDT 24
Peak memory	200692 kb
Host	smart-10d1cee7-c76b-4eb7-98d2-5eb2f28b0591
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347170438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.3347170438
Directory	/workspace/16.clkmgr_frequency/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.65742098
Short name	T124
Test name
Test status
Simulation time	191031147 ps
CPU time	2.25 seconds
Started	Mar 26 01:12:04 PM PDT 24
Finished	Mar 26 01:12:06 PM PDT 24
Peak memory	209708 kb
Host	smart-1243ed48-c014-48b6-9630-3bfc7382675b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65742098 -assert nopostproc +UVM_TESTNAME= clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.65742098
Directory	/workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3063426010
Short name	T118
Test name
Test status
Simulation time	229903565 ps
CPU time	2.29 seconds
Started	Mar 26 01:11:16 PM PDT 24
Finished	Mar 26 01:11:19 PM PDT 24
Peak memory	209692 kb
Host	smart-a811594e-3508-42a4-bd38-e60aace3501f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063426010 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.3063426010
Directory	/workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1743366819
Short name	T95
Test name
Test status
Simulation time	70385844 ps
CPU time	1.78 seconds
Started	Mar 26 01:11:29 PM PDT 24
Finished	Mar 26 01:11:31 PM PDT 24
Peak memory	201024 kb
Host	smart-a4e8da12-c40b-42bb-96ec-cf0f9b5be365
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743366819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 12.clkmgr_tl_intg_err.1743366819
Directory	/workspace/12.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2942584897
Short name	T102
Test name
Test status
Simulation time	56202258 ps
CPU time	1.61 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:19 PM PDT 24
Peak memory	201140 kb
Host	smart-084623d1-2e3d-428f-add4-4f0f98276a0e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942584897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 3.clkmgr_tl_intg_err.2942584897
Directory	/workspace/3.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3917390625
Short name	T98
Test name
Test status
Simulation time	59443734 ps
CPU time	1.49 seconds
Started	Mar 26 01:11:16 PM PDT 24
Finished	Mar 26 01:11:18 PM PDT 24
Peak memory	201016 kb
Host	smart-400bf88a-7ce6-4a9b-b9fb-ec96203bbfdf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917390625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 4.clkmgr_tl_intg_err.3917390625
Directory	/workspace/4.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2183429959
Short name	T980
Test name
Test status
Simulation time	893011770 ps
CPU time	4.03 seconds
Started	Mar 26 01:11:02 PM PDT 24
Finished	Mar 26 01:11:06 PM PDT 24
Peak memory	201148 kb
Host	smart-69df24da-0d34-429d-adfb-5fbe5b2ca38e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183429959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_aliasing.2183429959
Directory	/workspace/0.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.805434177
Short name	T969
Test name
Test status
Simulation time	144580874 ps
CPU time	3.48 seconds
Started	Mar 26 01:10:52 PM PDT 24
Finished	Mar 26 01:10:56 PM PDT 24
Peak memory	200968 kb
Host	smart-5d77591e-8358-4771-94a6-17ee451d8de3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805434177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.clkmgr_csr_bit_bash.805434177
Directory	/workspace/0.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1068345940
Short name	T994
Test name
Test status
Simulation time	31710449 ps
CPU time	0.82 seconds
Started	Mar 26 01:10:51 PM PDT 24
Finished	Mar 26 01:10:52 PM PDT 24
Peak memory	200800 kb
Host	smart-5a6c6c06-d359-4b86-a30c-663f5b149f6a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068345940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_hw_reset.1068345940
Directory	/workspace/0.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2327735101
Short name	T101
Test name
Test status
Simulation time	208883245 ps
CPU time	1.91 seconds
Started	Mar 26 01:11:02 PM PDT 24
Finished	Mar 26 01:11:04 PM PDT 24
Peak memory	201052 kb
Host	smart-b3473b64-840c-494d-bf58-c20994bf3187
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327735101 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.2327735101
Directory	/workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1423522014
Short name	T100
Test name
Test status
Simulation time	20466756 ps
CPU time	0.85 seconds
Started	Mar 26 01:10:55 PM PDT 24
Finished	Mar 26 01:10:56 PM PDT 24
Peak memory	200804 kb
Host	smart-d10fc765-ccb0-4580-80a8-027b6ea20b60
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423522014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. clkmgr_csr_rw.1423522014
Directory	/workspace/0.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3776046366
Short name	T872
Test name
Test status
Simulation time	21100594 ps
CPU time	0.67 seconds
Started	Mar 26 01:10:53 PM PDT 24
Finished	Mar 26 01:10:53 PM PDT 24
Peak memory	199260 kb
Host	smart-c7881e65-e0f9-4749-8edc-996bc0c33081
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776046366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk mgr_intr_test.3776046366
Directory	/workspace/0.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3928464404
Short name	T972
Test name
Test status
Simulation time	38086425 ps
CPU time	1.39 seconds
Started	Mar 26 01:11:02 PM PDT 24
Finished	Mar 26 01:11:03 PM PDT 24
Peak memory	201024 kb
Host	smart-52a1e72c-7109-43d3-b73a-3c8f9ecd4394
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928464404 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.clkmgr_same_csr_outstanding.3928464404
Directory	/workspace/0.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.2941296256
Short name	T136
Test name
Test status
Simulation time	580442915 ps
CPU time	2.83 seconds
Started	Mar 26 01:10:53 PM PDT 24
Finished	Mar 26 01:10:56 PM PDT 24
Peak memory	201488 kb
Host	smart-162d220b-f0c0-4393-939d-4186996a894e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941296256 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.clkmgr_shadow_reg_errors.2941296256
Directory	/workspace/0.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3090425476
Short name	T125
Test name
Test status
Simulation time	173722992 ps
CPU time	3.32 seconds
Started	Mar 26 01:10:52 PM PDT 24
Finished	Mar 26 01:10:56 PM PDT 24
Peak memory	209712 kb
Host	smart-7ec23722-0d68-477e-ba91-4a8fea538b35
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090425476 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.3090425476
Directory	/workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2679255554
Short name	T916
Test name
Test status
Simulation time	37406262 ps
CPU time	2.17 seconds
Started	Mar 26 01:10:53 PM PDT 24
Finished	Mar 26 01:10:55 PM PDT 24
Peak memory	200968 kb
Host	smart-7cc95ba1-c41a-4c92-a782-7ca4307e5a88
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679255554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk mgr_tl_errors.2679255554
Directory	/workspace/0.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1490760782
Short name	T900
Test name
Test status
Simulation time	347611720 ps
CPU time	3.27 seconds
Started	Mar 26 01:10:51 PM PDT 24
Finished	Mar 26 01:10:55 PM PDT 24
Peak memory	201012 kb
Host	smart-79d69033-1796-4601-9690-ca9c25c1db42
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490760782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 0.clkmgr_tl_intg_err.1490760782
Directory	/workspace/0.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.608692641
Short name	T904
Test name
Test status
Simulation time	21321588 ps
CPU time	1.07 seconds
Started	Mar 26 01:11:00 PM PDT 24
Finished	Mar 26 01:11:01 PM PDT 24
Peak memory	200980 kb
Host	smart-6413ed25-ea47-4049-9094-d00be334b53d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608692641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 1.clkmgr_csr_aliasing.608692641
Directory	/workspace/1.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3590148315
Short name	T995
Test name
Test status
Simulation time	514351334 ps
CPU time	5.53 seconds
Started	Mar 26 01:11:01 PM PDT 24
Finished	Mar 26 01:11:07 PM PDT 24
Peak memory	200992 kb
Host	smart-dec692c5-eb27-4f69-b81a-634a328210c5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590148315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_bit_bash.3590148315
Directory	/workspace/1.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2631078619
Short name	T1001
Test name
Test status
Simulation time	23581097 ps
CPU time	0.89 seconds
Started	Mar 26 01:11:01 PM PDT 24
Finished	Mar 26 01:11:01 PM PDT 24
Peak memory	200724 kb
Host	smart-0c0a05b2-0228-4731-b593-3024859bc785
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631078619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_hw_reset.2631078619
Directory	/workspace/1.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.137338021
Short name	T996
Test name
Test status
Simulation time	36533985 ps
CPU time	1.22 seconds
Started	Mar 26 01:11:02 PM PDT 24
Finished	Mar 26 01:11:03 PM PDT 24
Peak memory	200816 kb
Host	smart-cce99991-9f1a-4619-9841-e2dfa896ac95
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137338021 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.137338021
Directory	/workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.3716010534
Short name	T963
Test name
Test status
Simulation time	73193495 ps
CPU time	0.93 seconds
Started	Mar 26 01:11:00 PM PDT 24
Finished	Mar 26 01:11:01 PM PDT 24
Peak memory	200844 kb
Host	smart-f9eddebd-216d-4d60-b1c1-2cd281007139
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716010534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. clkmgr_csr_rw.3716010534
Directory	/workspace/1.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_intr_test.22949930
Short name	T978
Test name
Test status
Simulation time	21033808 ps
CPU time	0.65 seconds
Started	Mar 26 01:10:58 PM PDT 24
Finished	Mar 26 01:11:00 PM PDT 24
Peak memory	199340 kb
Host	smart-03b0904e-ed2d-4e7e-9626-2bd62a709238
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22949930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ =clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmg r_intr_test.22949930
Directory	/workspace/1.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.4152747029
Short name	T951
Test name
Test status
Simulation time	95932132 ps
CPU time	1.12 seconds
Started	Mar 26 01:11:01 PM PDT 24
Finished	Mar 26 01:11:02 PM PDT 24
Peak memory	200756 kb
Host	smart-1110a5e4-95cc-4e8f-ae03-0f61c1a00141
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152747029 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.clkmgr_same_csr_outstanding.4152747029
Directory	/workspace/1.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1361660708
Short name	T990
Test name
Test status
Simulation time	61853199 ps
CPU time	1.41 seconds
Started	Mar 26 01:11:03 PM PDT 24
Finished	Mar 26 01:11:04 PM PDT 24
Peak memory	201212 kb
Host	smart-38e7a9a3-d401-4f33-9986-cd079044d50d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361660708 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 1.clkmgr_shadow_reg_errors.1361660708
Directory	/workspace/1.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.16951380
Short name	T64
Test name
Test status
Simulation time	52545165 ps
CPU time	1.58 seconds
Started	Mar 26 01:11:00 PM PDT 24
Finished	Mar 26 01:11:02 PM PDT 24
Peak memory	217696 kb
Host	smart-0d979468-38d6-4dbd-80d8-1f5ce7d106f0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16951380 -assert nopostproc +UVM_TESTNAME= clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.16951380
Directory	/workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.625044119
Short name	T871
Test name
Test status
Simulation time	207660865 ps
CPU time	2.7 seconds
Started	Mar 26 01:11:02 PM PDT 24
Finished	Mar 26 01:11:05 PM PDT 24
Peak memory	201216 kb
Host	smart-d9f145dc-6a77-48af-8e68-2c7dc58720d6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625044119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkm gr_tl_errors.625044119
Directory	/workspace/1.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.2545488827
Short name	T169
Test name
Test status
Simulation time	69605935 ps
CPU time	1.7 seconds
Started	Mar 26 01:11:00 PM PDT 24
Finished	Mar 26 01:11:02 PM PDT 24
Peak memory	201016 kb
Host	smart-119ff646-b44f-44b8-b7c5-d55fd53adc42
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545488827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 1.clkmgr_tl_intg_err.2545488827
Directory	/workspace/1.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2501469266
Short name	T919
Test name
Test status
Simulation time	34291116 ps
CPU time	1.16 seconds
Started	Mar 26 01:11:30 PM PDT 24
Finished	Mar 26 01:11:31 PM PDT 24
Peak memory	200936 kb
Host	smart-bb9a61b0-080e-45de-b902-0176ea1d447c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501469266 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.2501469266
Directory	/workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.1562749515
Short name	T944
Test name
Test status
Simulation time	18803653 ps
CPU time	0.85 seconds
Started	Mar 26 01:11:29 PM PDT 24
Finished	Mar 26 01:11:30 PM PDT 24
Peak memory	200896 kb
Host	smart-7fd81923-4425-4c1b-a361-aa1e2f7c6993
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562749515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .clkmgr_csr_rw.1562749515
Directory	/workspace/10.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_intr_test.244504592
Short name	T890
Test name
Test status
Simulation time	20734860 ps
CPU time	0.69 seconds
Started	Mar 26 01:11:30 PM PDT 24
Finished	Mar 26 01:11:31 PM PDT 24
Peak memory	199304 kb
Host	smart-0f6e2347-a877-41be-8af0-fbef2ecaba9e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244504592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clk mgr_intr_test.244504592
Directory	/workspace/10.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.1031351684
Short name	T974
Test name
Test status
Simulation time	58502825 ps
CPU time	1.42 seconds
Started	Mar 26 01:11:31 PM PDT 24
Finished	Mar 26 01:11:33 PM PDT 24
Peak memory	201092 kb
Host	smart-7ccec1b5-22df-46d9-aedf-44d355cd2557
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031351684 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.clkmgr_same_csr_outstanding.1031351684
Directory	/workspace/10.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1147757430
Short name	T140
Test name
Test status
Simulation time	221543646 ps
CPU time	2.56 seconds
Started	Mar 26 01:11:30 PM PDT 24
Finished	Mar 26 01:11:33 PM PDT 24
Peak memory	201504 kb
Host	smart-99d39fa7-d431-4d85-940f-26634dd26fec
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147757430 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 10.clkmgr_shadow_reg_errors.1147757430
Directory	/workspace/10.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3072156431
Short name	T131
Test name
Test status
Simulation time	137155137 ps
CPU time	1.78 seconds
Started	Mar 26 01:11:35 PM PDT 24
Finished	Mar 26 01:11:37 PM PDT 24
Peak memory	209648 kb
Host	smart-16d6d436-cc47-4c0e-b988-a50678cff8b7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072156431 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.3072156431
Directory	/workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2029346378
Short name	T970
Test name
Test status
Simulation time	175348515 ps
CPU time	2.09 seconds
Started	Mar 26 01:11:27 PM PDT 24
Finished	Mar 26 01:11:30 PM PDT 24
Peak memory	200992 kb
Host	smart-7e7e3e2f-6cb4-4903-8847-8e7a8cf4eaef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029346378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl kmgr_tl_errors.2029346378
Directory	/workspace/10.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1125812016
Short name	T96
Test name
Test status
Simulation time	113530209 ps
CPU time	1.82 seconds
Started	Mar 26 01:11:32 PM PDT 24
Finished	Mar 26 01:11:34 PM PDT 24
Peak memory	201008 kb
Host	smart-f3945129-2584-4739-9dae-f3b6149bbe6f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125812016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 10.clkmgr_tl_intg_err.1125812016
Directory	/workspace/10.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3082670739
Short name	T926
Test name
Test status
Simulation time	198428079 ps
CPU time	2.36 seconds
Started	Mar 26 01:11:28 PM PDT 24
Finished	Mar 26 01:11:31 PM PDT 24
Peak memory	201172 kb
Host	smart-e743cd5b-95ba-45c6-95fd-f088d6bf427c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082670739 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.3082670739
Directory	/workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3530854212
Short name	T908
Test name
Test status
Simulation time	44464160 ps
CPU time	0.85 seconds
Started	Mar 26 01:11:32 PM PDT 24
Finished	Mar 26 01:11:33 PM PDT 24
Peak memory	200812 kb
Host	smart-e372592e-2729-4736-84c3-24279f83512b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530854212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .clkmgr_csr_rw.3530854212
Directory	/workspace/11.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3993785763
Short name	T899
Test name
Test status
Simulation time	11819793 ps
CPU time	0.66 seconds
Started	Mar 26 01:11:31 PM PDT 24
Finished	Mar 26 01:11:32 PM PDT 24
Peak memory	199264 kb
Host	smart-0734abce-ecc6-4504-b4dd-8037de0a067d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993785763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl kmgr_intr_test.3993785763
Directory	/workspace/11.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2430887547
Short name	T922
Test name
Test status
Simulation time	94937906 ps
CPU time	1.16 seconds
Started	Mar 26 01:11:31 PM PDT 24
Finished	Mar 26 01:11:33 PM PDT 24
Peak memory	200812 kb
Host	smart-f2603d36-e0ca-4e66-ad85-34c50e3f47d9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430887547 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.clkmgr_same_csr_outstanding.2430887547
Directory	/workspace/11.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.4098005749
Short name	T126
Test name
Test status
Simulation time	183689728 ps
CPU time	1.41 seconds
Started	Mar 26 01:11:30 PM PDT 24
Finished	Mar 26 01:11:32 PM PDT 24
Peak memory	201316 kb
Host	smart-66b33996-4892-4c18-8f75-92da0172a168
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098005749 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 11.clkmgr_shadow_reg_errors.4098005749
Directory	/workspace/11.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.1597469022
Short name	T933
Test name
Test status
Simulation time	64863529 ps
CPU time	1.62 seconds
Started	Mar 26 01:11:28 PM PDT 24
Finished	Mar 26 01:11:30 PM PDT 24
Peak memory	209600 kb
Host	smart-8d7f2ea0-879b-4075-a0c6-edd7fd0ff3c1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597469022 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.1597469022
Directory	/workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1514501906
Short name	T875
Test name
Test status
Simulation time	54247359 ps
CPU time	1.59 seconds
Started	Mar 26 01:11:28 PM PDT 24
Finished	Mar 26 01:11:30 PM PDT 24
Peak memory	200992 kb
Host	smart-88b9fe9a-03b3-49da-b345-0bdfb676b4c9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514501906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl kmgr_tl_errors.1514501906
Directory	/workspace/11.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.334382383
Short name	T105
Test name
Test status
Simulation time	111606523 ps
CPU time	1.84 seconds
Started	Mar 26 01:11:27 PM PDT 24
Finished	Mar 26 01:11:30 PM PDT 24
Peak memory	201012 kb
Host	smart-29bfc634-69f7-4617-8754-ef96f1e43f57
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334382383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 11.clkmgr_tl_intg_err.334382383
Directory	/workspace/11.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.759907230
Short name	T993
Test name
Test status
Simulation time	24707368 ps
CPU time	1.04 seconds
Started	Mar 26 01:11:44 PM PDT 24
Finished	Mar 26 01:11:46 PM PDT 24
Peak memory	200900 kb
Host	smart-ec303cc6-afe9-4f8d-8e20-7695c350e0f7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759907230 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.759907230
Directory	/workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2649093527
Short name	T882
Test name
Test status
Simulation time	33382990 ps
CPU time	0.88 seconds
Started	Mar 26 01:11:45 PM PDT 24
Finished	Mar 26 01:11:47 PM PDT 24
Peak memory	200848 kb
Host	smart-3cd939d8-2f5e-4b89-9da5-9f4841b92a1e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649093527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .clkmgr_csr_rw.2649093527
Directory	/workspace/12.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1828312159
Short name	T929
Test name
Test status
Simulation time	16256720 ps
CPU time	0.68 seconds
Started	Mar 26 01:11:35 PM PDT 24
Finished	Mar 26 01:11:36 PM PDT 24
Peak memory	199364 kb
Host	smart-1f240de6-0ea0-49f7-81f0-71a17cd30923
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828312159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_intr_test.1828312159
Directory	/workspace/12.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1665069376
Short name	T985
Test name
Test status
Simulation time	42452882 ps
CPU time	0.99 seconds
Started	Mar 26 01:11:45 PM PDT 24
Finished	Mar 26 01:11:48 PM PDT 24
Peak memory	200836 kb
Host	smart-5feff984-a48c-4f67-ae43-8d5db0ae2fb4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665069376 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 12.clkmgr_same_csr_outstanding.1665069376
Directory	/workspace/12.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.884580424
Short name	T129
Test name
Test status
Simulation time	176737797 ps
CPU time	2.01 seconds
Started	Mar 26 01:11:29 PM PDT 24
Finished	Mar 26 01:11:31 PM PDT 24
Peak memory	201396 kb
Host	smart-d394f9ad-1931-455a-b164-64fef9d97640
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884580424 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 12.clkmgr_shadow_reg_errors.884580424
Directory	/workspace/12.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1402336708
Short name	T132
Test name
Test status
Simulation time	603652050 ps
CPU time	3.08 seconds
Started	Mar 26 01:11:30 PM PDT 24
Finished	Mar 26 01:11:33 PM PDT 24
Peak memory	210612 kb
Host	smart-496cd882-db46-4975-875b-0f84b2014317
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402336708 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.1402336708
Directory	/workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3140993230
Short name	T907
Test name
Test status
Simulation time	54535057 ps
CPU time	1.67 seconds
Started	Mar 26 01:11:35 PM PDT 24
Finished	Mar 26 01:11:37 PM PDT 24
Peak memory	201104 kb
Host	smart-c3bef361-96ce-4480-96fd-2a51322ecd8d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140993230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_tl_errors.3140993230
Directory	/workspace/12.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.3223736723
Short name	T971
Test name
Test status
Simulation time	42531349 ps
CPU time	1.49 seconds
Started	Mar 26 01:11:46 PM PDT 24
Finished	Mar 26 01:11:48 PM PDT 24
Peak memory	200920 kb
Host	smart-213cb9e4-f98d-4fe2-8775-4b17d40ada83
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223736723 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.3223736723
Directory	/workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.3968611474
Short name	T982
Test name
Test status
Simulation time	15443361 ps
CPU time	0.79 seconds
Started	Mar 26 01:11:45 PM PDT 24
Finished	Mar 26 01:11:46 PM PDT 24
Peak memory	200832 kb
Host	smart-cbbbbef6-9306-42a6-9063-62b0340b217b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968611474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .clkmgr_csr_rw.3968611474
Directory	/workspace/13.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_intr_test.4142931747
Short name	T874
Test name
Test status
Simulation time	27793781 ps
CPU time	0.75 seconds
Started	Mar 26 01:11:45 PM PDT 24
Finished	Mar 26 01:11:46 PM PDT 24
Peak memory	199256 kb
Host	smart-dffa38f8-3a8e-4e35-96f4-8d61ca9994f7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142931747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl kmgr_intr_test.4142931747
Directory	/workspace/13.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.4268589458
Short name	T905
Test name
Test status
Simulation time	36397423 ps
CPU time	1.1 seconds
Started	Mar 26 01:11:45 PM PDT 24
Finished	Mar 26 01:11:47 PM PDT 24
Peak memory	201068 kb
Host	smart-3dda3aa4-06d3-47c4-ad2c-0e47987a68a6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268589458 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.clkmgr_same_csr_outstanding.4268589458
Directory	/workspace/13.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2741769068
Short name	T966
Test name
Test status
Simulation time	170985917 ps
CPU time	2.15 seconds
Started	Mar 26 01:11:45 PM PDT 24
Finished	Mar 26 01:11:48 PM PDT 24
Peak memory	217564 kb
Host	smart-1b29bd36-61d4-40a2-b821-44deffeb20be
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741769068 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.2741769068
Directory	/workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.3540892871
Short name	T999
Test name
Test status
Simulation time	79062971 ps
CPU time	1.48 seconds
Started	Mar 26 01:11:45 PM PDT 24
Finished	Mar 26 01:11:47 PM PDT 24
Peak memory	201104 kb
Host	smart-8e212732-b6cc-4de0-933d-9c095f137543
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540892871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl kmgr_tl_errors.3540892871
Directory	/workspace/13.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1001081850
Short name	T94
Test name
Test status
Simulation time	61885796 ps
CPU time	1.66 seconds
Started	Mar 26 01:11:46 PM PDT 24
Finished	Mar 26 01:11:48 PM PDT 24
Peak memory	201004 kb
Host	smart-c96b0fee-d0e8-40b0-a0b9-3ef95b467607
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001081850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 13.clkmgr_tl_intg_err.1001081850
Directory	/workspace/13.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.776789357
Short name	T927
Test name
Test status
Simulation time	44413674 ps
CPU time	1.4 seconds
Started	Mar 26 01:11:46 PM PDT 24
Finished	Mar 26 01:11:48 PM PDT 24
Peak memory	200888 kb
Host	smart-84793b19-3993-4bd5-8fe0-e1f66813f71e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776789357 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.776789357
Directory	/workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.3545036805
Short name	T960
Test name
Test status
Simulation time	43494140 ps
CPU time	0.81 seconds
Started	Mar 26 01:11:46 PM PDT 24
Finished	Mar 26 01:11:48 PM PDT 24
Peak memory	200844 kb
Host	smart-f3804d97-01e9-465d-95dd-9870dc9ea960
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545036805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .clkmgr_csr_rw.3545036805
Directory	/workspace/14.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_intr_test.2067055411
Short name	T936
Test name
Test status
Simulation time	15022247 ps
CPU time	0.68 seconds
Started	Mar 26 01:11:45 PM PDT 24
Finished	Mar 26 01:11:47 PM PDT 24
Peak memory	199216 kb
Host	smart-25d42627-67c7-4183-8128-5cd4657c94f5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067055411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl kmgr_intr_test.2067055411
Directory	/workspace/14.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1185337663
Short name	T998
Test name
Test status
Simulation time	52626936 ps
CPU time	1.39 seconds
Started	Mar 26 01:11:44 PM PDT 24
Finished	Mar 26 01:11:47 PM PDT 24
Peak memory	201084 kb
Host	smart-a5468c98-a51a-4e6b-9fd6-072351a37e42
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185337663 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.clkmgr_same_csr_outstanding.1185337663
Directory	/workspace/14.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2023971674
Short name	T122
Test name
Test status
Simulation time	119664298 ps
CPU time	1.34 seconds
Started	Mar 26 01:11:50 PM PDT 24
Finished	Mar 26 01:11:52 PM PDT 24
Peak memory	201340 kb
Host	smart-14ba7750-2720-47d4-990f-320b564c8eaa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023971674 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 14.clkmgr_shadow_reg_errors.2023971674
Directory	/workspace/14.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3153448948
Short name	T991
Test name
Test status
Simulation time	135522865 ps
CPU time	2.01 seconds
Started	Mar 26 01:11:49 PM PDT 24
Finished	Mar 26 01:11:51 PM PDT 24
Peak memory	201680 kb
Host	smart-88b9ee1d-ad4d-4999-b5e0-3be5e788e69e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153448948 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.3153448948
Directory	/workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.1182783051
Short name	T952
Test name
Test status
Simulation time	62062713 ps
CPU time	1.71 seconds
Started	Mar 26 01:11:44 PM PDT 24
Finished	Mar 26 01:11:47 PM PDT 24
Peak memory	201108 kb
Host	smart-76633bf6-f80b-42d3-b283-b761d858c072
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182783051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl kmgr_tl_errors.1182783051
Directory	/workspace/14.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3721554533
Short name	T940
Test name
Test status
Simulation time	126159047 ps
CPU time	1.63 seconds
Started	Mar 26 01:11:45 PM PDT 24
Finished	Mar 26 01:11:48 PM PDT 24
Peak memory	201044 kb
Host	smart-265873a0-0183-47a1-94fb-4ea0a7fde0bc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721554533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 14.clkmgr_tl_intg_err.3721554533
Directory	/workspace/14.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2962843878
Short name	T913
Test name
Test status
Simulation time	69530572 ps
CPU time	1.11 seconds
Started	Mar 26 01:11:48 PM PDT 24
Finished	Mar 26 01:11:49 PM PDT 24
Peak memory	200816 kb
Host	smart-f0e8b66d-c71f-493c-a2dc-ef69be5863fc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962843878 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.2962843878
Directory	/workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1600025132
Short name	T957
Test name
Test status
Simulation time	27605403 ps
CPU time	0.85 seconds
Started	Mar 26 01:11:47 PM PDT 24
Finished	Mar 26 01:11:48 PM PDT 24
Peak memory	200768 kb
Host	smart-cc8ed738-2f8b-4683-ad35-093ffb7a3bc0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600025132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .clkmgr_csr_rw.1600025132
Directory	/workspace/15.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_intr_test.3885528991
Short name	T862
Test name
Test status
Simulation time	23546513 ps
CPU time	0.73 seconds
Started	Mar 26 01:11:49 PM PDT 24
Finished	Mar 26 01:11:50 PM PDT 24
Peak memory	199368 kb
Host	smart-fd2561ec-44b1-4800-8445-e88ab7ce0440
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885528991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl kmgr_intr_test.3885528991
Directory	/workspace/15.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1151950766
Short name	T892
Test name
Test status
Simulation time	21074741 ps
CPU time	0.94 seconds
Started	Mar 26 01:11:46 PM PDT 24
Finished	Mar 26 01:11:48 PM PDT 24
Peak memory	200932 kb
Host	smart-95fa7bc2-f42c-4252-8fc4-0407babad1ad
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151950766 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.clkmgr_same_csr_outstanding.1151950766
Directory	/workspace/15.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2104462070
Short name	T977
Test name
Test status
Simulation time	111473229 ps
CPU time	1.35 seconds
Started	Mar 26 01:11:43 PM PDT 24
Finished	Mar 26 01:11:46 PM PDT 24
Peak memory	201236 kb
Host	smart-b3899e4b-a3cb-4205-9193-9ba05ab5d934
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104462070 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.clkmgr_shadow_reg_errors.2104462070
Directory	/workspace/15.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.2767531263
Short name	T67
Test name
Test status
Simulation time	455014948 ps
CPU time	3.49 seconds
Started	Mar 26 01:11:44 PM PDT 24
Finished	Mar 26 01:11:49 PM PDT 24
Peak memory	217680 kb
Host	smart-113c6a14-ea12-4706-9e1b-51281d6dbcab
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767531263 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.2767531263
Directory	/workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.4162870008
Short name	T883
Test name
Test status
Simulation time	234484913 ps
CPU time	2.23 seconds
Started	Mar 26 01:11:46 PM PDT 24
Finished	Mar 26 01:11:49 PM PDT 24
Peak memory	201108 kb
Host	smart-926e873e-70c1-4342-bcc6-4969dc6a982c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162870008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl kmgr_tl_errors.4162870008
Directory	/workspace/15.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2973761075
Short name	T1010
Test name
Test status
Simulation time	528871813 ps
CPU time	2.59 seconds
Started	Mar 26 01:11:44 PM PDT 24
Finished	Mar 26 01:11:48 PM PDT 24
Peak memory	201140 kb
Host	smart-fd0f1bbd-8244-44c7-b183-9522307eb619
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973761075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 15.clkmgr_tl_intg_err.2973761075
Directory	/workspace/15.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3920170837
Short name	T947
Test name
Test status
Simulation time	73376850 ps
CPU time	1.41 seconds
Started	Mar 26 01:11:48 PM PDT 24
Finished	Mar 26 01:11:50 PM PDT 24
Peak memory	200728 kb
Host	smart-06aa6a1c-367a-4176-a5d0-049f6c7e86df
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920170837 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.3920170837
Directory	/workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3399364257
Short name	T945
Test name
Test status
Simulation time	106387123 ps
CPU time	1.12 seconds
Started	Mar 26 01:11:46 PM PDT 24
Finished	Mar 26 01:11:48 PM PDT 24
Peak memory	200900 kb
Host	smart-2d3466d9-6948-4916-a2f9-ba8b8fae78dc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399364257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .clkmgr_csr_rw.3399364257
Directory	/workspace/16.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_intr_test.305789829
Short name	T891
Test name
Test status
Simulation time	14929598 ps
CPU time	0.67 seconds
Started	Mar 26 01:11:43 PM PDT 24
Finished	Mar 26 01:11:45 PM PDT 24
Peak memory	199320 kb
Host	smart-6f2a7fb8-2407-40f2-b5cd-31cc745d10ab
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305789829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clk mgr_intr_test.305789829
Directory	/workspace/16.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1122216892
Short name	T879
Test name
Test status
Simulation time	38315203 ps
CPU time	1.22 seconds
Started	Mar 26 01:11:49 PM PDT 24
Finished	Mar 26 01:11:50 PM PDT 24
Peak memory	200940 kb
Host	smart-1008e15f-292f-44b8-bb82-0818224310f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122216892 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.clkmgr_same_csr_outstanding.1122216892
Directory	/workspace/16.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3803309337
Short name	T120
Test name
Test status
Simulation time	109608144 ps
CPU time	1.34 seconds
Started	Mar 26 01:11:45 PM PDT 24
Finished	Mar 26 01:11:47 PM PDT 24
Peak memory	201168 kb
Host	smart-2e202857-4f44-4e41-80ad-2328a27b671c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803309337 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 16.clkmgr_shadow_reg_errors.3803309337
Directory	/workspace/16.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3710514820
Short name	T66
Test name
Test status
Simulation time	71169338 ps
CPU time	1.77 seconds
Started	Mar 26 01:11:43 PM PDT 24
Finished	Mar 26 01:11:47 PM PDT 24
Peak memory	201588 kb
Host	smart-69ec14e7-ad4d-481b-80c1-4598cd6f706f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710514820 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.3710514820
Directory	/workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.849655878
Short name	T954
Test name
Test status
Simulation time	121614436 ps
CPU time	1.81 seconds
Started	Mar 26 01:11:44 PM PDT 24
Finished	Mar 26 01:11:47 PM PDT 24
Peak memory	200952 kb
Host	smart-40bd7ec4-1ad0-4483-9a84-654060703d6d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849655878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clk mgr_tl_errors.849655878
Directory	/workspace/16.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.288733383
Short name	T898
Test name
Test status
Simulation time	279243415 ps
CPU time	2.09 seconds
Started	Mar 26 01:11:46 PM PDT 24
Finished	Mar 26 01:11:49 PM PDT 24
Peak memory	201016 kb
Host	smart-a4732a98-c394-49e8-a7b9-bd7639d11b19
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288733383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 16.clkmgr_tl_intg_err.288733383
Directory	/workspace/16.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.1014682988
Short name	T925
Test name
Test status
Simulation time	55361971 ps
CPU time	1.11 seconds
Started	Mar 26 01:12:00 PM PDT 24
Finished	Mar 26 01:12:01 PM PDT 24
Peak memory	201068 kb
Host	smart-41118697-34c2-4703-8ea1-bc6849404b3b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014682988 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.1014682988
Directory	/workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.4044633260
Short name	T959
Test name
Test status
Simulation time	88888135 ps
CPU time	0.91 seconds
Started	Mar 26 01:12:01 PM PDT 24
Finished	Mar 26 01:12:02 PM PDT 24
Peak memory	200788 kb
Host	smart-f3089abf-a15b-4b5a-bbb7-b7a48956bf29
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044633260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .clkmgr_csr_rw.4044633260
Directory	/workspace/17.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_intr_test.1658237293
Short name	T997
Test name
Test status
Simulation time	35892495 ps
CPU time	0.7 seconds
Started	Mar 26 01:11:59 PM PDT 24
Finished	Mar 26 01:12:00 PM PDT 24
Peak memory	199332 kb
Host	smart-00eee2a1-0b93-4142-b1de-5c0a4b179683
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658237293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl kmgr_intr_test.1658237293
Directory	/workspace/17.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.433654903
Short name	T928
Test name
Test status
Simulation time	169051969 ps
CPU time	1.61 seconds
Started	Mar 26 01:11:59 PM PDT 24
Finished	Mar 26 01:12:00 PM PDT 24
Peak memory	201088 kb
Host	smart-c318a3a4-7b81-4670-a3d4-7b0970b725f1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433654903 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 17.clkmgr_same_csr_outstanding.433654903
Directory	/workspace/17.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2182967959
Short name	T127
Test name
Test status
Simulation time	393518568 ps
CPU time	3.46 seconds
Started	Mar 26 01:11:46 PM PDT 24
Finished	Mar 26 01:11:50 PM PDT 24
Peak memory	209392 kb
Host	smart-7863243a-05d5-4dcd-b14a-32bc95d84f66
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182967959 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.2182967959
Directory	/workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.146818318
Short name	T1006
Test name
Test status
Simulation time	302216452 ps
CPU time	2.84 seconds
Started	Mar 26 01:12:01 PM PDT 24
Finished	Mar 26 01:12:04 PM PDT 24
Peak memory	201100 kb
Host	smart-f88eebea-21c5-4e19-b097-b8d5e6e5807b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146818318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clk mgr_tl_errors.146818318
Directory	/workspace/17.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.357072232
Short name	T881
Test name
Test status
Simulation time	91419870 ps
CPU time	1.17 seconds
Started	Mar 26 01:12:02 PM PDT 24
Finished	Mar 26 01:12:03 PM PDT 24
Peak memory	200936 kb
Host	smart-262e2269-dbf5-4adb-9783-02579ab60465
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357072232 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.357072232
Directory	/workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.2710845904
Short name	T85
Test name
Test status
Simulation time	57500004 ps
CPU time	0.9 seconds
Started	Mar 26 01:12:00 PM PDT 24
Finished	Mar 26 01:12:01 PM PDT 24
Peak memory	200924 kb
Host	smart-dfc76dd1-015e-4ad9-86ef-78fa8a341f3d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710845904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .clkmgr_csr_rw.2710845904
Directory	/workspace/18.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_intr_test.2930345533
Short name	T864
Test name
Test status
Simulation time	12828542 ps
CPU time	0.67 seconds
Started	Mar 26 01:11:58 PM PDT 24
Finished	Mar 26 01:11:59 PM PDT 24
Peak memory	199256 kb
Host	smart-93880ce4-870d-4ec4-ac9f-cbad75226120
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930345533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl kmgr_intr_test.2930345533
Directory	/workspace/18.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3034219314
Short name	T896
Test name
Test status
Simulation time	41730712 ps
CPU time	1.38 seconds
Started	Mar 26 01:12:05 PM PDT 24
Finished	Mar 26 01:12:06 PM PDT 24
Peak memory	201100 kb
Host	smart-57b510ba-61bb-448d-8f6c-186a3ad64896
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034219314 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 18.clkmgr_same_csr_outstanding.3034219314
Directory	/workspace/18.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.2914606606
Short name	T986
Test name
Test status
Simulation time	379206961 ps
CPU time	3.64 seconds
Started	Mar 26 01:11:57 PM PDT 24
Finished	Mar 26 01:12:01 PM PDT 24
Peak memory	201116 kb
Host	smart-d23eb721-e9d2-4631-bf8f-014f1a0eefc4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914606606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl kmgr_tl_errors.2914606606
Directory	/workspace/18.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3060479677
Short name	T984
Test name
Test status
Simulation time	62250588 ps
CPU time	1.61 seconds
Started	Mar 26 01:12:00 PM PDT 24
Finished	Mar 26 01:12:02 PM PDT 24
Peak memory	201028 kb
Host	smart-281eabc5-b856-4744-ae6e-66514e0fa7ce
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060479677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 18.clkmgr_tl_intg_err.3060479677
Directory	/workspace/18.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3733283247
Short name	T906
Test name
Test status
Simulation time	65944240 ps
CPU time	1.37 seconds
Started	Mar 26 01:12:03 PM PDT 24
Finished	Mar 26 01:12:05 PM PDT 24
Peak memory	200912 kb
Host	smart-4ed6a51d-6203-4b3f-838b-f3ba77ea5fc0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733283247 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3733283247
Directory	/workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.1779339484
Short name	T988
Test name
Test status
Simulation time	42605984 ps
CPU time	0.88 seconds
Started	Mar 26 01:11:59 PM PDT 24
Finished	Mar 26 01:12:00 PM PDT 24
Peak memory	200820 kb
Host	smart-844c5acb-5a0a-46ce-ac55-24bcda2b9725
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779339484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .clkmgr_csr_rw.1779339484
Directory	/workspace/19.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_intr_test.3780290944
Short name	T917
Test name
Test status
Simulation time	12628748 ps
CPU time	0.68 seconds
Started	Mar 26 01:12:01 PM PDT 24
Finished	Mar 26 01:12:01 PM PDT 24
Peak memory	199320 kb
Host	smart-0dee2375-02b6-4ca0-9cd9-a10bbbc72b5d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780290944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl kmgr_intr_test.3780290944
Directory	/workspace/19.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.889180640
Short name	T979
Test name
Test status
Simulation time	27791963 ps
CPU time	0.96 seconds
Started	Mar 26 01:12:00 PM PDT 24
Finished	Mar 26 01:12:01 PM PDT 24
Peak memory	200796 kb
Host	smart-caddc5ae-5094-4a29-8955-710002d13cdf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889180640 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 19.clkmgr_same_csr_outstanding.889180640
Directory	/workspace/19.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3509281021
Short name	T62
Test name
Test status
Simulation time	516937224 ps
CPU time	2.84 seconds
Started	Mar 26 01:12:01 PM PDT 24
Finished	Mar 26 01:12:04 PM PDT 24
Peak memory	217580 kb
Host	smart-59de4ae2-a160-4ef9-99b3-f889604ff205
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509281021 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 19.clkmgr_shadow_reg_errors.3509281021
Directory	/workspace/19.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.2807433551
Short name	T1007
Test name
Test status
Simulation time	51591630 ps
CPU time	1.8 seconds
Started	Mar 26 01:11:58 PM PDT 24
Finished	Mar 26 01:12:00 PM PDT 24
Peak memory	200972 kb
Host	smart-995aefc5-0b2b-4ed6-b9d8-21125917993a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807433551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl kmgr_tl_errors.2807433551
Directory	/workspace/19.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.2306471252
Short name	T172
Test name
Test status
Simulation time	1835858197 ps
CPU time	6.72 seconds
Started	Mar 26 01:11:59 PM PDT 24
Finished	Mar 26 01:12:06 PM PDT 24
Peak memory	201124 kb
Host	smart-a14ec390-fd48-41ef-85a0-7a9be24c35b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306471252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 19.clkmgr_tl_intg_err.2306471252
Directory	/workspace/19.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.94714527
Short name	T961
Test name
Test status
Simulation time	50202503 ps
CPU time	1.56 seconds
Started	Mar 26 01:11:16 PM PDT 24
Finished	Mar 26 01:11:18 PM PDT 24
Peak memory	201120 kb
Host	smart-ea167061-d968-4f3e-a4ff-c0e576f9a486
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94714527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.clkmgr_csr_aliasing.94714527
Directory	/workspace/2.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3320729139
Short name	T869
Test name
Test status
Simulation time	696999995 ps
CPU time	8.43 seconds
Started	Mar 26 01:11:03 PM PDT 24
Finished	Mar 26 01:11:12 PM PDT 24
Peak memory	200992 kb
Host	smart-aba9c0cb-edbe-4067-a18e-a0241c7f8555
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320729139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_bit_bash.3320729139
Directory	/workspace/2.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2461063024
Short name	T965
Test name
Test status
Simulation time	23714422 ps
CPU time	0.84 seconds
Started	Mar 26 01:11:01 PM PDT 24
Finished	Mar 26 01:11:02 PM PDT 24
Peak memory	200828 kb
Host	smart-5002089b-6922-4776-9308-1345a21d809d
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461063024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_hw_reset.2461063024
Directory	/workspace/2.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3580432212
Short name	T870
Test name
Test status
Simulation time	18932562 ps
CPU time	1.02 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:18 PM PDT 24
Peak memory	200936 kb
Host	smart-d6a1f483-aa79-460f-b69e-b241ec579189
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580432212 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.3580432212
Directory	/workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.3099338234
Short name	T955
Test name
Test status
Simulation time	23864779 ps
CPU time	0.87 seconds
Started	Mar 26 01:11:01 PM PDT 24
Finished	Mar 26 01:11:02 PM PDT 24
Peak memory	200916 kb
Host	smart-61d803f3-918e-4486-885f-8c90be6d77b8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099338234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. clkmgr_csr_rw.3099338234
Directory	/workspace/2.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_intr_test.572876238
Short name	T1003
Test name
Test status
Simulation time	37829260 ps
CPU time	0.73 seconds
Started	Mar 26 01:11:02 PM PDT 24
Finished	Mar 26 01:11:03 PM PDT 24
Peak memory	199228 kb
Host	smart-94ffaad5-6a70-48f9-b2d5-dc135a3cdc1d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572876238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm gr_intr_test.572876238
Directory	/workspace/2.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3524401128
Short name	T86
Test name
Test status
Simulation time	190223906 ps
CPU time	1.51 seconds
Started	Mar 26 01:11:16 PM PDT 24
Finished	Mar 26 01:11:18 PM PDT 24
Peak memory	200908 kb
Host	smart-34558fe5-a203-486a-b6da-5d11fa80f486
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524401128 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.clkmgr_same_csr_outstanding.3524401128
Directory	/workspace/2.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.376639538
Short name	T123
Test name
Test status
Simulation time	168892314 ps
CPU time	1.96 seconds
Started	Mar 26 01:11:01 PM PDT 24
Finished	Mar 26 01:11:03 PM PDT 24
Peak memory	201364 kb
Host	smart-14e3ae3e-8d3b-4f47-a165-6324d4e72047
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376639538 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.clkmgr_shadow_reg_errors.376639538
Directory	/workspace/2.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.4019313535
Short name	T138
Test name
Test status
Simulation time	312460674 ps
CPU time	2.84 seconds
Started	Mar 26 01:10:59 PM PDT 24
Finished	Mar 26 01:11:02 PM PDT 24
Peak memory	217856 kb
Host	smart-1d38a07d-68d9-4fc1-98ab-cb19204c55d5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019313535 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.4019313535
Directory	/workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.4166131152
Short name	T941
Test name
Test status
Simulation time	37764174 ps
CPU time	2.13 seconds
Started	Mar 26 01:11:05 PM PDT 24
Finished	Mar 26 01:11:07 PM PDT 24
Peak memory	200992 kb
Host	smart-d8a0c888-0537-4681-b0f2-95977023edef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166131152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk mgr_tl_errors.4166131152
Directory	/workspace/2.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3689264958
Short name	T103
Test name
Test status
Simulation time	117202058 ps
CPU time	1.79 seconds
Started	Mar 26 01:10:59 PM PDT 24
Finished	Mar 26 01:11:01 PM PDT 24
Peak memory	200980 kb
Host	smart-24d9ede9-6c91-4d7e-85be-33ad5b19d016
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689264958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 2.clkmgr_tl_intg_err.3689264958
Directory	/workspace/2.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2818822942
Short name	T868
Test name
Test status
Simulation time	20837539 ps
CPU time	0.71 seconds
Started	Mar 26 01:12:03 PM PDT 24
Finished	Mar 26 01:12:05 PM PDT 24
Peak memory	199112 kb
Host	smart-34d7e09c-4e4d-4d07-a9a9-ebd75f47c9e4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818822942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl kmgr_intr_test.2818822942
Directory	/workspace/20.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.clkmgr_intr_test.4277189856
Short name	T937
Test name
Test status
Simulation time	25983873 ps
CPU time	0.69 seconds
Started	Mar 26 01:12:04 PM PDT 24
Finished	Mar 26 01:12:05 PM PDT 24
Peak memory	199260 kb
Host	smart-c1107528-ee49-4575-8dba-3aca8da6fe11
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277189856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl kmgr_intr_test.4277189856
Directory	/workspace/21.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.clkmgr_intr_test.122655891
Short name	T949
Test name
Test status
Simulation time	13659285 ps
CPU time	0.69 seconds
Started	Mar 26 01:12:01 PM PDT 24
Finished	Mar 26 01:12:02 PM PDT 24
Peak memory	199360 kb
Host	smart-f48e0d96-89d9-46db-bf4b-b54198c1184b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122655891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clk mgr_intr_test.122655891
Directory	/workspace/22.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.clkmgr_intr_test.1405705240
Short name	T878
Test name
Test status
Simulation time	166984471 ps
CPU time	1.04 seconds
Started	Mar 26 01:12:02 PM PDT 24
Finished	Mar 26 01:12:03 PM PDT 24
Peak memory	199212 kb
Host	smart-168c45d0-8b11-4047-8da4-eee7332ce4f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405705240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl kmgr_intr_test.1405705240
Directory	/workspace/23.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2268671764
Short name	T895
Test name
Test status
Simulation time	13663829 ps
CPU time	0.7 seconds
Started	Mar 26 01:12:01 PM PDT 24
Finished	Mar 26 01:12:01 PM PDT 24
Peak memory	199236 kb
Host	smart-947ca418-4906-403f-af38-ef334a0a31ae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268671764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl kmgr_intr_test.2268671764
Directory	/workspace/24.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.clkmgr_intr_test.840312623
Short name	T866
Test name
Test status
Simulation time	22519141 ps
CPU time	0.74 seconds
Started	Mar 26 01:12:03 PM PDT 24
Finished	Mar 26 01:12:05 PM PDT 24
Peak memory	199432 kb
Host	smart-832de4d2-b67f-4021-a93e-0e302bc3333f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840312623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clk mgr_intr_test.840312623
Directory	/workspace/25.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3396130061
Short name	T956
Test name
Test status
Simulation time	17126813 ps
CPU time	0.66 seconds
Started	Mar 26 01:11:59 PM PDT 24
Finished	Mar 26 01:12:00 PM PDT 24
Peak memory	199364 kb
Host	smart-ac608616-4b0e-4514-84c7-e008366e6a06
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396130061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl kmgr_intr_test.3396130061
Directory	/workspace/26.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2940936837
Short name	T932
Test name
Test status
Simulation time	13728330 ps
CPU time	0.69 seconds
Started	Mar 26 01:12:01 PM PDT 24
Finished	Mar 26 01:12:02 PM PDT 24
Peak memory	198908 kb
Host	smart-e3d0abe6-d005-4dc9-9bcb-68d5e59658c0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940936837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl kmgr_intr_test.2940936837
Directory	/workspace/27.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.clkmgr_intr_test.577981850
Short name	T865
Test name
Test status
Simulation time	88308604 ps
CPU time	0.91 seconds
Started	Mar 26 01:11:59 PM PDT 24
Finished	Mar 26 01:12:00 PM PDT 24
Peak memory	199264 kb
Host	smart-5780780a-9594-4dff-8b14-bedb5fea0ca6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577981850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clk mgr_intr_test.577981850
Directory	/workspace/28.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.clkmgr_intr_test.100482859
Short name	T887
Test name
Test status
Simulation time	30153275 ps
CPU time	0.68 seconds
Started	Mar 26 01:12:00 PM PDT 24
Finished	Mar 26 01:12:01 PM PDT 24
Peak memory	199260 kb
Host	smart-c67ace6f-df88-416b-847f-cab36e552f30
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100482859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clk mgr_intr_test.100482859
Directory	/workspace/29.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.2186771968
Short name	T82
Test name
Test status
Simulation time	201141221 ps
CPU time	1.9 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:20 PM PDT 24
Peak memory	201004 kb
Host	smart-c6f5d0b3-a6ad-4501-a060-edcf88c6ec2b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186771968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_aliasing.2186771968
Directory	/workspace/3.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.1029833924
Short name	T912
Test name
Test status
Simulation time	419930387 ps
CPU time	7.82 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:25 PM PDT 24
Peak memory	200996 kb
Host	smart-c6241fc7-d6e3-450d-90ae-dd8e1d4aeb7f
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029833924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_bit_bash.1029833924
Directory	/workspace/3.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2866731786
Short name	T1002
Test name
Test status
Simulation time	17081447 ps
CPU time	0.77 seconds
Started	Mar 26 01:11:18 PM PDT 24
Finished	Mar 26 01:11:18 PM PDT 24
Peak memory	200896 kb
Host	smart-0ee8001f-de47-403c-a0d1-e901db4dfe79
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866731786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_hw_reset.2866731786
Directory	/workspace/3.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1892052251
Short name	T924
Test name
Test status
Simulation time	25357370 ps
CPU time	1.03 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:19 PM PDT 24
Peak memory	200952 kb
Host	smart-519d9457-247e-4456-9149-91c1d9c0ba72
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892052251 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.1892052251
Directory	/workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1262926345
Short name	T938
Test name
Test status
Simulation time	16246659 ps
CPU time	0.77 seconds
Started	Mar 26 01:11:16 PM PDT 24
Finished	Mar 26 01:11:17 PM PDT 24
Peak memory	200944 kb
Host	smart-50f103de-e54a-48bf-bcbf-068f82dd81fe
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262926345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. clkmgr_csr_rw.1262926345
Directory	/workspace/3.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2524835433
Short name	T939
Test name
Test status
Simulation time	15040875 ps
CPU time	0.7 seconds
Started	Mar 26 01:11:15 PM PDT 24
Finished	Mar 26 01:11:17 PM PDT 24
Peak memory	199424 kb
Host	smart-b71c8e76-3201-450e-8525-bec93da038da
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524835433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_intr_test.2524835433
Directory	/workspace/3.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.891339255
Short name	T1004
Test name
Test status
Simulation time	59768401 ps
CPU time	1.19 seconds
Started	Mar 26 01:11:16 PM PDT 24
Finished	Mar 26 01:11:18 PM PDT 24
Peak memory	200944 kb
Host	smart-f447c412-37d0-4bc1-8b48-b203db7afe08
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891339255 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 3.clkmgr_same_csr_outstanding.891339255
Directory	/workspace/3.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.235080757
Short name	T135
Test name
Test status
Simulation time	55646139 ps
CPU time	1.24 seconds
Started	Mar 26 01:11:15 PM PDT 24
Finished	Mar 26 01:11:18 PM PDT 24
Peak memory	201232 kb
Host	smart-5fc7a83c-371d-4df8-89a8-79cfb1692fcb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235080757 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.clkmgr_shadow_reg_errors.235080757
Directory	/workspace/3.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.40974496
Short name	T117
Test name
Test status
Simulation time	408815523 ps
CPU time	2.4 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:19 PM PDT 24
Peak memory	217720 kb
Host	smart-0b25938c-07be-46e1-93a4-ae5e34f49a27
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40974496 -assert nopostproc +UVM_TESTNAME= clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.40974496
Directory	/workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.3416102124
Short name	T914
Test name
Test status
Simulation time	307801987 ps
CPU time	2.68 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:20 PM PDT 24
Peak memory	201096 kb
Host	smart-dba51a4f-e889-450f-85c9-f38f10d51060
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416102124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_tl_errors.3416102124
Directory	/workspace/3.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/30.clkmgr_intr_test.1446002407
Short name	T1005
Test name
Test status
Simulation time	34749386 ps
CPU time	0.74 seconds
Started	Mar 26 01:11:59 PM PDT 24
Finished	Mar 26 01:12:00 PM PDT 24
Peak memory	199288 kb
Host	smart-301f45ec-175a-4dc4-98bd-552ff296937c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446002407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl kmgr_intr_test.1446002407
Directory	/workspace/30.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3570138138
Short name	T885
Test name
Test status
Simulation time	28094581 ps
CPU time	0.69 seconds
Started	Mar 26 01:12:02 PM PDT 24
Finished	Mar 26 01:12:03 PM PDT 24
Peak memory	199328 kb
Host	smart-ce852320-773a-4bdf-90d3-4001e0fbc605
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570138138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl kmgr_intr_test.3570138138
Directory	/workspace/31.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.clkmgr_intr_test.2051259999
Short name	T873
Test name
Test status
Simulation time	19227040 ps
CPU time	0.68 seconds
Started	Mar 26 01:12:04 PM PDT 24
Finished	Mar 26 01:12:06 PM PDT 24
Peak memory	199360 kb
Host	smart-dc6b27ff-c3b8-44f3-9e14-d55fc5dd90b8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051259999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl kmgr_intr_test.2051259999
Directory	/workspace/32.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.clkmgr_intr_test.4199660535
Short name	T867
Test name
Test status
Simulation time	15541285 ps
CPU time	0.69 seconds
Started	Mar 26 01:12:04 PM PDT 24
Finished	Mar 26 01:12:05 PM PDT 24
Peak memory	199356 kb
Host	smart-5f1d9876-f799-406d-bfa1-170fc66b3444
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199660535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl kmgr_intr_test.4199660535
Directory	/workspace/33.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.clkmgr_intr_test.2764200693
Short name	T863
Test name
Test status
Simulation time	13819215 ps
CPU time	0.69 seconds
Started	Mar 26 01:12:01 PM PDT 24
Finished	Mar 26 01:12:01 PM PDT 24
Peak memory	199364 kb
Host	smart-5a75ec6e-2cd6-4b64-9d80-88ab1fdb9c25
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764200693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl kmgr_intr_test.2764200693
Directory	/workspace/34.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.clkmgr_intr_test.623240345
Short name	T981
Test name
Test status
Simulation time	37217991 ps
CPU time	0.69 seconds
Started	Mar 26 01:11:58 PM PDT 24
Finished	Mar 26 01:11:59 PM PDT 24
Peak memory	199264 kb
Host	smart-2b5dc03a-d76f-496d-ad88-f328f57cd313
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623240345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clk mgr_intr_test.623240345
Directory	/workspace/35.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.clkmgr_intr_test.842683550
Short name	T921
Test name
Test status
Simulation time	16077246 ps
CPU time	0.65 seconds
Started	Mar 26 01:12:00 PM PDT 24
Finished	Mar 26 01:12:01 PM PDT 24
Peak memory	199368 kb
Host	smart-f5b318e8-34ca-4be7-bb00-fdab5cca9836
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842683550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clk mgr_intr_test.842683550
Directory	/workspace/36.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.clkmgr_intr_test.1426902890
Short name	T861
Test name
Test status
Simulation time	23458851 ps
CPU time	0.7 seconds
Started	Mar 26 01:12:02 PM PDT 24
Finished	Mar 26 01:12:02 PM PDT 24
Peak memory	199328 kb
Host	smart-1d85fe1b-4cb1-4f2a-92b8-14fa8bd972a5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426902890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl kmgr_intr_test.1426902890
Directory	/workspace/37.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.clkmgr_intr_test.1945028755
Short name	T1000
Test name
Test status
Simulation time	42163407 ps
CPU time	0.77 seconds
Started	Mar 26 01:12:00 PM PDT 24
Finished	Mar 26 01:12:01 PM PDT 24
Peak memory	199428 kb
Host	smart-bf95c863-2c8c-4359-bc04-ac9c74579fb0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945028755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl kmgr_intr_test.1945028755
Directory	/workspace/38.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.clkmgr_intr_test.3067445273
Short name	T962
Test name
Test status
Simulation time	14284102 ps
CPU time	0.68 seconds
Started	Mar 26 01:12:00 PM PDT 24
Finished	Mar 26 01:12:01 PM PDT 24
Peak memory	199252 kb
Host	smart-3d9b6810-15b5-4bcb-b51e-305b572f72a2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067445273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl kmgr_intr_test.3067445273
Directory	/workspace/39.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.261251664
Short name	T1008
Test name
Test status
Simulation time	224661470 ps
CPU time	2.18 seconds
Started	Mar 26 01:11:16 PM PDT 24
Finished	Mar 26 01:11:19 PM PDT 24
Peak memory	201044 kb
Host	smart-b40758c4-cd23-4df7-9051-a180f4ead22f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261251664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.clkmgr_csr_aliasing.261251664
Directory	/workspace/4.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.928001784
Short name	T987
Test name
Test status
Simulation time	537215515 ps
CPU time	9.27 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:27 PM PDT 24
Peak memory	201124 kb
Host	smart-aff176a9-06d1-4b05-a687-d813eebbcf85
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928001784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.clkmgr_csr_bit_bash.928001784
Directory	/workspace/4.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.37468226
Short name	T976
Test name
Test status
Simulation time	75657400 ps
CPU time	0.9 seconds
Started	Mar 26 01:11:15 PM PDT 24
Finished	Mar 26 01:11:17 PM PDT 24
Peak memory	200940 kb
Host	smart-57a627e1-09eb-414e-bafd-39445b4a149b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37468226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.clkmgr_csr_hw_reset.37468226
Directory	/workspace/4.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.930533828
Short name	T901
Test name
Test status
Simulation time	127466295 ps
CPU time	1.53 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:19 PM PDT 24
Peak memory	200916 kb
Host	smart-cf8f9918-7914-4175-bc47-7e9f4cd61441
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930533828 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.930533828
Directory	/workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.2236393063
Short name	T909
Test name
Test status
Simulation time	16801639 ps
CPU time	0.81 seconds
Started	Mar 26 01:11:16 PM PDT 24
Finished	Mar 26 01:11:17 PM PDT 24
Peak memory	200752 kb
Host	smart-73a9d347-7fcb-4c54-ab4b-dcdaf154978b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236393063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. clkmgr_csr_rw.2236393063
Directory	/workspace/4.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_intr_test.3605677712
Short name	T876
Test name
Test status
Simulation time	12143189 ps
CPU time	0.66 seconds
Started	Mar 26 01:11:15 PM PDT 24
Finished	Mar 26 01:11:17 PM PDT 24
Peak memory	199224 kb
Host	smart-fc5a08cd-25fe-4c4f-a4ba-c926acfe2621
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605677712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_intr_test.3605677712
Directory	/workspace/4.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.187841384
Short name	T930
Test name
Test status
Simulation time	33961401 ps
CPU time	1.1 seconds
Started	Mar 26 01:11:18 PM PDT 24
Finished	Mar 26 01:11:19 PM PDT 24
Peak memory	200816 kb
Host	smart-5fd78989-595a-4446-9d6b-323963e443e8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187841384 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.clkmgr_same_csr_outstanding.187841384
Directory	/workspace/4.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3376584306
Short name	T1009
Test name
Test status
Simulation time	53052667 ps
CPU time	1.66 seconds
Started	Mar 26 01:11:16 PM PDT 24
Finished	Mar 26 01:11:18 PM PDT 24
Peak memory	201080 kb
Host	smart-c265de95-d150-454e-925c-71dac314ede9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376584306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_tl_errors.3376584306
Directory	/workspace/4.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.clkmgr_intr_test.2028643448
Short name	T886
Test name
Test status
Simulation time	20715427 ps
CPU time	0.71 seconds
Started	Mar 26 01:12:04 PM PDT 24
Finished	Mar 26 01:12:05 PM PDT 24
Peak memory	199368 kb
Host	smart-82318f21-cc4a-4dd4-854a-e41ddef137fb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028643448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl kmgr_intr_test.2028643448
Directory	/workspace/40.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.clkmgr_intr_test.467686255
Short name	T893
Test name
Test status
Simulation time	31782574 ps
CPU time	0.72 seconds
Started	Mar 26 01:11:59 PM PDT 24
Finished	Mar 26 01:12:00 PM PDT 24
Peak memory	199256 kb
Host	smart-570e2d2c-beb7-416a-8094-5e2c140bcd54
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467686255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clk mgr_intr_test.467686255
Directory	/workspace/41.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.clkmgr_intr_test.2015011103
Short name	T934
Test name
Test status
Simulation time	27610665 ps
CPU time	0.7 seconds
Started	Mar 26 01:12:02 PM PDT 24
Finished	Mar 26 01:12:02 PM PDT 24
Peak memory	199144 kb
Host	smart-180a0e73-816d-4db2-a7c9-b450449ed393
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015011103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl kmgr_intr_test.2015011103
Directory	/workspace/42.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1001339942
Short name	T880
Test name
Test status
Simulation time	15303487 ps
CPU time	0.67 seconds
Started	Mar 26 01:12:01 PM PDT 24
Finished	Mar 26 01:12:02 PM PDT 24
Peak memory	198816 kb
Host	smart-5f1f36a4-1db1-4680-b614-8a063d8a8c0f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001339942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl kmgr_intr_test.1001339942
Directory	/workspace/43.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.clkmgr_intr_test.3068071910
Short name	T968
Test name
Test status
Simulation time	15234134 ps
CPU time	0.71 seconds
Started	Mar 26 01:11:59 PM PDT 24
Finished	Mar 26 01:12:00 PM PDT 24
Peak memory	199348 kb
Host	smart-58f7ff49-bce9-4690-bf73-ad6c2a9910d0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068071910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl kmgr_intr_test.3068071910
Directory	/workspace/44.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.clkmgr_intr_test.2984396081
Short name	T935
Test name
Test status
Simulation time	17389253 ps
CPU time	0.7 seconds
Started	Mar 26 01:12:01 PM PDT 24
Finished	Mar 26 01:12:02 PM PDT 24
Peak memory	199236 kb
Host	smart-20b38ee7-c54d-4cfc-9453-a27daa439ff4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984396081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl kmgr_intr_test.2984396081
Directory	/workspace/45.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2702873937
Short name	T911
Test name
Test status
Simulation time	66189978 ps
CPU time	0.8 seconds
Started	Mar 26 01:12:13 PM PDT 24
Finished	Mar 26 01:12:14 PM PDT 24
Peak memory	199224 kb
Host	smart-aaac57f4-f195-4b8e-b6c7-aca66f96988e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702873937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl kmgr_intr_test.2702873937
Directory	/workspace/46.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.clkmgr_intr_test.2907446965
Short name	T888
Test name
Test status
Simulation time	14541650 ps
CPU time	0.69 seconds
Started	Mar 26 01:12:14 PM PDT 24
Finished	Mar 26 01:12:15 PM PDT 24
Peak memory	199252 kb
Host	smart-3a24090c-8cc5-403d-9a96-c11df43edf8f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907446965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl kmgr_intr_test.2907446965
Directory	/workspace/47.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.clkmgr_intr_test.370678351
Short name	T989
Test name
Test status
Simulation time	104818384 ps
CPU time	0.87 seconds
Started	Mar 26 01:12:14 PM PDT 24
Finished	Mar 26 01:12:15 PM PDT 24
Peak memory	199428 kb
Host	smart-fd3db49f-f6e9-428b-a981-b328679b102b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370678351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clk mgr_intr_test.370678351
Directory	/workspace/48.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.clkmgr_intr_test.70943581
Short name	T948
Test name
Test status
Simulation time	18785668 ps
CPU time	0.78 seconds
Started	Mar 26 01:12:17 PM PDT 24
Finished	Mar 26 01:12:18 PM PDT 24
Peak memory	199412 kb
Host	smart-b71dc12c-6c83-476a-97de-40425515a0b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70943581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ =clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clkm gr_intr_test.70943581
Directory	/workspace/49.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.421202473
Short name	T920
Test name
Test status
Simulation time	83658814 ps
CPU time	1.41 seconds
Started	Mar 26 01:11:15 PM PDT 24
Finished	Mar 26 01:11:17 PM PDT 24
Peak memory	200904 kb
Host	smart-14b0651d-c447-4d50-9a0c-1f0b1b62acfd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421202473 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.421202473
Directory	/workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2534435958
Short name	T897
Test name
Test status
Simulation time	37938205 ps
CPU time	0.81 seconds
Started	Mar 26 01:11:16 PM PDT 24
Finished	Mar 26 01:11:17 PM PDT 24
Peak memory	200932 kb
Host	smart-faa6db55-6cfc-42ad-bcad-c58a3413a3b0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534435958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. clkmgr_csr_rw.2534435958
Directory	/workspace/5.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_intr_test.733754059
Short name	T923
Test name
Test status
Simulation time	42756348 ps
CPU time	0.73 seconds
Started	Mar 26 01:11:16 PM PDT 24
Finished	Mar 26 01:11:17 PM PDT 24
Peak memory	199236 kb
Host	smart-d0d829f9-4d42-4ec6-a71a-c5964b4f8730
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733754059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkm gr_intr_test.733754059
Directory	/workspace/5.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3204397633
Short name	T964
Test name
Test status
Simulation time	37761152 ps
CPU time	1.13 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:18 PM PDT 24
Peak memory	200444 kb
Host	smart-4b215801-6980-4c0e-8206-136700494b02
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204397633 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.clkmgr_same_csr_outstanding.3204397633
Directory	/workspace/5.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2182679964
Short name	T128
Test name
Test status
Simulation time	85622634 ps
CPU time	1.32 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:18 PM PDT 24
Peak memory	201196 kb
Host	smart-ba88e8b9-4200-4e01-a50a-f5618d6f60a7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182679964 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.clkmgr_shadow_reg_errors.2182679964
Directory	/workspace/5.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3189931279
Short name	T133
Test name
Test status
Simulation time	427610690 ps
CPU time	3.27 seconds
Started	Mar 26 01:11:18 PM PDT 24
Finished	Mar 26 01:11:22 PM PDT 24
Peak memory	201592 kb
Host	smart-fbad4851-1c04-4c16-a815-4df5e3355dbc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189931279 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.3189931279
Directory	/workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.78200796
Short name	T918
Test name
Test status
Simulation time	514226452 ps
CPU time	4.23 seconds
Started	Mar 26 01:11:15 PM PDT 24
Finished	Mar 26 01:11:21 PM PDT 24
Peak memory	200952 kb
Host	smart-2b962923-4bb0-4b77-9dd9-ee44b5aefed5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78200796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ =clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmg r_tl_errors.78200796
Directory	/workspace/5.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.3478784610
Short name	T171
Test name
Test status
Simulation time	449369052 ps
CPU time	3.09 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:20 PM PDT 24
Peak memory	201000 kb
Host	smart-24301977-042b-48e4-a7e2-6d80ed87253c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478784610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 5.clkmgr_tl_intg_err.3478784610
Directory	/workspace/5.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.957675674
Short name	T946
Test name
Test status
Simulation time	175125166 ps
CPU time	1.5 seconds
Started	Mar 26 01:11:29 PM PDT 24
Finished	Mar 26 01:11:31 PM PDT 24
Peak memory	201020 kb
Host	smart-9702b50a-478c-403a-816c-3457658d380f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957675674 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.957675674
Directory	/workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1703212032
Short name	T931
Test name
Test status
Simulation time	82111383 ps
CPU time	0.99 seconds
Started	Mar 26 01:11:29 PM PDT 24
Finished	Mar 26 01:11:30 PM PDT 24
Peak memory	200944 kb
Host	smart-2dbdef7a-7ce9-4232-9a34-4dd4d47bcee7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703212032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. clkmgr_csr_rw.1703212032
Directory	/workspace/6.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1000761270
Short name	T942
Test name
Test status
Simulation time	33351027 ps
CPU time	0.7 seconds
Started	Mar 26 01:11:29 PM PDT 24
Finished	Mar 26 01:11:30 PM PDT 24
Peak memory	199224 kb
Host	smart-64069d68-1655-4ec7-abf3-56af3141140d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000761270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk mgr_intr_test.1000761270
Directory	/workspace/6.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1862803927
Short name	T975
Test name
Test status
Simulation time	19617461 ps
CPU time	0.95 seconds
Started	Mar 26 01:11:29 PM PDT 24
Finished	Mar 26 01:11:30 PM PDT 24
Peak memory	200872 kb
Host	smart-3a6fab3e-9673-43f0-bf0a-e02f224087d7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862803927 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.clkmgr_same_csr_outstanding.1862803927
Directory	/workspace/6.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1697755072
Short name	T137
Test name
Test status
Simulation time	117129607 ps
CPU time	1.38 seconds
Started	Mar 26 01:11:14 PM PDT 24
Finished	Mar 26 01:11:15 PM PDT 24
Peak memory	201232 kb
Host	smart-0b706a68-e676-4019-b169-860ae25f2c7d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697755072 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 6.clkmgr_shadow_reg_errors.1697755072
Directory	/workspace/6.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.793372022
Short name	T68
Test name
Test status
Simulation time	313432928 ps
CPU time	2.56 seconds
Started	Mar 26 01:11:17 PM PDT 24
Finished	Mar 26 01:11:20 PM PDT 24
Peak memory	201508 kb
Host	smart-703da1e3-483c-444b-b367-16e1f354b338
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793372022 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.793372022
Directory	/workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.2520785119
Short name	T902
Test name
Test status
Simulation time	125601550 ps
CPU time	2.14 seconds
Started	Mar 26 01:11:16 PM PDT 24
Finished	Mar 26 01:11:19 PM PDT 24
Peak memory	200972 kb
Host	smart-bde85b1a-d6f9-40a7-aa55-b48d0c579581
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520785119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk mgr_tl_errors.2520785119
Directory	/workspace/6.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1477310398
Short name	T104
Test name
Test status
Simulation time	111056230 ps
CPU time	2.38 seconds
Started	Mar 26 01:11:16 PM PDT 24
Finished	Mar 26 01:11:19 PM PDT 24
Peak memory	201040 kb
Host	smart-e03d727c-2b9a-42f7-9c58-8d0737821a8d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477310398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 6.clkmgr_tl_intg_err.1477310398
Directory	/workspace/6.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1941058144
Short name	T967
Test name
Test status
Simulation time	45508881 ps
CPU time	1.09 seconds
Started	Mar 26 01:11:29 PM PDT 24
Finished	Mar 26 01:11:31 PM PDT 24
Peak memory	200884 kb
Host	smart-41fe4e7d-a31d-45c0-94dc-64d4d0e93662
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941058144 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.1941058144
Directory	/workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3152231700
Short name	T83
Test name
Test status
Simulation time	32459462 ps
CPU time	0.76 seconds
Started	Mar 26 01:11:29 PM PDT 24
Finished	Mar 26 01:11:30 PM PDT 24
Peak memory	200784 kb
Host	smart-9e27d018-5781-4ae7-b63b-91184e8d948b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152231700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. clkmgr_csr_rw.3152231700
Directory	/workspace/7.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_intr_test.885818977
Short name	T903
Test name
Test status
Simulation time	18867119 ps
CPU time	0.7 seconds
Started	Mar 26 01:11:31 PM PDT 24
Finished	Mar 26 01:11:32 PM PDT 24
Peak memory	199244 kb
Host	smart-1b07a7e3-2fa1-45d3-b677-d322ea82ca05
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885818977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkm gr_intr_test.885818977
Directory	/workspace/7.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1860696581
Short name	T84
Test name
Test status
Simulation time	54776444 ps
CPU time	1.45 seconds
Started	Mar 26 01:11:32 PM PDT 24
Finished	Mar 26 01:11:33 PM PDT 24
Peak memory	201036 kb
Host	smart-05f67c27-3a0e-445e-8cd0-8a794eb0b484
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860696581 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.clkmgr_same_csr_outstanding.1860696581
Directory	/workspace/7.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2158801327
Short name	T65
Test name
Test status
Simulation time	216447591 ps
CPU time	2.06 seconds
Started	Mar 26 01:11:29 PM PDT 24
Finished	Mar 26 01:11:31 PM PDT 24
Peak memory	201520 kb
Host	smart-f93d0a59-ad81-4ec5-a6b8-d5469136b852
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158801327 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.clkmgr_shadow_reg_errors.2158801327
Directory	/workspace/7.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2810338465
Short name	T139
Test name
Test status
Simulation time	173827012 ps
CPU time	3.38 seconds
Started	Mar 26 01:11:35 PM PDT 24
Finished	Mar 26 01:11:38 PM PDT 24
Peak memory	217792 kb
Host	smart-c3869999-e7ac-4ffb-9c70-84c2dc43eccd
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810338465 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.2810338465
Directory	/workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.3099572352
Short name	T915
Test name
Test status
Simulation time	90092291 ps
CPU time	2.68 seconds
Started	Mar 26 01:11:28 PM PDT 24
Finished	Mar 26 01:11:31 PM PDT 24
Peak memory	201108 kb
Host	smart-04166591-b6c2-405b-a026-5172adf2155f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099572352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk mgr_tl_errors.3099572352
Directory	/workspace/7.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.206624594
Short name	T953
Test name
Test status
Simulation time	197077056 ps
CPU time	1.66 seconds
Started	Mar 26 01:11:28 PM PDT 24
Finished	Mar 26 01:11:30 PM PDT 24
Peak memory	200912 kb
Host	smart-dc60b5fa-49f8-4a3c-8399-34b7cf27e73b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206624594 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.206624594
Directory	/workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3162357478
Short name	T877
Test name
Test status
Simulation time	12349896 ps
CPU time	0.75 seconds
Started	Mar 26 01:11:29 PM PDT 24
Finished	Mar 26 01:11:30 PM PDT 24
Peak memory	200804 kb
Host	smart-25a0f186-4401-48e6-99b6-129ab54dd7f2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162357478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. clkmgr_csr_rw.3162357478
Directory	/workspace/8.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_intr_test.2207792800
Short name	T884
Test name
Test status
Simulation time	11300116 ps
CPU time	0.64 seconds
Started	Mar 26 01:11:31 PM PDT 24
Finished	Mar 26 01:11:32 PM PDT 24
Peak memory	199260 kb
Host	smart-b36a543e-b2e1-49f6-8553-0ef542441382
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207792800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk mgr_intr_test.2207792800
Directory	/workspace/8.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3314279277
Short name	T992
Test name
Test status
Simulation time	745280128 ps
CPU time	2.94 seconds
Started	Mar 26 01:11:30 PM PDT 24
Finished	Mar 26 01:11:33 PM PDT 24
Peak memory	200784 kb
Host	smart-175495c3-5536-4d09-9d55-ff912c8b159d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314279277 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.clkmgr_same_csr_outstanding.3314279277
Directory	/workspace/8.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.2223948335
Short name	T950
Test name
Test status
Simulation time	54534919 ps
CPU time	1.22 seconds
Started	Mar 26 01:11:27 PM PDT 24
Finished	Mar 26 01:11:29 PM PDT 24
Peak memory	201220 kb
Host	smart-7f91cab4-f9cd-4508-a5cd-d7c39ac4e233
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223948335 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 8.clkmgr_shadow_reg_errors.2223948335
Directory	/workspace/8.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3029828215
Short name	T121
Test name
Test status
Simulation time	431525636 ps
CPU time	3.5 seconds
Started	Mar 26 01:11:30 PM PDT 24
Finished	Mar 26 01:11:33 PM PDT 24
Peak memory	201556 kb
Host	smart-cc0521cc-2e2e-4586-868f-abd6f845761f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029828215 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.3029828215
Directory	/workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.683516411
Short name	T910
Test name
Test status
Simulation time	44750735 ps
CPU time	1.46 seconds
Started	Mar 26 01:11:31 PM PDT 24
Finished	Mar 26 01:11:32 PM PDT 24
Peak memory	200988 kb
Host	smart-ba1bbbc9-aaca-4906-82db-b17798447c32
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683516411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm gr_tl_errors.683516411
Directory	/workspace/8.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2631255922
Short name	T170
Test name
Test status
Simulation time	110899718 ps
CPU time	1.73 seconds
Started	Mar 26 01:11:30 PM PDT 24
Finished	Mar 26 01:11:32 PM PDT 24
Peak memory	201112 kb
Host	smart-19ef24eb-35f7-4cb2-b7c4-e541d6466310
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631255922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 8.clkmgr_tl_intg_err.2631255922
Directory	/workspace/8.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.2875408018
Short name	T983
Test name
Test status
Simulation time	90849455 ps
CPU time	1.92 seconds
Started	Mar 26 01:11:28 PM PDT 24
Finished	Mar 26 01:11:31 PM PDT 24
Peak memory	201184 kb
Host	smart-8f1220b6-8a03-4d0b-902e-2b3bfa468add
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875408018 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.2875408018
Directory	/workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3555319300
Short name	T894
Test name
Test status
Simulation time	18230834 ps
CPU time	0.76 seconds
Started	Mar 26 01:11:27 PM PDT 24
Finished	Mar 26 01:11:29 PM PDT 24
Peak memory	200916 kb
Host	smart-ad470916-8290-4ab4-85ab-dfc3aea2f116
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555319300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. clkmgr_csr_rw.3555319300
Directory	/workspace/9.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_intr_test.3150063301
Short name	T889
Test name
Test status
Simulation time	20019232 ps
CPU time	0.68 seconds
Started	Mar 26 01:11:30 PM PDT 24
Finished	Mar 26 01:11:31 PM PDT 24
Peak memory	199260 kb
Host	smart-3ea0ca5c-69a9-4c8c-8274-4085c7c442b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150063301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk mgr_intr_test.3150063301
Directory	/workspace/9.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1953647962
Short name	T973
Test name
Test status
Simulation time	136165097 ps
CPU time	1.51 seconds
Started	Mar 26 01:11:27 PM PDT 24
Finished	Mar 26 01:11:28 PM PDT 24
Peak memory	200792 kb
Host	smart-bdbe8d61-1a32-4992-ba91-d6f9766b0dbd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953647962 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.clkmgr_same_csr_outstanding.1953647962
Directory	/workspace/9.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3339173517
Short name	T134
Test name
Test status
Simulation time	182729017 ps
CPU time	1.62 seconds
Started	Mar 26 01:11:32 PM PDT 24
Finished	Mar 26 01:11:34 PM PDT 24
Peak memory	201292 kb
Host	smart-60984179-79ef-4f36-815a-766b2bae9c44
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339173517 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.clkmgr_shadow_reg_errors.3339173517
Directory	/workspace/9.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.1066182805
Short name	T943
Test name
Test status
Simulation time	142892626 ps
CPU time	2.89 seconds
Started	Mar 26 01:11:32 PM PDT 24
Finished	Mar 26 01:11:35 PM PDT 24
Peak memory	201484 kb
Host	smart-bd10610b-b8f9-4b85-887e-ea59f321bc02
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066182805 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.1066182805
Directory	/workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.251488615
Short name	T958
Test name
Test status
Simulation time	248614984 ps
CPU time	2.88 seconds
Started	Mar 26 01:11:29 PM PDT 24
Finished	Mar 26 01:11:32 PM PDT 24
Peak memory	201052 kb
Host	smart-6654ffdb-c09b-4043-ab2f-6f786ecced47
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251488615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkm gr_tl_errors.251488615
Directory	/workspace/9.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.509502797
Short name	T99
Test name
Test status
Simulation time	122230760 ps
CPU time	2.8 seconds
Started	Mar 26 01:11:31 PM PDT 24
Finished	Mar 26 01:11:34 PM PDT 24
Peak memory	201016 kb
Host	smart-e6938dba-a60d-4d85-a8d9-3152fed451ae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509502797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 9.clkmgr_tl_intg_err.509502797
Directory	/workspace/9.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/0.clkmgr_alert_test.3364285540
Short name	T544
Test name
Test status
Simulation time	13547089 ps
CPU time	0.67 seconds
Started	Mar 26 12:37:23 PM PDT 24
Finished	Mar 26 12:37:24 PM PDT 24
Peak memory	200216 kb
Host	smart-116bf5f5-e433-4906-9bea-7ef614ca9820
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364285540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm gr_alert_test.3364285540
Directory	/workspace/0.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.4141605319
Short name	T726
Test name
Test status
Simulation time	81312239 ps
CPU time	1.03 seconds
Started	Mar 26 12:37:19 PM PDT 24
Finished	Mar 26 12:37:20 PM PDT 24
Peak memory	200568 kb
Host	smart-0285f4bf-06cb-451e-bcdf-62a78a2daff5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141605319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.4141605319
Directory	/workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_status.2166226811
Short name	T414
Test name
Test status
Simulation time	14286596 ps
CPU time	0.71 seconds
Started	Mar 26 12:37:20 PM PDT 24
Finished	Mar 26 12:37:21 PM PDT 24
Peak memory	200524 kb
Host	smart-d021215c-a4f5-4895-8995-a6d6152b1cf6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166226811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.2166226811
Directory	/workspace/0.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/0.clkmgr_div_intersig_mubi.919035462
Short name	T825
Test name
Test status
Simulation time	21557001 ps
CPU time	0.8 seconds
Started	Mar 26 12:37:19 PM PDT 24
Finished	Mar 26 12:37:20 PM PDT 24
Peak memory	200580 kb
Host	smart-d685dfd0-24b4-46bf-b694-aa50f1bdf595
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919035462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .clkmgr_div_intersig_mubi.919035462
Directory	/workspace/0.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_extclk.2267492575
Short name	T655
Test name
Test status
Simulation time	41906953 ps
CPU time	0.84 seconds
Started	Mar 26 12:37:19 PM PDT 24
Finished	Mar 26 12:37:20 PM PDT 24
Peak memory	200528 kb
Host	smart-9ef9508f-7aaa-4b59-b853-491d88ebd3ea
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267492575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2267492575
Directory	/workspace/0.clkmgr_extclk/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency.2691648207
Short name	T518
Test name
Test status
Simulation time	2004183225 ps
CPU time	10.18 seconds
Started	Mar 26 12:37:18 PM PDT 24
Finished	Mar 26 12:37:28 PM PDT 24
Peak memory	200632 kb
Host	smart-107ef691-5e8f-430a-b7bd-bec588c44cfa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691648207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.2691648207
Directory	/workspace/0.clkmgr_frequency/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency_timeout.1913399428
Short name	T459
Test name
Test status
Simulation time	1821496618 ps
CPU time	9.32 seconds
Started	Mar 26 12:37:31 PM PDT 24
Finished	Mar 26 12:37:40 PM PDT 24
Peak memory	200560 kb
Host	smart-f203542f-b4ae-4d5a-ac13-1b515d5a340b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913399428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti meout.1913399428
Directory	/workspace/0.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/0.clkmgr_idle_intersig_mubi.2802375876
Short name	T773
Test name
Test status
Simulation time	46698240 ps
CPU time	1.06 seconds
Started	Mar 26 12:37:21 PM PDT 24
Finished	Mar 26 12:37:23 PM PDT 24
Peak memory	200492 kb
Host	smart-76613aa2-75cb-4811-a244-de4da70a13d6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802375876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.2802375876
Directory	/workspace/0.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.2653041199
Short name	T569
Test name
Test status
Simulation time	65210450 ps
CPU time	0.94 seconds
Started	Mar 26 12:37:19 PM PDT 24
Finished	Mar 26 12:37:20 PM PDT 24
Peak memory	200576 kb
Host	smart-9a14eb0b-4fc8-4831-9576-d6f89fc1d7fd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653041199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.clkmgr_lc_clk_byp_req_intersig_mubi.2653041199
Directory	/workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.507426708
Short name	T188
Test name
Test status
Simulation time	91593849 ps
CPU time	1.1 seconds
Started	Mar 26 12:37:21 PM PDT 24
Finished	Mar 26 12:37:23 PM PDT 24
Peak memory	200536 kb
Host	smart-06ce9181-f8ca-4d1d-bf5a-1d2b1e2a6163
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507426708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.clkmgr_lc_ctrl_intersig_mubi.507426708
Directory	/workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_peri.1456698112
Short name	T661
Test name
Test status
Simulation time	25257580 ps
CPU time	0.76 seconds
Started	Mar 26 12:37:21 PM PDT 24
Finished	Mar 26 12:37:22 PM PDT 24
Peak memory	200536 kb
Host	smart-7d7ba284-1143-427b-ab11-3ffd612f9d7d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456698112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.1456698112
Directory	/workspace/0.clkmgr_peri/latest

Test location	/workspace/coverage/default/0.clkmgr_regwen.860325506
Short name	T466
Test name
Test status
Simulation time	240168365 ps
CPU time	1.34 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200652 kb
Host	smart-35c10aa4-dc93-432e-b04e-f5d7bb154b3e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860325506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.860325506
Directory	/workspace/0.clkmgr_regwen/latest

Test location	/workspace/coverage/default/0.clkmgr_smoke.722369199
Short name	T703
Test name
Test status
Simulation time	114716364 ps
CPU time	1.11 seconds
Started	Mar 26 12:37:20 PM PDT 24
Finished	Mar 26 12:37:21 PM PDT 24
Peak memory	200636 kb
Host	smart-9e2b438b-0550-4e87-9029-d252ccc18f6e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722369199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.722369199
Directory	/workspace/0.clkmgr_smoke/latest

Test location	/workspace/coverage/default/0.clkmgr_stress_all.521629650
Short name	T810
Test name
Test status
Simulation time	31574398 ps
CPU time	0.85 seconds
Started	Mar 26 12:37:23 PM PDT 24
Finished	Mar 26 12:37:24 PM PDT 24
Peak memory	200332 kb
Host	smart-2bbff454-7441-4f23-94b6-3e0fede3c7f7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521629650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.521629650
Directory	/workspace/0.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.3551838611
Short name	T156
Test name
Test status
Simulation time	46554959936 ps
CPU time	707.32 seconds
Started	Mar 26 12:37:17 PM PDT 24
Finished	Mar 26 12:49:05 PM PDT 24
Peak memory	217416 kb
Host	smart-c5da0e8a-5c1e-4cba-821a-65a5fb489624
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3551838611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.3551838611
Directory	/workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.clkmgr_trans.3512756064
Short name	T111
Test name
Test status
Simulation time	397444546 ps
CPU time	1.99 seconds
Started	Mar 26 12:37:18 PM PDT 24
Finished	Mar 26 12:37:20 PM PDT 24
Peak memory	200552 kb
Host	smart-d9dcfbf4-0234-41b1-9a7d-aca94f51de07
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512756064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.3512756064
Directory	/workspace/0.clkmgr_trans/latest

Test location	/workspace/coverage/default/1.clkmgr_alert_test.1658555220
Short name	T439
Test name
Test status
Simulation time	60709945 ps
CPU time	0.98 seconds
Started	Mar 26 12:37:30 PM PDT 24
Finished	Mar 26 12:37:31 PM PDT 24
Peak memory	200680 kb
Host	smart-55acee54-b7f7-4143-872e-6f4b30731b3c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658555220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm gr_alert_test.1658555220
Directory	/workspace/1.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.2904109207
Short name	T204
Test name
Test status
Simulation time	18670445 ps
CPU time	0.82 seconds
Started	Mar 26 12:37:31 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200568 kb
Host	smart-591fe6c4-8090-4c9d-9420-dc544284c311
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904109207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.2904109207
Directory	/workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_status.3298721100
Short name	T508
Test name
Test status
Simulation time	21481413 ps
CPU time	0.7 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	199432 kb
Host	smart-d591ca87-2b57-4760-a2a1-90568c01a509
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298721100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.3298721100
Directory	/workspace/1.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/1.clkmgr_div_intersig_mubi.4019387207
Short name	T681
Test name
Test status
Simulation time	74694258 ps
CPU time	0.98 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200572 kb
Host	smart-c2c46499-5861-4674-8ce2-a9d8263b9814
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019387207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.4019387207
Directory	/workspace/1.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_extclk.1639384870
Short name	T380
Test name
Test status
Simulation time	35990938 ps
CPU time	0.85 seconds
Started	Mar 26 12:37:22 PM PDT 24
Finished	Mar 26 12:37:24 PM PDT 24
Peak memory	200576 kb
Host	smart-0a321b74-bf8f-441e-9dd4-b78586bebe7a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639384870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1639384870
Directory	/workspace/1.clkmgr_extclk/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency.3364591952
Short name	T431
Test name
Test status
Simulation time	2257650926 ps
CPU time	9.6 seconds
Started	Mar 26 12:37:22 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200768 kb
Host	smart-54dec016-b8cd-471c-9a1d-360e8dd2adce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364591952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.3364591952
Directory	/workspace/1.clkmgr_frequency/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency_timeout.3018643699
Short name	T282
Test name
Test status
Simulation time	155624483 ps
CPU time	1.21 seconds
Started	Mar 26 12:37:22 PM PDT 24
Finished	Mar 26 12:37:24 PM PDT 24
Peak memory	200432 kb
Host	smart-90c16ed2-c0ed-4b0b-8dac-6b5fd914c332
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018643699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti meout.3018643699
Directory	/workspace/1.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/1.clkmgr_idle_intersig_mubi.1864043478
Short name	T493
Test name
Test status
Simulation time	14280350 ps
CPU time	0.71 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200364 kb
Host	smart-c35f6307-ee2f-4b5c-af1f-1875d4981042
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864043478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.1864043478
Directory	/workspace/1.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.2700547647
Short name	T588
Test name
Test status
Simulation time	37621855 ps
CPU time	0.89 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200576 kb
Host	smart-a2499fb2-76a1-4e8b-98b9-18619107d264
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700547647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_clk_byp_req_intersig_mubi.2700547647
Directory	/workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.2747582128
Short name	T593
Test name
Test status
Simulation time	19494060 ps
CPU time	0.77 seconds
Started	Mar 26 12:37:30 PM PDT 24
Finished	Mar 26 12:37:31 PM PDT 24
Peak memory	200584 kb
Host	smart-0a209dc0-6ba7-46f7-8140-311eb1d8c065
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747582128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_ctrl_intersig_mubi.2747582128
Directory	/workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_peri.962018938
Short name	T384
Test name
Test status
Simulation time	12059366 ps
CPU time	0.69 seconds
Started	Mar 26 12:37:20 PM PDT 24
Finished	Mar 26 12:37:21 PM PDT 24
Peak memory	200560 kb
Host	smart-7114bf4f-8aae-438f-a278-56e01554cdcd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962018938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.962018938
Directory	/workspace/1.clkmgr_peri/latest

Test location	/workspace/coverage/default/1.clkmgr_regwen.2011768076
Short name	T154
Test name
Test status
Simulation time	678066330 ps
CPU time	4.36 seconds
Started	Mar 26 12:37:34 PM PDT 24
Finished	Mar 26 12:37:39 PM PDT 24
Peak memory	200632 kb
Host	smart-457b132d-d036-4ded-a830-8ed8d9d34eb4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011768076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.2011768076
Directory	/workspace/1.clkmgr_regwen/latest

Test location	/workspace/coverage/default/1.clkmgr_sec_cm.2246678871
Short name	T59
Test name
Test status
Simulation time	325756178 ps
CPU time	2.26 seconds
Started	Mar 26 12:37:29 PM PDT 24
Finished	Mar 26 12:37:31 PM PDT 24
Peak memory	215964 kb
Host	smart-e07e882f-f125-4233-83fd-66c126426d57
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246678871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg r_sec_cm.2246678871
Directory	/workspace/1.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/1.clkmgr_smoke.3113290374
Short name	T423
Test name
Test status
Simulation time	20151830 ps
CPU time	0.83 seconds
Started	Mar 26 12:37:22 PM PDT 24
Finished	Mar 26 12:37:24 PM PDT 24
Peak memory	200556 kb
Host	smart-8588fe53-714f-4b55-9d2e-6ffddc534f23
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113290374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.3113290374
Directory	/workspace/1.clkmgr_smoke/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all.756777917
Short name	T42
Test name
Test status
Simulation time	8274866985 ps
CPU time	32.93 seconds
Started	Mar 26 12:37:28 PM PDT 24
Finished	Mar 26 12:38:01 PM PDT 24
Peak memory	200888 kb
Host	smart-1d14eb36-4690-45a5-a93e-8a45e86c14d2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756777917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.756777917
Directory	/workspace/1.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.149202493
Short name	T3
Test name
Test status
Simulation time	87659371025 ps
CPU time	373.68 seconds
Started	Mar 26 12:37:31 PM PDT 24
Finished	Mar 26 12:43:45 PM PDT 24
Peak memory	209224 kb
Host	smart-77415d27-b7a9-44e6-8819-acf10fcc0337
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=149202493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.149202493
Directory	/workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.clkmgr_trans.1542690844
Short name	T276
Test name
Test status
Simulation time	27156949 ps
CPU time	0.77 seconds
Started	Mar 26 12:37:22 PM PDT 24
Finished	Mar 26 12:37:24 PM PDT 24
Peak memory	200412 kb
Host	smart-488c9bef-200b-4433-9d04-aa9bf9b8145e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542690844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.1542690844
Directory	/workspace/1.clkmgr_trans/latest

Test location	/workspace/coverage/default/10.clkmgr_alert_test.1269990261
Short name	T791
Test name
Test status
Simulation time	19647287 ps
CPU time	0.81 seconds
Started	Mar 26 12:37:43 PM PDT 24
Finished	Mar 26 12:37:44 PM PDT 24
Peak memory	200700 kb
Host	smart-79397f71-233b-4360-b22c-7369a5e7bb7e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269990261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk mgr_alert_test.1269990261
Directory	/workspace/10.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.2161986490
Short name	T394
Test name
Test status
Simulation time	48471756 ps
CPU time	0.94 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200512 kb
Host	smart-fb59b8da-649c-4fe4-a71e-7355ab01e4dc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161986490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.2161986490
Directory	/workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_status.2511180803
Short name	T725
Test name
Test status
Simulation time	46032798 ps
CPU time	0.81 seconds
Started	Mar 26 12:37:45 PM PDT 24
Finished	Mar 26 12:37:46 PM PDT 24
Peak memory	199528 kb
Host	smart-7138c560-bfdc-4020-b38a-d8f8ff5bb15a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511180803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.2511180803
Directory	/workspace/10.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/10.clkmgr_div_intersig_mubi.1056983108
Short name	T581
Test name
Test status
Simulation time	25414281 ps
CPU time	0.89 seconds
Started	Mar 26 12:37:46 PM PDT 24
Finished	Mar 26 12:37:48 PM PDT 24
Peak memory	200580 kb
Host	smart-109b5bb8-c483-44fe-b5bc-afaaa23879fc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056983108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_div_intersig_mubi.1056983108
Directory	/workspace/10.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_extclk.3643171424
Short name	T56
Test name
Test status
Simulation time	24404842 ps
CPU time	0.8 seconds
Started	Mar 26 12:37:44 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200556 kb
Host	smart-754c4449-9805-4021-a8be-93e09ed14ad7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643171424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.3643171424
Directory	/workspace/10.clkmgr_extclk/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency.4197913095
Short name	T304
Test name
Test status
Simulation time	800188155 ps
CPU time	6.09 seconds
Started	Mar 26 12:37:46 PM PDT 24
Finished	Mar 26 12:37:53 PM PDT 24
Peak memory	200580 kb
Host	smart-0645c4e9-9165-450b-a27b-53fdc12c02d9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197913095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.4197913095
Directory	/workspace/10.clkmgr_frequency/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency_timeout.2265519448
Short name	T715
Test name
Test status
Simulation time	256848597 ps
CPU time	2.51 seconds
Started	Mar 26 12:37:46 PM PDT 24
Finished	Mar 26 12:37:48 PM PDT 24
Peak memory	200636 kb
Host	smart-584d2883-690c-4895-accf-330161d6d72f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265519448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t imeout.2265519448
Directory	/workspace/10.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/10.clkmgr_idle_intersig_mubi.1961210803
Short name	T338
Test name
Test status
Simulation time	102632128 ps
CPU time	1.11 seconds
Started	Mar 26 12:37:40 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200504 kb
Host	smart-4d72c523-74b2-4a8b-b0d9-51785ff5512d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961210803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.1961210803
Directory	/workspace/10.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.2997104859
Short name	T146
Test name
Test status
Simulation time	13033923 ps
CPU time	0.77 seconds
Started	Mar 26 12:37:46 PM PDT 24
Finished	Mar 26 12:37:47 PM PDT 24
Peak memory	200560 kb
Host	smart-e0ecf7af-2d89-49f7-94e0-77a1e8760679
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997104859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_clk_byp_req_intersig_mubi.2997104859
Directory	/workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.3058488225
Short name	T828
Test name
Test status
Simulation time	152655754 ps
CPU time	1.16 seconds
Started	Mar 26 12:37:45 PM PDT 24
Finished	Mar 26 12:37:46 PM PDT 24
Peak memory	200592 kb
Host	smart-9053bf62-a6da-4069-aad5-f495ad740b0d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058488225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_ctrl_intersig_mubi.3058488225
Directory	/workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_peri.680934278
Short name	T183
Test name
Test status
Simulation time	15402557 ps
CPU time	0.79 seconds
Started	Mar 26 12:37:44 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200628 kb
Host	smart-7bb3ebf2-b26e-4616-aa66-fb25b76ea97e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680934278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.680934278
Directory	/workspace/10.clkmgr_peri/latest

Test location	/workspace/coverage/default/10.clkmgr_regwen.188100859
Short name	T177
Test name
Test status
Simulation time	1286407540 ps
CPU time	7.39 seconds
Started	Mar 26 12:37:50 PM PDT 24
Finished	Mar 26 12:37:57 PM PDT 24
Peak memory	200632 kb
Host	smart-c004ef54-c9e0-4671-9f4c-5ba14c2e2ade
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188100859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.188100859
Directory	/workspace/10.clkmgr_regwen/latest

Test location	/workspace/coverage/default/10.clkmgr_smoke.3704328969
Short name	T644
Test name
Test status
Simulation time	42692997 ps
CPU time	0.86 seconds
Started	Mar 26 12:37:45 PM PDT 24
Finished	Mar 26 12:37:47 PM PDT 24
Peak memory	200568 kb
Host	smart-11fdd299-a885-4607-9b31-e4d3370b4e3c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704328969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.3704328969
Directory	/workspace/10.clkmgr_smoke/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all.3680263255
Short name	T320
Test name
Test status
Simulation time	3906181113 ps
CPU time	22.01 seconds
Started	Mar 26 12:37:43 PM PDT 24
Finished	Mar 26 12:38:06 PM PDT 24
Peak memory	200828 kb
Host	smart-f2793984-602f-49fe-b536-e9ca37f8b533
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680263255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.3680263255
Directory	/workspace/10.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.1077398199
Short name	T73
Test name
Test status
Simulation time	49562997166 ps
CPU time	307.93 seconds
Started	Mar 26 12:37:40 PM PDT 24
Finished	Mar 26 12:42:50 PM PDT 24
Peak memory	209228 kb
Host	smart-96397bd5-4637-4429-8250-26dd69e9f67a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1077398199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.1077398199
Directory	/workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.clkmgr_trans.2276828920
Short name	T258
Test name
Test status
Simulation time	245773407 ps
CPU time	1.67 seconds
Started	Mar 26 12:37:45 PM PDT 24
Finished	Mar 26 12:37:48 PM PDT 24
Peak memory	200540 kb
Host	smart-0987d5ba-5ba5-4ef5-b547-c597d19fbb89
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276828920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2276828920
Directory	/workspace/10.clkmgr_trans/latest

Test location	/workspace/coverage/default/11.clkmgr_alert_test.1106796719
Short name	T674
Test name
Test status
Simulation time	58964058 ps
CPU time	0.89 seconds
Started	Mar 26 12:37:57 PM PDT 24
Finished	Mar 26 12:37:58 PM PDT 24
Peak memory	200640 kb
Host	smart-83c6f6f2-da3c-44e4-957f-a38f59e94478
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106796719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk mgr_alert_test.1106796719
Directory	/workspace/11.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.3688300755
Short name	T512
Test name
Test status
Simulation time	41961762 ps
CPU time	0.84 seconds
Started	Mar 26 12:37:44 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200592 kb
Host	smart-feff6321-cf07-4faa-a95c-fb8c99261f52
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688300755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.3688300755
Directory	/workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_status.1857951302
Short name	T166
Test name
Test status
Simulation time	45486004 ps
CPU time	0.8 seconds
Started	Mar 26 12:37:49 PM PDT 24
Finished	Mar 26 12:37:50 PM PDT 24
Peak memory	199488 kb
Host	smart-1b108b77-e1e1-46a0-8576-d0721a553bb2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857951302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.1857951302
Directory	/workspace/11.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/11.clkmgr_div_intersig_mubi.2048134660
Short name	T838
Test name
Test status
Simulation time	13445857 ps
CPU time	0.71 seconds
Started	Mar 26 12:37:53 PM PDT 24
Finished	Mar 26 12:37:54 PM PDT 24
Peak memory	200552 kb
Host	smart-5f945cbe-b589-43f6-a770-eb41957aef67
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048134660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.2048134660
Directory	/workspace/11.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_extclk.2014930279
Short name	T716
Test name
Test status
Simulation time	30704833 ps
CPU time	0.77 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200580 kb
Host	smart-d0bca297-ebe3-4f3f-b065-b27ce9f65b17
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014930279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.2014930279
Directory	/workspace/11.clkmgr_extclk/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency.2568018322
Short name	T747
Test name
Test status
Simulation time	919198474 ps
CPU time	7.27 seconds
Started	Mar 26 12:37:49 PM PDT 24
Finished	Mar 26 12:37:57 PM PDT 24
Peak memory	200524 kb
Host	smart-735b9caa-b7e6-4ff5-abf4-d7c70254f21c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568018322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.2568018322
Directory	/workspace/11.clkmgr_frequency/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency_timeout.149959429
Short name	T211
Test name
Test status
Simulation time	985726351 ps
CPU time	5.45 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:48 PM PDT 24
Peak memory	200608 kb
Host	smart-fadc7f64-7562-4ca5-8f7d-e668b542d4f9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149959429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_ti meout.149959429
Directory	/workspace/11.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/11.clkmgr_idle_intersig_mubi.1525554690
Short name	T330
Test name
Test status
Simulation time	19682377 ps
CPU time	0.82 seconds
Started	Mar 26 12:37:46 PM PDT 24
Finished	Mar 26 12:37:48 PM PDT 24
Peak memory	200628 kb
Host	smart-5e6cf157-5f36-474d-a55a-0b482c58a57f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525554690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.1525554690
Directory	/workspace/11.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1455474594
Short name	T312
Test name
Test status
Simulation time	53752716 ps
CPU time	0.94 seconds
Started	Mar 26 12:37:46 PM PDT 24
Finished	Mar 26 12:37:48 PM PDT 24
Peak memory	200640 kb
Host	smart-7a933850-43b3-499b-9e24-94c79f4e0d87
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455474594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 11.clkmgr_lc_clk_byp_req_intersig_mubi.1455474594
Directory	/workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.1228776817
Short name	T654
Test name
Test status
Simulation time	35708659 ps
CPU time	0.85 seconds
Started	Mar 26 12:37:44 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200540 kb
Host	smart-30fd2c76-2c0f-4962-bd67-4549ed38bae0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228776817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 11.clkmgr_lc_ctrl_intersig_mubi.1228776817
Directory	/workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_peri.1985115717
Short name	T592
Test name
Test status
Simulation time	46142421 ps
CPU time	0.86 seconds
Started	Mar 26 12:37:47 PM PDT 24
Finished	Mar 26 12:37:48 PM PDT 24
Peak memory	200604 kb
Host	smart-54cfd295-3469-4fba-b346-1b8220cbd771
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985115717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.1985115717
Directory	/workspace/11.clkmgr_peri/latest

Test location	/workspace/coverage/default/11.clkmgr_regwen.3850999005
Short name	T749
Test name
Test status
Simulation time	411559165 ps
CPU time	2.73 seconds
Started	Mar 26 12:37:57 PM PDT 24
Finished	Mar 26 12:38:01 PM PDT 24
Peak memory	200576 kb
Host	smart-a785da08-643c-4be5-b1cf-59de6ea0192e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850999005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.3850999005
Directory	/workspace/11.clkmgr_regwen/latest

Test location	/workspace/coverage/default/11.clkmgr_smoke.849258652
Short name	T402
Test name
Test status
Simulation time	47283983 ps
CPU time	0.84 seconds
Started	Mar 26 12:37:43 PM PDT 24
Finished	Mar 26 12:37:44 PM PDT 24
Peak memory	200624 kb
Host	smart-a8064177-2ab9-45b0-b98d-cc4cee375630
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849258652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.849258652
Directory	/workspace/11.clkmgr_smoke/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all.2392720088
Short name	T337
Test name
Test status
Simulation time	64876042 ps
CPU time	0.95 seconds
Started	Mar 26 12:37:56 PM PDT 24
Finished	Mar 26 12:37:57 PM PDT 24
Peak memory	200536 kb
Host	smart-58aa797d-169b-4153-bed1-7c332ea371fc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392720088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.2392720088
Directory	/workspace/11.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.1272126541
Short name	T356
Test name
Test status
Simulation time	24892464769 ps
CPU time	161.25 seconds
Started	Mar 26 12:37:57 PM PDT 24
Finished	Mar 26 12:40:39 PM PDT 24
Peak memory	209252 kb
Host	smart-14625ef0-aedd-4cf6-9bee-21b39c25a5fa
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1272126541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.1272126541
Directory	/workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.clkmgr_trans.784417464
Short name	T245
Test name
Test status
Simulation time	26743557 ps
CPU time	0.91 seconds
Started	Mar 26 12:37:49 PM PDT 24
Finished	Mar 26 12:37:50 PM PDT 24
Peak memory	200548 kb
Host	smart-c6e4b43b-2ce8-4242-bfc8-f93158368802
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784417464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.784417464
Directory	/workspace/11.clkmgr_trans/latest

Test location	/workspace/coverage/default/12.clkmgr_alert_test.1963552853
Short name	T350
Test name
Test status
Simulation time	18299060 ps
CPU time	0.74 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:37:59 PM PDT 24
Peak memory	200632 kb
Host	smart-7f17de8d-4715-4a45-bc98-1d21c367d4e1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963552853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk mgr_alert_test.1963552853
Directory	/workspace/12.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.1753027399
Short name	T57
Test name
Test status
Simulation time	76414228 ps
CPU time	1.01 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:37:59 PM PDT 24
Peak memory	200596 kb
Host	smart-dbf00087-67b4-43d0-888d-797ae6366545
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753027399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.1753027399
Directory	/workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_status.3871227142
Short name	T520
Test name
Test status
Simulation time	13876050 ps
CPU time	0.67 seconds
Started	Mar 26 12:37:55 PM PDT 24
Finished	Mar 26 12:37:55 PM PDT 24
Peak memory	200488 kb
Host	smart-4b61c37f-36a1-4673-8691-0e61511b6ccf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871227142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.3871227142
Directory	/workspace/12.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/12.clkmgr_div_intersig_mubi.3271306889
Short name	T616
Test name
Test status
Simulation time	16548679 ps
CPU time	0.75 seconds
Started	Mar 26 12:37:56 PM PDT 24
Finished	Mar 26 12:37:57 PM PDT 24
Peak memory	200584 kb
Host	smart-9e5d87b5-72fc-4466-b89d-0c3d8e83de28
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271306889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.3271306889
Directory	/workspace/12.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_extclk.1044499678
Short name	T462
Test name
Test status
Simulation time	70161121 ps
CPU time	1.12 seconds
Started	Mar 26 12:37:56 PM PDT 24
Finished	Mar 26 12:37:58 PM PDT 24
Peak memory	200568 kb
Host	smart-0a334399-be0c-43a4-9632-6018e5c96124
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044499678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.1044499678
Directory	/workspace/12.clkmgr_extclk/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency.3359737257
Short name	T482
Test name
Test status
Simulation time	228787371 ps
CPU time	1.66 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:38:01 PM PDT 24
Peak memory	200600 kb
Host	smart-c077747d-187d-4f65-abbf-208be8695b67
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359737257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.3359737257
Directory	/workspace/12.clkmgr_frequency/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency_timeout.234488343
Short name	T358
Test name
Test status
Simulation time	1245621079 ps
CPU time	5.5 seconds
Started	Mar 26 12:37:56 PM PDT 24
Finished	Mar 26 12:38:02 PM PDT 24
Peak memory	200632 kb
Host	smart-ae9bfce7-230c-466b-8e3e-4b98c98a3835
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234488343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_ti meout.234488343
Directory	/workspace/12.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/12.clkmgr_idle_intersig_mubi.3312080080
Short name	T800
Test name
Test status
Simulation time	47564634 ps
CPU time	0.97 seconds
Started	Mar 26 12:37:59 PM PDT 24
Finished	Mar 26 12:38:01 PM PDT 24
Peak memory	200540 kb
Host	smart-007f4283-4230-4e5c-8f97-4d48aff4f5fe
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312080080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.3312080080
Directory	/workspace/12.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.1113870457
Short name	T622
Test name
Test status
Simulation time	84708140 ps
CPU time	0.95 seconds
Started	Mar 26 12:37:56 PM PDT 24
Finished	Mar 26 12:37:57 PM PDT 24
Peak memory	200640 kb
Host	smart-8f070515-7ccc-4fac-8bab-9fa1e9886635
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113870457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_clk_byp_req_intersig_mubi.1113870457
Directory	/workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1705506760
Short name	T323
Test name
Test status
Simulation time	49860660 ps
CPU time	1.01 seconds
Started	Mar 26 12:37:57 PM PDT 24
Finished	Mar 26 12:37:58 PM PDT 24
Peak memory	200536 kb
Host	smart-4547c7f9-4ecf-4bb6-bbb2-91b484351692
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705506760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_ctrl_intersig_mubi.1705506760
Directory	/workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_peri.206783377
Short name	T206
Test name
Test status
Simulation time	41502010 ps
CPU time	0.82 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:38:00 PM PDT 24
Peak memory	200588 kb
Host	smart-02d881d4-7d13-4d29-aa0e-861732477c40
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206783377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.206783377
Directory	/workspace/12.clkmgr_peri/latest

Test location	/workspace/coverage/default/12.clkmgr_regwen.1746549081
Short name	T151
Test name
Test status
Simulation time	1243608108 ps
CPU time	7.02 seconds
Started	Mar 26 12:37:57 PM PDT 24
Finished	Mar 26 12:38:05 PM PDT 24
Peak memory	200652 kb
Host	smart-275d6ded-54f5-4bd4-82e9-57b5f20cd8bd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746549081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.1746549081
Directory	/workspace/12.clkmgr_regwen/latest

Test location	/workspace/coverage/default/12.clkmgr_smoke.3909634213
Short name	T613
Test name
Test status
Simulation time	14883469 ps
CPU time	0.87 seconds
Started	Mar 26 12:37:57 PM PDT 24
Finished	Mar 26 12:38:00 PM PDT 24
Peak memory	200652 kb
Host	smart-bac70d5b-e73b-43e0-a153-439898d7f1e5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909634213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.3909634213
Directory	/workspace/12.clkmgr_smoke/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all.3406867768
Short name	T449
Test name
Test status
Simulation time	6454624008 ps
CPU time	27.01 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:38:26 PM PDT 24
Peak memory	200816 kb
Host	smart-1c93b064-538f-4b0d-9c77-91a445919d18
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406867768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.3406867768
Directory	/workspace/12.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.2965189481
Short name	T632
Test name
Test status
Simulation time	31797460126 ps
CPU time	602.15 seconds
Started	Mar 26 12:37:57 PM PDT 24
Finished	Mar 26 12:48:00 PM PDT 24
Peak memory	217388 kb
Host	smart-c1511c26-9fe3-4593-a522-e6564f143b36
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2965189481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.2965189481
Directory	/workspace/12.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.clkmgr_trans.2499076363
Short name	T220
Test name
Test status
Simulation time	15167344 ps
CPU time	0.78 seconds
Started	Mar 26 12:37:57 PM PDT 24
Finished	Mar 26 12:37:59 PM PDT 24
Peak memory	200500 kb
Host	smart-59848d09-9b81-4b5f-b741-f0c3fbfc0ce7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499076363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.2499076363
Directory	/workspace/12.clkmgr_trans/latest

Test location	/workspace/coverage/default/13.clkmgr_alert_test.2783465573
Short name	T292
Test name
Test status
Simulation time	23961504 ps
CPU time	0.73 seconds
Started	Mar 26 12:37:57 PM PDT 24
Finished	Mar 26 12:37:59 PM PDT 24
Peak memory	200604 kb
Host	smart-5bef2346-6730-46b1-8797-4a78e8230f35
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783465573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk mgr_alert_test.2783465573
Directory	/workspace/13.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.1049688505
Short name	T93
Test name
Test status
Simulation time	29504020 ps
CPU time	0.87 seconds
Started	Mar 26 12:37:57 PM PDT 24
Finished	Mar 26 12:37:59 PM PDT 24
Peak memory	200624 kb
Host	smart-9b29c929-a275-4a4c-93df-7b6f3bd6b6aa
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049688505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.1049688505
Directory	/workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_div_intersig_mubi.843655521
Short name	T851
Test name
Test status
Simulation time	39699358 ps
CPU time	0.91 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:37:59 PM PDT 24
Peak memory	200624 kb
Host	smart-b200e7f4-a6f1-4bd8-a15d-c7535a101caf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843655521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.clkmgr_div_intersig_mubi.843655521
Directory	/workspace/13.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_extclk.1487112179
Short name	T604
Test name
Test status
Simulation time	79412138 ps
CPU time	1.01 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:38:00 PM PDT 24
Peak memory	200624 kb
Host	smart-3d65f056-6de0-4b96-9357-0929543320f8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487112179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.1487112179
Directory	/workspace/13.clkmgr_extclk/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency.1537413899
Short name	T396
Test name
Test status
Simulation time	568727401 ps
CPU time	3.66 seconds
Started	Mar 26 12:37:56 PM PDT 24
Finished	Mar 26 12:38:00 PM PDT 24
Peak memory	200536 kb
Host	smart-3cb32dc7-f124-43cf-82fc-970b0f263dd5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537413899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.1537413899
Directory	/workspace/13.clkmgr_frequency/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency_timeout.3586685943
Short name	T222
Test name
Test status
Simulation time	281982174 ps
CPU time	1.55 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:38:01 PM PDT 24
Peak memory	200624 kb
Host	smart-b0dfe3c2-56f5-4165-ad0b-45d53fd5537a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586685943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t imeout.3586685943
Directory	/workspace/13.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/13.clkmgr_idle_intersig_mubi.3521570950
Short name	T335
Test name
Test status
Simulation time	33804283 ps
CPU time	0.79 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:37:59 PM PDT 24
Peak memory	200484 kb
Host	smart-019061b9-cb09-47c5-a90b-4d0b91213754
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521570950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.3521570950
Directory	/workspace/13.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.93672537
Short name	T517
Test name
Test status
Simulation time	64364687 ps
CPU time	0.94 seconds
Started	Mar 26 12:37:54 PM PDT 24
Finished	Mar 26 12:37:55 PM PDT 24
Peak memory	200560 kb
Host	smart-a99d0026-61fa-4cea-95bd-a92ea0bbae90
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93672537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_clk_byp_req_intersig_mubi.93672537
Directory	/workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.3658864578
Short name	T333
Test name
Test status
Simulation time	21985510 ps
CPU time	0.9 seconds
Started	Mar 26 12:37:54 PM PDT 24
Finished	Mar 26 12:37:55 PM PDT 24
Peak memory	200568 kb
Host	smart-c4293e9c-cc51-4e4e-9bc5-54c5b583ba2b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658864578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.clkmgr_lc_ctrl_intersig_mubi.3658864578
Directory	/workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_peri.4228403312
Short name	T51
Test name
Test status
Simulation time	21070155 ps
CPU time	0.82 seconds
Started	Mar 26 12:38:00 PM PDT 24
Finished	Mar 26 12:38:01 PM PDT 24
Peak memory	200500 kb
Host	smart-e9881632-0426-4b9f-9a2e-cb68a133bd28
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228403312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.4228403312
Directory	/workspace/13.clkmgr_peri/latest

Test location	/workspace/coverage/default/13.clkmgr_regwen.269268501
Short name	T419
Test name
Test status
Simulation time	707444457 ps
CPU time	3.41 seconds
Started	Mar 26 12:37:55 PM PDT 24
Finished	Mar 26 12:37:59 PM PDT 24
Peak memory	200960 kb
Host	smart-2f86e0e9-cb25-41a1-bd9b-07c6f34000fc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269268501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.269268501
Directory	/workspace/13.clkmgr_regwen/latest

Test location	/workspace/coverage/default/13.clkmgr_smoke.738385993
Short name	T724
Test name
Test status
Simulation time	22991116 ps
CPU time	0.91 seconds
Started	Mar 26 12:37:55 PM PDT 24
Finished	Mar 26 12:37:57 PM PDT 24
Peak memory	200568 kb
Host	smart-c993c1b7-8644-4202-90b8-b92406262429
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738385993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.738385993
Directory	/workspace/13.clkmgr_smoke/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all.3315163544
Short name	T735
Test name
Test status
Simulation time	3737521863 ps
CPU time	29.07 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:38:28 PM PDT 24
Peak memory	200812 kb
Host	smart-680d4cb5-a41b-4b4a-846c-69bf92ae93ee
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315163544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.3315163544
Directory	/workspace/13.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.2015584786
Short name	T708
Test name
Test status
Simulation time	10777745554 ps
CPU time	102.08 seconds
Started	Mar 26 12:38:00 PM PDT 24
Finished	Mar 26 12:39:43 PM PDT 24
Peak memory	213520 kb
Host	smart-96b683d6-cad7-41db-9a39-a29994116716
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2015584786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.2015584786
Directory	/workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.clkmgr_trans.1511165867
Short name	T232
Test name
Test status
Simulation time	20876003 ps
CPU time	0.83 seconds
Started	Mar 26 12:37:56 PM PDT 24
Finished	Mar 26 12:37:57 PM PDT 24
Peak memory	200596 kb
Host	smart-9bedb94b-5406-4479-bd58-0f1a01541167
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511165867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.1511165867
Directory	/workspace/13.clkmgr_trans/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.3664961704
Short name	T451
Test name
Test status
Simulation time	114821733 ps
CPU time	0.99 seconds
Started	Mar 26 12:37:57 PM PDT 24
Finished	Mar 26 12:37:58 PM PDT 24
Peak memory	200592 kb
Host	smart-5b787e5c-6856-47b5-8c38-c280c289e494
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664961704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.3664961704
Directory	/workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_status.3839677213
Short name	T793
Test name
Test status
Simulation time	16314052 ps
CPU time	0.72 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:38:00 PM PDT 24
Peak memory	199528 kb
Host	smart-0c9f46bf-4eb2-4132-8ecc-18b78e3196dd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839677213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.3839677213
Directory	/workspace/14.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/14.clkmgr_div_intersig_mubi.3811809411
Short name	T19
Test name
Test status
Simulation time	70394517 ps
CPU time	1 seconds
Started	Mar 26 12:37:59 PM PDT 24
Finished	Mar 26 12:38:00 PM PDT 24
Peak memory	199984 kb
Host	smart-76fbe904-e8ff-4a3d-8776-c503f5e0ca71
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811809411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.3811809411
Directory	/workspace/14.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_extclk.858316861
Short name	T26
Test name
Test status
Simulation time	23641138 ps
CPU time	0.85 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:37:59 PM PDT 24
Peak memory	200584 kb
Host	smart-a60aa7af-2cde-40c9-a7ec-a3e728b2d11e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858316861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.858316861
Directory	/workspace/14.clkmgr_extclk/latest

Test location	/workspace/coverage/default/14.clkmgr_frequency.682966264
Short name	T294
Test name
Test status
Simulation time	263271710 ps
CPU time	1.59 seconds
Started	Mar 26 12:38:03 PM PDT 24
Finished	Mar 26 12:38:06 PM PDT 24
Peak memory	200520 kb
Host	smart-53f14dd4-fed7-41ce-86d4-9d4ef89bdb62
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682966264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.682966264
Directory	/workspace/14.clkmgr_frequency/latest

Test location	/workspace/coverage/default/14.clkmgr_frequency_timeout.283403270
Short name	T221
Test name
Test status
Simulation time	383621140 ps
CPU time	2.37 seconds
Started	Mar 26 12:37:56 PM PDT 24
Finished	Mar 26 12:37:58 PM PDT 24
Peak memory	200608 kb
Host	smart-7d46aff7-5719-4f5e-b53b-1b35f9c77962
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283403270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_ti meout.283403270
Directory	/workspace/14.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/14.clkmgr_idle_intersig_mubi.295085139
Short name	T373
Test name
Test status
Simulation time	27209185 ps
CPU time	0.82 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:38:00 PM PDT 24
Peak memory	200456 kb
Host	smart-0c2ba5a9-2e48-4760-9feb-8301dae13dbe
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295085139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.clkmgr_idle_intersig_mubi.295085139
Directory	/workspace/14.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.2051751403
Short name	T55
Test name
Test status
Simulation time	16322199 ps
CPU time	0.78 seconds
Started	Mar 26 12:37:59 PM PDT 24
Finished	Mar 26 12:38:00 PM PDT 24
Peak memory	199932 kb
Host	smart-48d82e4a-40e8-40cb-ae82-1c080d7ee69f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051751403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.clkmgr_lc_clk_byp_req_intersig_mubi.2051751403
Directory	/workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.3931158311
Short name	T25
Test name
Test status
Simulation time	74276518 ps
CPU time	0.94 seconds
Started	Mar 26 12:37:57 PM PDT 24
Finished	Mar 26 12:37:59 PM PDT 24
Peak memory	200584 kb
Host	smart-1666ba13-5a85-4c79-92dc-04f8b7c25c3a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931158311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.clkmgr_lc_ctrl_intersig_mubi.3931158311
Directory	/workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_peri.3589029149
Short name	T660
Test name
Test status
Simulation time	32626111 ps
CPU time	0.85 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:37:59 PM PDT 24
Peak memory	200604 kb
Host	smart-b1a1232a-5060-4d77-adf4-8f245624e8b8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589029149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.3589029149
Directory	/workspace/14.clkmgr_peri/latest

Test location	/workspace/coverage/default/14.clkmgr_regwen.3259029990
Short name	T153
Test name
Test status
Simulation time	739765392 ps
CPU time	2.97 seconds
Started	Mar 26 12:37:58 PM PDT 24
Finished	Mar 26 12:38:02 PM PDT 24
Peak memory	200672 kb
Host	smart-6deed871-baad-4a3d-85c0-d3d9b0b102dd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259029990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.3259029990
Directory	/workspace/14.clkmgr_regwen/latest

Test location	/workspace/coverage/default/14.clkmgr_smoke.3756944810
Short name	T846
Test name
Test status
Simulation time	16655166 ps
CPU time	0.81 seconds
Started	Mar 26 12:38:04 PM PDT 24
Finished	Mar 26 12:38:05 PM PDT 24
Peak memory	200556 kb
Host	smart-89c4431a-fbdf-4de2-a0fb-96bf72680585
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756944810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.3756944810
Directory	/workspace/14.clkmgr_smoke/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all.501848026
Short name	T546
Test name
Test status
Simulation time	18215460964 ps
CPU time	74.22 seconds
Started	Mar 26 12:38:00 PM PDT 24
Finished	Mar 26 12:39:15 PM PDT 24
Peak memory	200804 kb
Host	smart-09d39cc5-cd70-4575-a589-efa92a93fe01
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501848026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.501848026
Directory	/workspace/14.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/14.clkmgr_trans.3653847646
Short name	T403
Test name
Test status
Simulation time	22387065 ps
CPU time	0.83 seconds
Started	Mar 26 12:37:57 PM PDT 24
Finished	Mar 26 12:37:58 PM PDT 24
Peak memory	200564 kb
Host	smart-b8b5f9e2-a1a3-4c93-9d94-3af1d72aec0a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653847646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.3653847646
Directory	/workspace/14.clkmgr_trans/latest

Test location	/workspace/coverage/default/15.clkmgr_alert_test.2306387150
Short name	T39
Test name
Test status
Simulation time	47175948 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:10 PM PDT 24
Finished	Mar 26 12:38:11 PM PDT 24
Peak memory	200636 kb
Host	smart-af578b99-c9e6-4022-9bf2-f4106fb91ed2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306387150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk mgr_alert_test.2306387150
Directory	/workspace/15.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.845210675
Short name	T641
Test name
Test status
Simulation time	26360347 ps
CPU time	0.89 seconds
Started	Mar 26 12:38:15 PM PDT 24
Finished	Mar 26 12:38:17 PM PDT 24
Peak memory	200536 kb
Host	smart-558b87f7-d5b7-4164-a006-561f93476539
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845210675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.845210675
Directory	/workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_status.2017659970
Short name	T470
Test name
Test status
Simulation time	34350886 ps
CPU time	0.74 seconds
Started	Mar 26 12:38:15 PM PDT 24
Finished	Mar 26 12:38:16 PM PDT 24
Peak memory	199460 kb
Host	smart-7060a6d2-6943-4cc4-b05a-d85de80fd499
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017659970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.2017659970
Directory	/workspace/15.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/15.clkmgr_div_intersig_mubi.1129060444
Short name	T175
Test name
Test status
Simulation time	21889489 ps
CPU time	0.84 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200636 kb
Host	smart-9162d599-7eb3-44ee-a5f9-99c8b0bff00c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129060444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_div_intersig_mubi.1129060444
Directory	/workspace/15.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_extclk.3952032905
Short name	T859
Test name
Test status
Simulation time	31144068 ps
CPU time	0.96 seconds
Started	Mar 26 12:38:08 PM PDT 24
Finished	Mar 26 12:38:10 PM PDT 24
Peak memory	200560 kb
Host	smart-46ac39b2-7e46-4c18-b396-3e8840a76996
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952032905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.3952032905
Directory	/workspace/15.clkmgr_extclk/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency.1249564905
Short name	T296
Test name
Test status
Simulation time	2600663429 ps
CPU time	11.27 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:23 PM PDT 24
Peak memory	200888 kb
Host	smart-de796179-306a-424f-aeaa-c77cb5d52742
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249564905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.1249564905
Directory	/workspace/15.clkmgr_frequency/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency_timeout.1320608586
Short name	T34
Test name
Test status
Simulation time	659056969 ps
CPU time	3.27 seconds
Started	Mar 26 12:38:08 PM PDT 24
Finished	Mar 26 12:38:12 PM PDT 24
Peak memory	200652 kb
Host	smart-badb98a8-4697-414c-bf18-c2ef93d1f360
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320608586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t imeout.1320608586
Directory	/workspace/15.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/15.clkmgr_idle_intersig_mubi.263710025
Short name	T198
Test name
Test status
Simulation time	17923236 ps
CPU time	0.76 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:11 PM PDT 24
Peak memory	200580 kb
Host	smart-739abed3-f526-461e-b7ed-95add08ab598
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263710025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.clkmgr_idle_intersig_mubi.263710025
Directory	/workspace/15.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.4002748112
Short name	T643
Test name
Test status
Simulation time	46422792 ps
CPU time	0.82 seconds
Started	Mar 26 12:38:51 PM PDT 24
Finished	Mar 26 12:38:52 PM PDT 24
Peak memory	200656 kb
Host	smart-62ed9b0f-2356-4acc-a1b7-3c60c72b6761
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002748112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_clk_byp_req_intersig_mubi.4002748112
Directory	/workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.3354039884
Short name	T437
Test name
Test status
Simulation time	23487513 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:15 PM PDT 24
Finished	Mar 26 12:38:16 PM PDT 24
Peak memory	200544 kb
Host	smart-c5bedf64-055f-4532-a8a1-98b0473ef284
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354039884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_ctrl_intersig_mubi.3354039884
Directory	/workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_peri.3233792676
Short name	T469
Test name
Test status
Simulation time	27314378 ps
CPU time	0.78 seconds
Started	Mar 26 12:38:13 PM PDT 24
Finished	Mar 26 12:38:14 PM PDT 24
Peak memory	200564 kb
Host	smart-03f78143-cb9b-47d0-be4f-fef123b09fb0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233792676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.3233792676
Directory	/workspace/15.clkmgr_peri/latest

Test location	/workspace/coverage/default/15.clkmgr_regwen.3609423344
Short name	T774
Test name
Test status
Simulation time	1215840899 ps
CPU time	6.9 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:19 PM PDT 24
Peak memory	200652 kb
Host	smart-3c794f39-aafb-45b9-bb1d-252b932bdda7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609423344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.3609423344
Directory	/workspace/15.clkmgr_regwen/latest

Test location	/workspace/coverage/default/15.clkmgr_smoke.1170800280
Short name	T378
Test name
Test status
Simulation time	38211159 ps
CPU time	0.98 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200644 kb
Host	smart-1249634e-739d-47ec-a52a-fb52bf1e0aa7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170800280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1170800280
Directory	/workspace/15.clkmgr_smoke/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all.2905482053
Short name	T522
Test name
Test status
Simulation time	183150505 ps
CPU time	1.74 seconds
Started	Mar 26 12:38:09 PM PDT 24
Finished	Mar 26 12:38:11 PM PDT 24
Peak memory	200580 kb
Host	smart-6493aba6-3aa0-410d-bf2a-17465edad120
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905482053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.2905482053
Directory	/workspace/15.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.3457747339
Short name	T401
Test name
Test status
Simulation time	24930094071 ps
CPU time	376.35 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:44:28 PM PDT 24
Peak memory	217072 kb
Host	smart-24626dea-a28b-47c2-bd67-4566fa8e4a63
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3457747339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.3457747339
Directory	/workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.clkmgr_trans.69139577
Short name	T553
Test name
Test status
Simulation time	28384898 ps
CPU time	1.1 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:12 PM PDT 24
Peak memory	200592 kb
Host	smart-9bb88e92-614a-4adf-945d-29d2ed450d78
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69139577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.69139577
Directory	/workspace/15.clkmgr_trans/latest

Test location	/workspace/coverage/default/16.clkmgr_alert_test.2155758735
Short name	T202
Test name
Test status
Simulation time	14395974 ps
CPU time	0.73 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200608 kb
Host	smart-2b19b6f9-20f4-40cc-9bf6-4b588fdebf5d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155758735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk mgr_alert_test.2155758735
Directory	/workspace/16.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.795409970
Short name	T574
Test name
Test status
Simulation time	87597694 ps
CPU time	1.1 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200584 kb
Host	smart-f351f7ef-8e72-4bd9-8e6c-09d2cbc353c3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795409970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.795409970
Directory	/workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_status.1588985136
Short name	T448
Test name
Test status
Simulation time	69028732 ps
CPU time	0.83 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	199496 kb
Host	smart-4e309c8c-29ac-4598-9899-903de9382f80
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588985136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.1588985136
Directory	/workspace/16.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/16.clkmgr_div_intersig_mubi.20682563
Short name	T370
Test name
Test status
Simulation time	49278420 ps
CPU time	0.98 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200628 kb
Host	smart-2a6b9b5e-d240-4979-9bb4-7e1e43b1163e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20682563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .clkmgr_div_intersig_mubi.20682563
Directory	/workspace/16.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_extclk.2144063761
Short name	T236
Test name
Test status
Simulation time	69155859 ps
CPU time	0.96 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200628 kb
Host	smart-7e3dce29-bbd8-4b87-ad22-971812d82f08
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144063761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.2144063761
Directory	/workspace/16.clkmgr_extclk/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency_timeout.1731371900
Short name	T359
Test name
Test status
Simulation time	1129431915 ps
CPU time	5.06 seconds
Started	Mar 26 12:38:09 PM PDT 24
Finished	Mar 26 12:38:14 PM PDT 24
Peak memory	200552 kb
Host	smart-b621f737-7229-4a4b-b1ab-db3e3c06580b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731371900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t imeout.1731371900
Directory	/workspace/16.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/16.clkmgr_idle_intersig_mubi.4254863730
Short name	T18
Test name
Test status
Simulation time	18948820 ps
CPU time	0.8 seconds
Started	Mar 26 12:38:15 PM PDT 24
Finished	Mar 26 12:38:16 PM PDT 24
Peak memory	200524 kb
Host	smart-0bcd722c-6e82-42d1-bed2-d4272b2a27ca
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254863730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.4254863730
Directory	/workspace/16.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.1665635361
Short name	T577
Test name
Test status
Simulation time	27404030 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:06 PM PDT 24
Finished	Mar 26 12:38:07 PM PDT 24
Peak memory	200648 kb
Host	smart-152eab05-8819-4664-b280-ef404c1603c9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665635361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.clkmgr_lc_clk_byp_req_intersig_mubi.1665635361
Directory	/workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.443220721
Short name	T298
Test name
Test status
Simulation time	24163658 ps
CPU time	0.86 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200588 kb
Host	smart-2f191512-ffe0-4c89-a4b4-30775a715d06
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443220721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.clkmgr_lc_ctrl_intersig_mubi.443220721
Directory	/workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_peri.1364230260
Short name	T760
Test name
Test status
Simulation time	12547378 ps
CPU time	0.73 seconds
Started	Mar 26 12:38:10 PM PDT 24
Finished	Mar 26 12:38:10 PM PDT 24
Peak memory	200552 kb
Host	smart-f419fb5b-98e1-4187-a854-61488cce737d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364230260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.1364230260
Directory	/workspace/16.clkmgr_peri/latest

Test location	/workspace/coverage/default/16.clkmgr_regwen.331222841
Short name	T458
Test name
Test status
Simulation time	963776623 ps
CPU time	3.83 seconds
Started	Mar 26 12:38:09 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200688 kb
Host	smart-a0e5b827-6bf0-4704-af45-a067c31b1207
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331222841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.331222841
Directory	/workspace/16.clkmgr_regwen/latest

Test location	/workspace/coverage/default/16.clkmgr_smoke.2760352482
Short name	T147
Test name
Test status
Simulation time	75215548 ps
CPU time	0.99 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200512 kb
Host	smart-34e1e978-5ce5-43a1-9dab-9f199a08f33e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760352482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.2760352482
Directory	/workspace/16.clkmgr_smoke/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all.1849262993
Short name	T480
Test name
Test status
Simulation time	5396737652 ps
CPU time	39.27 seconds
Started	Mar 26 12:38:08 PM PDT 24
Finished	Mar 26 12:38:48 PM PDT 24
Peak memory	200852 kb
Host	smart-229caf7d-0828-4988-8a31-1687b44b5038
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849262993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.1849262993
Directory	/workspace/16.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.3791234851
Short name	T729
Test name
Test status
Simulation time	64746149786 ps
CPU time	495.45 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:46:26 PM PDT 24
Peak memory	209204 kb
Host	smart-67c92e1e-aff7-4372-a2af-08163ce796bb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3791234851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.3791234851
Directory	/workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.clkmgr_trans.2903226037
Short name	T355
Test name
Test status
Simulation time	102035724 ps
CPU time	1.14 seconds
Started	Mar 26 12:38:08 PM PDT 24
Finished	Mar 26 12:38:09 PM PDT 24
Peak memory	200548 kb
Host	smart-b2ff46cc-90f2-4c9a-981c-db6873f19353
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903226037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.2903226037
Directory	/workspace/16.clkmgr_trans/latest

Test location	/workspace/coverage/default/17.clkmgr_alert_test.3956085010
Short name	T576
Test name
Test status
Simulation time	22289398 ps
CPU time	0.86 seconds
Started	Mar 26 12:38:14 PM PDT 24
Finished	Mar 26 12:38:15 PM PDT 24
Peak memory	200576 kb
Host	smart-aff04120-fc14-43ab-918a-c4fe40d80c61
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956085010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk mgr_alert_test.3956085010
Directory	/workspace/17.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.2232600089
Short name	T91
Test name
Test status
Simulation time	30923629 ps
CPU time	0.84 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200628 kb
Host	smart-0c76c40d-1f16-4245-9057-b3c6f9f050dd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232600089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.2232600089
Directory	/workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_status.4073268361
Short name	T484
Test name
Test status
Simulation time	13825489 ps
CPU time	0.73 seconds
Started	Mar 26 12:38:10 PM PDT 24
Finished	Mar 26 12:38:10 PM PDT 24
Peak memory	199580 kb
Host	smart-a7b65a69-38e3-47ce-bd33-780ca5af567c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073268361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.4073268361
Directory	/workspace/17.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/17.clkmgr_div_intersig_mubi.3472434538
Short name	T525
Test name
Test status
Simulation time	28747505 ps
CPU time	0.93 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200580 kb
Host	smart-6a677338-e8df-4041-8d99-3226b3b7fb7a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472434538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.3472434538
Directory	/workspace/17.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_extclk.836596302
Short name	T348
Test name
Test status
Simulation time	17536160 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:14 PM PDT 24
Finished	Mar 26 12:38:14 PM PDT 24
Peak memory	200548 kb
Host	smart-154f1adb-0ef1-4e6a-a575-30e286560454
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836596302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.836596302
Directory	/workspace/17.clkmgr_extclk/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency.623424727
Short name	T734
Test name
Test status
Simulation time	571398171 ps
CPU time	3.7 seconds
Started	Mar 26 12:38:10 PM PDT 24
Finished	Mar 26 12:38:14 PM PDT 24
Peak memory	200584 kb
Host	smart-41544e4d-d672-4dfa-977a-dff69a5d23a8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623424727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.623424727
Directory	/workspace/17.clkmgr_frequency/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency_timeout.493754654
Short name	T6
Test name
Test status
Simulation time	1098088789 ps
CPU time	7.6 seconds
Started	Mar 26 12:38:09 PM PDT 24
Finished	Mar 26 12:38:17 PM PDT 24
Peak memory	200628 kb
Host	smart-c39e8d11-0887-47b5-889e-d0e4c98d1e15
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493754654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_ti meout.493754654
Directory	/workspace/17.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/17.clkmgr_idle_intersig_mubi.1225247744
Short name	T196
Test name
Test status
Simulation time	30956676 ps
CPU time	0.87 seconds
Started	Mar 26 12:38:08 PM PDT 24
Finished	Mar 26 12:38:09 PM PDT 24
Peak memory	200568 kb
Host	smart-271de1f7-6e52-4df6-a15a-85eaf15b8429
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225247744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.1225247744
Directory	/workspace/17.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.498362381
Short name	T505
Test name
Test status
Simulation time	45266159 ps
CPU time	0.87 seconds
Started	Mar 26 12:38:10 PM PDT 24
Finished	Mar 26 12:38:11 PM PDT 24
Peak memory	200572 kb
Host	smart-0b3667c4-a1db-43e6-9c64-67037d4b80b5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498362381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.clkmgr_lc_clk_byp_req_intersig_mubi.498362381
Directory	/workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.2980268359
Short name	T393
Test name
Test status
Simulation time	19686419 ps
CPU time	0.82 seconds
Started	Mar 26 12:38:09 PM PDT 24
Finished	Mar 26 12:38:10 PM PDT 24
Peak memory	200648 kb
Host	smart-fa1a3fc6-10d7-41c1-85a3-b9a3ed1e90e4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980268359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 17.clkmgr_lc_ctrl_intersig_mubi.2980268359
Directory	/workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_peri.2637666391
Short name	T489
Test name
Test status
Simulation time	36712211 ps
CPU time	0.8 seconds
Started	Mar 26 12:38:10 PM PDT 24
Finished	Mar 26 12:38:11 PM PDT 24
Peak memory	200560 kb
Host	smart-c04f4e59-de6f-4051-8217-6ee312a5f2ef
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637666391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.2637666391
Directory	/workspace/17.clkmgr_peri/latest

Test location	/workspace/coverage/default/17.clkmgr_regwen.2550279884
Short name	T603
Test name
Test status
Simulation time	829296173 ps
CPU time	3.44 seconds
Started	Mar 26 12:38:10 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200672 kb
Host	smart-54e3e894-fcfa-42bd-8642-5d522f6cae73
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550279884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.2550279884
Directory	/workspace/17.clkmgr_regwen/latest

Test location	/workspace/coverage/default/17.clkmgr_smoke.1374569251
Short name	T665
Test name
Test status
Simulation time	68978014 ps
CPU time	0.95 seconds
Started	Mar 26 12:38:10 PM PDT 24
Finished	Mar 26 12:38:11 PM PDT 24
Peak memory	200604 kb
Host	smart-647a168b-8858-4287-95b3-e2a6b87da510
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374569251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.1374569251
Directory	/workspace/17.clkmgr_smoke/latest

Test location	/workspace/coverage/default/17.clkmgr_stress_all.2797789244
Short name	T523
Test name
Test status
Simulation time	5962559826 ps
CPU time	40.4 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:52 PM PDT 24
Peak memory	200832 kb
Host	smart-dea0bd45-b31a-4c40-90fa-66f90a06979f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797789244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.2797789244
Directory	/workspace/17.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.2366697431
Short name	T70
Test name
Test status
Simulation time	26450648723 ps
CPU time	471.94 seconds
Started	Mar 26 12:38:14 PM PDT 24
Finished	Mar 26 12:46:06 PM PDT 24
Peak memory	209112 kb
Host	smart-66ac5aed-2faf-4961-b038-151121323a82
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2366697431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.2366697431
Directory	/workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.clkmgr_trans.3965781929
Short name	T76
Test name
Test status
Simulation time	38371362 ps
CPU time	0.89 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200556 kb
Host	smart-26018ff3-36d8-4c43-9392-8ecb3e0c0f27
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965781929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.3965781929
Directory	/workspace/17.clkmgr_trans/latest

Test location	/workspace/coverage/default/18.clkmgr_alert_test.3095456144
Short name	T264
Test name
Test status
Simulation time	17241474 ps
CPU time	0.76 seconds
Started	Mar 26 12:38:08 PM PDT 24
Finished	Mar 26 12:38:08 PM PDT 24
Peak memory	200620 kb
Host	smart-34f26b10-4d2b-4e7d-b5ce-c83a12d1f34a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095456144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk mgr_alert_test.3095456144
Directory	/workspace/18.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.3360280090
Short name	T353
Test name
Test status
Simulation time	75259244 ps
CPU time	1.01 seconds
Started	Mar 26 12:38:13 PM PDT 24
Finished	Mar 26 12:38:15 PM PDT 24
Peak memory	200548 kb
Host	smart-cb20e31a-4772-472b-93ff-72d9e833b9ff
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360280090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.3360280090
Directory	/workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_status.3235038805
Short name	T686
Test name
Test status
Simulation time	27805955 ps
CPU time	0.8 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200536 kb
Host	smart-50f67d4c-4c98-4c04-810d-4a0923f41291
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235038805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.3235038805
Directory	/workspace/18.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/18.clkmgr_div_intersig_mubi.3819332953
Short name	T652
Test name
Test status
Simulation time	53075780 ps
CPU time	0.95 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200628 kb
Host	smart-163ca61e-9302-40a3-9c60-2aff910d5527
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819332953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_div_intersig_mubi.3819332953
Directory	/workspace/18.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_extclk.44242625
Short name	T835
Test name
Test status
Simulation time	41991077 ps
CPU time	0.96 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200580 kb
Host	smart-fa4ac8d2-c15f-466b-b152-3f7f22d29c46
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44242625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.44242625
Directory	/workspace/18.clkmgr_extclk/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency.182510599
Short name	T36
Test name
Test status
Simulation time	559022072 ps
CPU time	3.63 seconds
Started	Mar 26 12:38:14 PM PDT 24
Finished	Mar 26 12:38:18 PM PDT 24
Peak memory	200576 kb
Host	smart-38c1d673-4121-4827-beae-647d331f1099
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182510599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.182510599
Directory	/workspace/18.clkmgr_frequency/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency_timeout.1945032424
Short name	T781
Test name
Test status
Simulation time	2364098510 ps
CPU time	9.76 seconds
Started	Mar 26 12:38:09 PM PDT 24
Finished	Mar 26 12:38:19 PM PDT 24
Peak memory	200880 kb
Host	smart-a9c20056-a081-4aca-a177-df7ec9219e4f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945032424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t imeout.1945032424
Directory	/workspace/18.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/18.clkmgr_idle_intersig_mubi.4232763547
Short name	T707
Test name
Test status
Simulation time	56347924 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200500 kb
Host	smart-2b8f07a4-d72c-4b97-8541-9705792a4910
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232763547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.4232763547
Directory	/workspace/18.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.377406645
Short name	T771
Test name
Test status
Simulation time	14200248 ps
CPU time	0.72 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200552 kb
Host	smart-7806b889-3168-43f5-bb1f-0745102704db
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377406645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.clkmgr_lc_clk_byp_req_intersig_mubi.377406645
Directory	/workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.4050798136
Short name	T369
Test name
Test status
Simulation time	20562429 ps
CPU time	0.8 seconds
Started	Mar 26 12:38:08 PM PDT 24
Finished	Mar 26 12:38:09 PM PDT 24
Peak memory	200544 kb
Host	smart-6e7603df-e173-48a4-9cef-e58ffaf2e443
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050798136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 18.clkmgr_lc_ctrl_intersig_mubi.4050798136
Directory	/workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_peri.1284405894
Short name	T782
Test name
Test status
Simulation time	20040079 ps
CPU time	0.78 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200520 kb
Host	smart-71ab031e-e832-4422-8d62-ba3930eb08ba
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284405894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.1284405894
Directory	/workspace/18.clkmgr_peri/latest

Test location	/workspace/coverage/default/18.clkmgr_regwen.2495060996
Short name	T367
Test name
Test status
Simulation time	975960010 ps
CPU time	3.48 seconds
Started	Mar 26 12:38:08 PM PDT 24
Finished	Mar 26 12:38:12 PM PDT 24
Peak memory	200600 kb
Host	smart-ba2e4782-cf94-4747-8437-3fb7b2752a9b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495060996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.2495060996
Directory	/workspace/18.clkmgr_regwen/latest

Test location	/workspace/coverage/default/18.clkmgr_smoke.519771515
Short name	T509
Test name
Test status
Simulation time	20532367 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:14 PM PDT 24
Finished	Mar 26 12:38:15 PM PDT 24
Peak memory	200572 kb
Host	smart-24ea4421-03d7-4394-8f5b-c7a857324cdc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519771515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.519771515
Directory	/workspace/18.clkmgr_smoke/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all.763853831
Short name	T798
Test name
Test status
Simulation time	4212658077 ps
CPU time	22.44 seconds
Started	Mar 26 12:38:08 PM PDT 24
Finished	Mar 26 12:38:31 PM PDT 24
Peak memory	200884 kb
Host	smart-70a15f68-698d-4ce8-91d4-5e4ddb330ab3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763853831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.763853831
Directory	/workspace/18.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.3480392960
Short name	T71
Test name
Test status
Simulation time	39695975279 ps
CPU time	689.85 seconds
Started	Mar 26 12:38:09 PM PDT 24
Finished	Mar 26 12:49:39 PM PDT 24
Peak memory	217376 kb
Host	smart-484969ba-4a3e-4f1a-bf84-97d7cb0a0b53
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3480392960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.3480392960
Directory	/workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.clkmgr_trans.2750715513
Short name	T709
Test name
Test status
Simulation time	94288562 ps
CPU time	0.95 seconds
Started	Mar 26 12:38:10 PM PDT 24
Finished	Mar 26 12:38:11 PM PDT 24
Peak memory	200556 kb
Host	smart-0707ed13-1f42-4261-9cc4-33208995536e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750715513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.2750715513
Directory	/workspace/18.clkmgr_trans/latest

Test location	/workspace/coverage/default/19.clkmgr_alert_test.4121310116
Short name	T331
Test name
Test status
Simulation time	32167180 ps
CPU time	0.79 seconds
Started	Mar 26 12:38:28 PM PDT 24
Finished	Mar 26 12:38:28 PM PDT 24
Peak memory	200616 kb
Host	smart-5f075026-2868-4792-84a5-e224e9988275
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121310116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk mgr_alert_test.4121310116
Directory	/workspace/19.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.1255518932
Short name	T187
Test name
Test status
Simulation time	24216035 ps
CPU time	0.87 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:25 PM PDT 24
Peak memory	200628 kb
Host	smart-64f5c320-9a25-49e9-b001-7029e46ee941
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255518932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.1255518932
Directory	/workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_status.1690779431
Short name	T803
Test name
Test status
Simulation time	26596650 ps
CPU time	0.74 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:11 PM PDT 24
Peak memory	199508 kb
Host	smart-3b7ae926-e393-4ed5-98ba-a8fce7157d07
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690779431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.1690779431
Directory	/workspace/19.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/19.clkmgr_div_intersig_mubi.3483758482
Short name	T271
Test name
Test status
Simulation time	168624609 ps
CPU time	1.28 seconds
Started	Mar 26 12:38:27 PM PDT 24
Finished	Mar 26 12:38:28 PM PDT 24
Peak memory	200552 kb
Host	smart-1c9b51a4-3d53-492d-b399-277303af511b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483758482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.3483758482
Directory	/workspace/19.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_extclk.3388608286
Short name	T649
Test name
Test status
Simulation time	30591945 ps
CPU time	0.91 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200564 kb
Host	smart-a6fa9822-8102-4d52-91c2-3cf5e599a571
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388608286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.3388608286
Directory	/workspace/19.clkmgr_extclk/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency.1424838911
Short name	T811
Test name
Test status
Simulation time	1367708506 ps
CPU time	6.1 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:19 PM PDT 24
Peak memory	200576 kb
Host	smart-5745f041-d876-4739-a85c-04138a837a45
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424838911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.1424838911
Directory	/workspace/19.clkmgr_frequency/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency_timeout.1602589567
Short name	T790
Test name
Test status
Simulation time	144612215 ps
CPU time	1.39 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200616 kb
Host	smart-0dd48b40-30d8-479d-8155-3ee925618fb5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602589567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t imeout.1602589567
Directory	/workspace/19.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/19.clkmgr_idle_intersig_mubi.957781048
Short name	T743
Test name
Test status
Simulation time	119268640 ps
CPU time	1.28 seconds
Started	Mar 26 12:38:13 PM PDT 24
Finished	Mar 26 12:38:15 PM PDT 24
Peak memory	200476 kb
Host	smart-103b0872-0d5a-4b63-b0a4-66b09f97553b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957781048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.clkmgr_idle_intersig_mubi.957781048
Directory	/workspace/19.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2251463724
Short name	T787
Test name
Test status
Simulation time	90342136 ps
CPU time	1.09 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:14 PM PDT 24
Peak memory	200588 kb
Host	smart-410abe7d-8a99-4192-855d-ef431f2539a9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251463724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.clkmgr_lc_clk_byp_req_intersig_mubi.2251463724
Directory	/workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.2568157564
Short name	T266
Test name
Test status
Simulation time	80526143 ps
CPU time	1.06 seconds
Started	Mar 26 12:38:11 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200656 kb
Host	smart-d6b1d7b5-b3bc-4685-a562-b8ba9fdceef6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568157564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.clkmgr_lc_ctrl_intersig_mubi.2568157564
Directory	/workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_peri.123532632
Short name	T770
Test name
Test status
Simulation time	29166254 ps
CPU time	0.75 seconds
Started	Mar 26 12:38:12 PM PDT 24
Finished	Mar 26 12:38:13 PM PDT 24
Peak memory	200608 kb
Host	smart-f85fcb26-f0ae-452a-a5fa-acecfa35082e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123532632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.123532632
Directory	/workspace/19.clkmgr_peri/latest

Test location	/workspace/coverage/default/19.clkmgr_regwen.363834971
Short name	T274
Test name
Test status
Simulation time	472778669 ps
CPU time	2.56 seconds
Started	Mar 26 12:38:19 PM PDT 24
Finished	Mar 26 12:38:22 PM PDT 24
Peak memory	200536 kb
Host	smart-5a8113b2-c14f-41d3-8db6-ab4ef1b49eb2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363834971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.363834971
Directory	/workspace/19.clkmgr_regwen/latest

Test location	/workspace/coverage/default/19.clkmgr_smoke.3825736102
Short name	T692
Test name
Test status
Simulation time	23556973 ps
CPU time	0.81 seconds
Started	Mar 26 12:38:14 PM PDT 24
Finished	Mar 26 12:38:15 PM PDT 24
Peak memory	200572 kb
Host	smart-54251b89-8696-4b62-9059-e9b7ead9d1fe
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825736102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.3825736102
Directory	/workspace/19.clkmgr_smoke/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all.195541546
Short name	T682
Test name
Test status
Simulation time	6530559482 ps
CPU time	19.96 seconds
Started	Mar 26 12:38:20 PM PDT 24
Finished	Mar 26 12:38:40 PM PDT 24
Peak memory	200840 kb
Host	smart-8a12bb13-6c48-4ce3-94b8-e927e3afb13d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195541546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.195541546
Directory	/workspace/19.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.3535925765
Short name	T519
Test name
Test status
Simulation time	22830036700 ps
CPU time	291.6 seconds
Started	Mar 26 12:38:20 PM PDT 24
Finished	Mar 26 12:43:12 PM PDT 24
Peak memory	209208 kb
Host	smart-8000f221-04bc-459a-986d-bee1f0630fe8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3535925765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.3535925765
Directory	/workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.clkmgr_trans.2354458268
Short name	T472
Test name
Test status
Simulation time	23290410 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:10 PM PDT 24
Finished	Mar 26 12:38:11 PM PDT 24
Peak memory	200568 kb
Host	smart-0a38431d-085f-4e86-a6dd-9b418b876c69
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354458268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.2354458268
Directory	/workspace/19.clkmgr_trans/latest

Test location	/workspace/coverage/default/2.clkmgr_alert_test.3548010742
Short name	T241
Test name
Test status
Simulation time	12513174 ps
CPU time	0.72 seconds
Started	Mar 26 12:37:29 PM PDT 24
Finished	Mar 26 12:37:30 PM PDT 24
Peak memory	200616 kb
Host	smart-62f12a17-4e0e-40da-92c6-5de1bdbe3651
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548010742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm gr_alert_test.3548010742
Directory	/workspace/2.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.120124520
Short name	T737
Test name
Test status
Simulation time	27485383 ps
CPU time	0.84 seconds
Started	Mar 26 12:37:30 PM PDT 24
Finished	Mar 26 12:37:31 PM PDT 24
Peak memory	200564 kb
Host	smart-f5eda314-27b0-4e85-be20-1a5dd301fda7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120124520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.120124520
Directory	/workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_status.3219725315
Short name	T440
Test name
Test status
Simulation time	34825826 ps
CPU time	0.72 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200464 kb
Host	smart-9c33b4ac-dee7-4389-a654-cd66c23b0e04
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219725315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.3219725315
Directory	/workspace/2.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/2.clkmgr_div_intersig_mubi.2270812440
Short name	T178
Test name
Test status
Simulation time	19824298 ps
CPU time	0.8 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200576 kb
Host	smart-9a6519e7-a589-4980-8a2e-42e29a44c6ba
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270812440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.2270812440
Directory	/workspace/2.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_extclk.319044977
Short name	T334
Test name
Test status
Simulation time	22287819 ps
CPU time	0.84 seconds
Started	Mar 26 12:37:28 PM PDT 24
Finished	Mar 26 12:37:29 PM PDT 24
Peak memory	200540 kb
Host	smart-cb19f62c-f70a-4dce-a74f-ee62b2913c3a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319044977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.319044977
Directory	/workspace/2.clkmgr_extclk/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency.419946173
Short name	T610
Test name
Test status
Simulation time	201829787 ps
CPU time	2.15 seconds
Started	Mar 26 12:37:31 PM PDT 24
Finished	Mar 26 12:37:34 PM PDT 24
Peak memory	200548 kb
Host	smart-771d745c-1081-4b43-931d-ff5bf5dc471f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419946173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.419946173
Directory	/workspace/2.clkmgr_frequency/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency_timeout.1528681622
Short name	T837
Test name
Test status
Simulation time	142380465 ps
CPU time	1.4 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:34 PM PDT 24
Peak memory	200640 kb
Host	smart-8afc5949-8c53-4e99-844e-97dade2602aa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528681622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti meout.1528681622
Directory	/workspace/2.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/2.clkmgr_idle_intersig_mubi.3888307169
Short name	T765
Test name
Test status
Simulation time	79886765 ps
CPU time	1.06 seconds
Started	Mar 26 12:37:29 PM PDT 24
Finished	Mar 26 12:37:30 PM PDT 24
Peak memory	200592 kb
Host	smart-e1852d09-bc12-4ec3-874a-bccb42524040
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888307169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.3888307169
Directory	/workspace/2.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.1703139804
Short name	T229
Test name
Test status
Simulation time	64613609 ps
CPU time	0.92 seconds
Started	Mar 26 12:37:30 PM PDT 24
Finished	Mar 26 12:37:31 PM PDT 24
Peak memory	200572 kb
Host	smart-5cdc417d-fbab-4211-af53-fd95c15c14b0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703139804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_clk_byp_req_intersig_mubi.1703139804
Directory	/workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.3783161381
Short name	T642
Test name
Test status
Simulation time	23093903 ps
CPU time	0.75 seconds
Started	Mar 26 12:37:31 PM PDT 24
Finished	Mar 26 12:37:32 PM PDT 24
Peak memory	200576 kb
Host	smart-d78734d5-f98b-48f8-b916-2d7fbc56b5bb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783161381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_ctrl_intersig_mubi.3783161381
Directory	/workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_peri.2641235459
Short name	T524
Test name
Test status
Simulation time	20531422 ps
CPU time	0.8 seconds
Started	Mar 26 12:37:39 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200608 kb
Host	smart-3c5eb391-8b38-4633-9e74-f02d54f85601
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641235459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2641235459
Directory	/workspace/2.clkmgr_peri/latest

Test location	/workspace/coverage/default/2.clkmgr_regwen.3847492052
Short name	T492
Test name
Test status
Simulation time	719110973 ps
CPU time	3.14 seconds
Started	Mar 26 12:37:29 PM PDT 24
Finished	Mar 26 12:37:32 PM PDT 24
Peak memory	200640 kb
Host	smart-f5fdf61f-255a-4d48-8e50-a99b7d7b20c4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847492052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.3847492052
Directory	/workspace/2.clkmgr_regwen/latest

Test location	/workspace/coverage/default/2.clkmgr_sec_cm.112145056
Short name	T50
Test name
Test status
Simulation time	213929564 ps
CPU time	1.99 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:34 PM PDT 24
Peak memory	215880 kb
Host	smart-847edf9b-a7d1-4fd2-a4ac-f928a58876c6
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112145056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr _sec_cm.112145056
Directory	/workspace/2.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/2.clkmgr_smoke.2556179022
Short name	T584
Test name
Test status
Simulation time	44394105 ps
CPU time	0.95 seconds
Started	Mar 26 12:37:28 PM PDT 24
Finished	Mar 26 12:37:29 PM PDT 24
Peak memory	200548 kb
Host	smart-25e99903-838e-40c6-9c55-6309397affcc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556179022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.2556179022
Directory	/workspace/2.clkmgr_smoke/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all.3035703241
Short name	T379
Test name
Test status
Simulation time	5885601582 ps
CPU time	38.71 seconds
Started	Mar 26 12:37:34 PM PDT 24
Finished	Mar 26 12:38:14 PM PDT 24
Peak memory	200796 kb
Host	smart-bf44d91f-bab2-4684-91fc-f8f12227b110
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035703241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.3035703241
Directory	/workspace/2.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.2450397420
Short name	T805
Test name
Test status
Simulation time	35581893142 ps
CPU time	218.91 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:41:11 PM PDT 24
Peak memory	209160 kb
Host	smart-95068eb3-99f5-43c9-abad-ea3e90cf54d9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2450397420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.2450397420
Directory	/workspace/2.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.clkmgr_trans.2933234542
Short name	T453
Test name
Test status
Simulation time	50770543 ps
CPU time	1.06 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200544 kb
Host	smart-1069f518-c04c-4b59-b112-e0ca364ddeec
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933234542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.2933234542
Directory	/workspace/2.clkmgr_trans/latest

Test location	/workspace/coverage/default/20.clkmgr_alert_test.3106459633
Short name	T557
Test name
Test status
Simulation time	18122720 ps
CPU time	0.78 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200608 kb
Host	smart-3cb8f41e-2731-4cc7-9da0-392deb20976a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106459633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk mgr_alert_test.3106459633
Directory	/workspace/20.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3353997385
Short name	T648
Test name
Test status
Simulation time	28715249 ps
CPU time	0.82 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:24 PM PDT 24
Peak memory	200592 kb
Host	smart-625d8674-ef89-447d-80d7-4f1b237c0de6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353997385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.3353997385
Directory	/workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_status.3483561696
Short name	T43
Test name
Test status
Simulation time	17280928 ps
CPU time	0.76 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:24 PM PDT 24
Peak memory	200564 kb
Host	smart-f254e0f9-c331-40aa-86a8-47b3ac685e08
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483561696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.3483561696
Directory	/workspace/20.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/20.clkmgr_div_intersig_mubi.1210896103
Short name	T285
Test name
Test status
Simulation time	32338079 ps
CPU time	0.81 seconds
Started	Mar 26 12:38:20 PM PDT 24
Finished	Mar 26 12:38:20 PM PDT 24
Peak memory	200588 kb
Host	smart-e9f21bcb-9eca-4572-b9ec-957c2197113c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210896103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.1210896103
Directory	/workspace/20.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_extclk.3968615253
Short name	T535
Test name
Test status
Simulation time	21342117 ps
CPU time	0.75 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:25 PM PDT 24
Peak memory	200464 kb
Host	smart-cdde2b8f-b2a8-48ab-a261-72e0b9666637
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968615253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.3968615253
Directory	/workspace/20.clkmgr_extclk/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency.2594028465
Short name	T740
Test name
Test status
Simulation time	1999770162 ps
CPU time	15.95 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:40 PM PDT 24
Peak memory	200544 kb
Host	smart-23bee1f9-9073-49fc-80d3-ac6a9cf87e1a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594028465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.2594028465
Directory	/workspace/20.clkmgr_frequency/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency_timeout.1584356983
Short name	T594
Test name
Test status
Simulation time	1936780889 ps
CPU time	13.63 seconds
Started	Mar 26 12:38:21 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200668 kb
Host	smart-e3af1dae-b98b-40b6-bb37-069c0c0f31ec
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584356983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t imeout.1584356983
Directory	/workspace/20.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/20.clkmgr_idle_intersig_mubi.867873418
Short name	T217
Test name
Test status
Simulation time	54010524 ps
CPU time	0.83 seconds
Started	Mar 26 12:38:20 PM PDT 24
Finished	Mar 26 12:38:21 PM PDT 24
Peak memory	200560 kb
Host	smart-6706145a-d850-45b3-9f0f-f72550835210
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867873418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.clkmgr_idle_intersig_mubi.867873418
Directory	/workspace/20.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.803572188
Short name	T193
Test name
Test status
Simulation time	15984639 ps
CPU time	0.75 seconds
Started	Mar 26 12:38:20 PM PDT 24
Finished	Mar 26 12:38:20 PM PDT 24
Peak memory	200588 kb
Host	smart-c4e551b9-c300-4211-baa6-06b17dbdaa0f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803572188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.clkmgr_lc_clk_byp_req_intersig_mubi.803572188
Directory	/workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.3188380404
Short name	T516
Test name
Test status
Simulation time	38872247 ps
CPU time	0.78 seconds
Started	Mar 26 12:38:28 PM PDT 24
Finished	Mar 26 12:38:28 PM PDT 24
Peak memory	200564 kb
Host	smart-115907df-2168-461a-9a21-fd9dcecd1f15
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188380404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_ctrl_intersig_mubi.3188380404
Directory	/workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_peri.427061696
Short name	T732
Test name
Test status
Simulation time	50898571 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:21 PM PDT 24
Finished	Mar 26 12:38:22 PM PDT 24
Peak memory	200552 kb
Host	smart-a0a36c40-418d-4b60-9271-c9df9443eaa3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427061696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.427061696
Directory	/workspace/20.clkmgr_peri/latest

Test location	/workspace/coverage/default/20.clkmgr_regwen.3131123936
Short name	T704
Test name
Test status
Simulation time	1239078172 ps
CPU time	4.03 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200640 kb
Host	smart-fcd3356a-05e1-438c-8f44-0ff625be6415
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131123936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.3131123936
Directory	/workspace/20.clkmgr_regwen/latest

Test location	/workspace/coverage/default/20.clkmgr_smoke.998710762
Short name	T669
Test name
Test status
Simulation time	47192728 ps
CPU time	0.9 seconds
Started	Mar 26 12:38:22 PM PDT 24
Finished	Mar 26 12:38:23 PM PDT 24
Peak memory	200588 kb
Host	smart-b9e748d6-49a3-4933-91c8-81757773fd90
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998710762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.998710762
Directory	/workspace/20.clkmgr_smoke/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all.2193184209
Short name	T58
Test name
Test status
Simulation time	10729136077 ps
CPU time	75.88 seconds
Started	Mar 26 12:38:22 PM PDT 24
Finished	Mar 26 12:39:38 PM PDT 24
Peak memory	200808 kb
Host	smart-e6704eea-c6cd-442e-9ad0-fdfc20e58921
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193184209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.2193184209
Directory	/workspace/20.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.715900282
Short name	T756
Test name
Test status
Simulation time	219939036982 ps
CPU time	1139.31 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:57:23 PM PDT 24
Peak memory	213144 kb
Host	smart-338af392-bf4c-403d-9e0b-5b6aeb35b3ee
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=715900282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.715900282
Directory	/workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.clkmgr_trans.737604342
Short name	T179
Test name
Test status
Simulation time	50027338 ps
CPU time	0.99 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:24 PM PDT 24
Peak memory	200556 kb
Host	smart-a6042a30-3dd7-4bdb-95be-138f2767f5af
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737604342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.737604342
Directory	/workspace/20.clkmgr_trans/latest

Test location	/workspace/coverage/default/21.clkmgr_alert_test.3289077450
Short name	T409
Test name
Test status
Simulation time	20646130 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:21 PM PDT 24
Finished	Mar 26 12:38:22 PM PDT 24
Peak memory	200616 kb
Host	smart-4f79fa55-8f3a-4a33-880e-47efed98820b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289077450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk mgr_alert_test.3289077450
Directory	/workspace/21.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.1795029050
Short name	T362
Test name
Test status
Simulation time	64768709 ps
CPU time	0.96 seconds
Started	Mar 26 12:38:22 PM PDT 24
Finished	Mar 26 12:38:23 PM PDT 24
Peak memory	200572 kb
Host	smart-c0bd18ac-6e94-4efe-907d-06ac617ad0dc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795029050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.1795029050
Directory	/workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_status.3443965639
Short name	T412
Test name
Test status
Simulation time	16448329 ps
CPU time	0.69 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	199504 kb
Host	smart-605cbe08-391d-40ed-be58-255c51c37ba6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443965639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.3443965639
Directory	/workspace/21.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/21.clkmgr_div_intersig_mubi.3969486934
Short name	T231
Test name
Test status
Simulation time	23876527 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:25 PM PDT 24
Peak memory	200544 kb
Host	smart-4f228d2f-b7b1-4aa6-af08-8a40d3cfb66d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969486934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.3969486934
Directory	/workspace/21.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_extclk.1561946362
Short name	T381
Test name
Test status
Simulation time	52287303 ps
CPU time	0.86 seconds
Started	Mar 26 12:38:22 PM PDT 24
Finished	Mar 26 12:38:23 PM PDT 24
Peak memory	200548 kb
Host	smart-e361a55e-39d1-4e8f-a21f-00116bf8c625
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561946362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.1561946362
Directory	/workspace/21.clkmgr_extclk/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency.2927032899
Short name	T32
Test name
Test status
Simulation time	2001935989 ps
CPU time	14.96 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:39 PM PDT 24
Peak memory	200696 kb
Host	smart-866bdeeb-a4ab-459d-a995-87126fe4edc9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927032899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.2927032899
Directory	/workspace/21.clkmgr_frequency/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency_timeout.1426219795
Short name	T244
Test name
Test status
Simulation time	502066140 ps
CPU time	3.48 seconds
Started	Mar 26 12:38:19 PM PDT 24
Finished	Mar 26 12:38:23 PM PDT 24
Peak memory	200632 kb
Host	smart-2bc2e70a-3785-4708-a26d-c9dda4d06e1c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426219795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t imeout.1426219795
Directory	/workspace/21.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/21.clkmgr_idle_intersig_mubi.3961813554
Short name	T253
Test name
Test status
Simulation time	31209505 ps
CPU time	0.84 seconds
Started	Mar 26 12:38:28 PM PDT 24
Finished	Mar 26 12:38:29 PM PDT 24
Peak memory	200876 kb
Host	smart-8f6c0822-8817-4115-b67f-80a4ab36482a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961813554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.3961813554
Directory	/workspace/21.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.286426556
Short name	T609
Test name
Test status
Simulation time	16766149 ps
CPU time	0.75 seconds
Started	Mar 26 12:38:22 PM PDT 24
Finished	Mar 26 12:38:23 PM PDT 24
Peak memory	200600 kb
Host	smart-48784ea5-5a12-4d83-b37d-2befd0061938
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286426556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.clkmgr_lc_clk_byp_req_intersig_mubi.286426556
Directory	/workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.3032974483
Short name	T706
Test name
Test status
Simulation time	34336755 ps
CPU time	0.81 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:24 PM PDT 24
Peak memory	200564 kb
Host	smart-5a67fa0a-ec0a-4c7e-a43f-f70740321f81
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032974483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.clkmgr_lc_ctrl_intersig_mubi.3032974483
Directory	/workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_peri.2006831976
Short name	T314
Test name
Test status
Simulation time	50967588 ps
CPU time	0.86 seconds
Started	Mar 26 12:38:21 PM PDT 24
Finished	Mar 26 12:38:22 PM PDT 24
Peak memory	200564 kb
Host	smart-4fc1786c-a6fc-4c1e-b3b7-e81ca398a9f6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006831976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.2006831976
Directory	/workspace/21.clkmgr_peri/latest

Test location	/workspace/coverage/default/21.clkmgr_regwen.1104453197
Short name	T108
Test name
Test status
Simulation time	1214276757 ps
CPU time	5.17 seconds
Started	Mar 26 12:38:22 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200724 kb
Host	smart-053fc8ce-5ac4-450f-9386-0e17aa10d59d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104453197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.1104453197
Directory	/workspace/21.clkmgr_regwen/latest

Test location	/workspace/coverage/default/21.clkmgr_smoke.3496200786
Short name	T507
Test name
Test status
Simulation time	16402526 ps
CPU time	0.79 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:24 PM PDT 24
Peak memory	200576 kb
Host	smart-19911a03-25c3-4d8c-a2a2-25bbf284484f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496200786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.3496200786
Directory	/workspace/21.clkmgr_smoke/latest

Test location	/workspace/coverage/default/21.clkmgr_trans.2903471902
Short name	T233
Test name
Test status
Simulation time	19450784 ps
CPU time	0.78 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:24 PM PDT 24
Peak memory	200588 kb
Host	smart-b71e0b6b-17ec-4633-9223-9ed59f74a2d3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903471902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.2903471902
Directory	/workspace/21.clkmgr_trans/latest

Test location	/workspace/coverage/default/22.clkmgr_alert_test.3421490358
Short name	T430
Test name
Test status
Simulation time	26465860 ps
CPU time	0.78 seconds
Started	Mar 26 12:38:27 PM PDT 24
Finished	Mar 26 12:38:28 PM PDT 24
Peak memory	200636 kb
Host	smart-938d2755-ae73-4884-8e1c-a4f15f3d44d7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421490358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk mgr_alert_test.3421490358
Directory	/workspace/22.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.4099505170
Short name	T741
Test name
Test status
Simulation time	108157942 ps
CPU time	1.02 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:25 PM PDT 24
Peak memory	200652 kb
Host	smart-b480eb32-3c13-4186-ad67-550fd378c520
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099505170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.4099505170
Directory	/workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_status.2279950806
Short name	T759
Test name
Test status
Simulation time	61982144 ps
CPU time	0.8 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:24 PM PDT 24
Peak memory	200504 kb
Host	smart-eb5cdc09-42c0-4c91-8678-24b54f6a2db8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279950806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.2279950806
Directory	/workspace/22.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/22.clkmgr_div_intersig_mubi.1826437032
Short name	T243
Test name
Test status
Simulation time	67396296 ps
CPU time	0.89 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:25 PM PDT 24
Peak memory	200652 kb
Host	smart-d3a93dea-4e8a-4d5c-8ef7-27a88ceae91a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826437032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.1826437032
Directory	/workspace/22.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_extclk.150156900
Short name	T366
Test name
Test status
Simulation time	24300594 ps
CPU time	0.94 seconds
Started	Mar 26 12:38:20 PM PDT 24
Finished	Mar 26 12:38:21 PM PDT 24
Peak memory	200604 kb
Host	smart-21b9256e-889b-4c7f-9ca1-b133577f6ae4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150156900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.150156900
Directory	/workspace/22.clkmgr_extclk/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency.3399242635
Short name	T295
Test name
Test status
Simulation time	2479628672 ps
CPU time	13.41 seconds
Started	Mar 26 12:38:22 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200800 kb
Host	smart-995143ec-c00a-4025-b8ad-5fc130a6e842
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399242635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.3399242635
Directory	/workspace/22.clkmgr_frequency/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency_timeout.227599489
Short name	T585
Test name
Test status
Simulation time	1674027932 ps
CPU time	6.07 seconds
Started	Mar 26 12:38:28 PM PDT 24
Finished	Mar 26 12:38:34 PM PDT 24
Peak memory	200944 kb
Host	smart-2597c9a8-9f65-4b11-a044-138d738ddbba
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227599489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_ti meout.227599489
Directory	/workspace/22.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/22.clkmgr_idle_intersig_mubi.1220773718
Short name	T702
Test name
Test status
Simulation time	34509477 ps
CPU time	0.95 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:25 PM PDT 24
Peak memory	200496 kb
Host	smart-df0564e0-bd44-407d-aa30-741eac004fe2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220773718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.1220773718
Directory	/workspace/22.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.504437831
Short name	T786
Test name
Test status
Simulation time	14187055 ps
CPU time	0.76 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:25 PM PDT 24
Peak memory	200488 kb
Host	smart-be0955ad-c40a-4439-b955-3443ded167b2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504437831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.clkmgr_lc_clk_byp_req_intersig_mubi.504437831
Directory	/workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.1057622592
Short name	T612
Test name
Test status
Simulation time	19757223 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200868 kb
Host	smart-8e762c3c-2f6c-48b4-8619-3fe2aca1fb53
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057622592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.clkmgr_lc_ctrl_intersig_mubi.1057622592
Directory	/workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_peri.3560122647
Short name	T208
Test name
Test status
Simulation time	90650998 ps
CPU time	0.9 seconds
Started	Mar 26 12:38:21 PM PDT 24
Finished	Mar 26 12:38:22 PM PDT 24
Peak memory	200540 kb
Host	smart-78381da9-2443-46cc-958e-8ac8f781d14a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560122647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.3560122647
Directory	/workspace/22.clkmgr_peri/latest

Test location	/workspace/coverage/default/22.clkmgr_regwen.321619931
Short name	T552
Test name
Test status
Simulation time	972179637 ps
CPU time	5.68 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:29 PM PDT 24
Peak memory	200716 kb
Host	smart-fbd457dd-a4be-4469-b455-e8036cb8ba3f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321619931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.321619931
Directory	/workspace/22.clkmgr_regwen/latest

Test location	/workspace/coverage/default/22.clkmgr_smoke.1588409072
Short name	T328
Test name
Test status
Simulation time	58185217 ps
CPU time	0.95 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:25 PM PDT 24
Peak memory	200652 kb
Host	smart-6fedc5cb-a8f8-447f-bb92-cd94d9986032
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588409072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.1588409072
Directory	/workspace/22.clkmgr_smoke/latest

Test location	/workspace/coverage/default/22.clkmgr_stress_all.1146143890
Short name	T400
Test name
Test status
Simulation time	11052665882 ps
CPU time	44.58 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:39:07 PM PDT 24
Peak memory	200884 kb
Host	smart-19160188-9e17-4a25-8859-e20d0a788e80
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146143890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.1146143890
Directory	/workspace/22.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.2359687072
Short name	T413
Test name
Test status
Simulation time	100474429159 ps
CPU time	515.86 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:47:00 PM PDT 24
Peak memory	209228 kb
Host	smart-26c9f27f-3824-4532-b50b-65d80e3f32d7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2359687072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.2359687072
Directory	/workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.clkmgr_trans.1590152386
Short name	T764
Test name
Test status
Simulation time	27875887 ps
CPU time	0.84 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:24 PM PDT 24
Peak memory	200580 kb
Host	smart-50ca72cf-f214-46a2-8f21-9c3ee89b3cbe
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590152386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.1590152386
Directory	/workspace/22.clkmgr_trans/latest

Test location	/workspace/coverage/default/23.clkmgr_alert_test.547129145
Short name	T564
Test name
Test status
Simulation time	66580950 ps
CPU time	0.92 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200664 kb
Host	smart-bae94cb2-aaf1-4fc7-9472-48a08332a095
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547129145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkm gr_alert_test.547129145
Directory	/workspace/23.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.1293859812
Short name	T662
Test name
Test status
Simulation time	19697684 ps
CPU time	0.76 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200556 kb
Host	smart-f26645f5-1df0-4349-833c-8ae94fe60397
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293859812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.1293859812
Directory	/workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_status.318104
Short name	T739
Test name
Test status
Simulation time	92868727 ps
CPU time	0.87 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	199820 kb
Host	smart-9da8e052-8158-4fce-a622-31722f55e3ae
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.318104
Directory	/workspace/23.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/23.clkmgr_div_intersig_mubi.841199762
Short name	T637
Test name
Test status
Simulation time	83491985 ps
CPU time	1.08 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:25 PM PDT 24
Peak memory	200660 kb
Host	smart-6170bc21-775b-466c-be3b-af01ddd599f0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841199762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.clkmgr_div_intersig_mubi.841199762
Directory	/workspace/23.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_extclk.4015174382
Short name	T711
Test name
Test status
Simulation time	20491952 ps
CPU time	0.79 seconds
Started	Mar 26 12:38:27 PM PDT 24
Finished	Mar 26 12:38:28 PM PDT 24
Peak memory	200576 kb
Host	smart-cde0f3e2-87e5-49d9-b442-c50af6b50da8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015174382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.4015174382
Directory	/workspace/23.clkmgr_extclk/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency.2232276281
Short name	T701
Test name
Test status
Simulation time	561797499 ps
CPU time	4.73 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:28 PM PDT 24
Peak memory	200640 kb
Host	smart-05dfe027-f467-4d07-9aed-1d8a02cb06c1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232276281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.2232276281
Directory	/workspace/23.clkmgr_frequency/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency_timeout.721451825
Short name	T766
Test name
Test status
Simulation time	1456910839 ps
CPU time	10.73 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200628 kb
Host	smart-4ce6ae6a-f858-406f-95ee-3f0c01ceb05a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721451825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_ti meout.721451825
Directory	/workspace/23.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/23.clkmgr_idle_intersig_mubi.298500823
Short name	T225
Test name
Test status
Simulation time	19865962 ps
CPU time	0.83 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200568 kb
Host	smart-9e5ae95a-c90d-423e-a573-da60827b0808
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298500823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.clkmgr_idle_intersig_mubi.298500823
Directory	/workspace/23.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.3659325960
Short name	T391
Test name
Test status
Simulation time	17557080 ps
CPU time	0.8 seconds
Started	Mar 26 12:38:31 PM PDT 24
Finished	Mar 26 12:38:32 PM PDT 24
Peak memory	200608 kb
Host	smart-196c668c-1056-446a-ae0e-61ec47389f4c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659325960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.clkmgr_lc_clk_byp_req_intersig_mubi.3659325960
Directory	/workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.758160495
Short name	T849
Test name
Test status
Simulation time	84637001 ps
CPU time	0.93 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200608 kb
Host	smart-11dba169-ac22-4727-868c-abe6a082e128
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758160495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.clkmgr_lc_ctrl_intersig_mubi.758160495
Directory	/workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_peri.1351589324
Short name	T556
Test name
Test status
Simulation time	16165494 ps
CPU time	0.73 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:24 PM PDT 24
Peak memory	200528 kb
Host	smart-7b582631-0103-4603-9610-0dea29fd45d3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351589324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.1351589324
Directory	/workspace/23.clkmgr_peri/latest

Test location	/workspace/coverage/default/23.clkmgr_regwen.2261113780
Short name	T836
Test name
Test status
Simulation time	528204419 ps
CPU time	2.5 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:29 PM PDT 24
Peak memory	200488 kb
Host	smart-3089ceb9-9a6a-459b-b204-1f8c66cb8ef3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261113780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.2261113780
Directory	/workspace/23.clkmgr_regwen/latest

Test location	/workspace/coverage/default/23.clkmgr_smoke.2682508172
Short name	T688
Test name
Test status
Simulation time	25451613 ps
CPU time	0.81 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200568 kb
Host	smart-5d31345b-949d-4d37-9200-d6222ebf3c16
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682508172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.2682508172
Directory	/workspace/23.clkmgr_smoke/latest

Test location	/workspace/coverage/default/23.clkmgr_stress_all.4129386801
Short name	T589
Test name
Test status
Simulation time	2839965280 ps
CPU time	16.19 seconds
Started	Mar 26 12:38:27 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200932 kb
Host	smart-57a231d4-8b49-4c0d-a63b-6cc1e69679f5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129386801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.4129386801
Directory	/workspace/23.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.2880823139
Short name	T11
Test name
Test status
Simulation time	34664251565 ps
CPU time	493.02 seconds
Started	Mar 26 12:38:27 PM PDT 24
Finished	Mar 26 12:46:40 PM PDT 24
Peak memory	217364 kb
Host	smart-1058dbf7-7c19-4c73-9e67-2d0a8d92d9c7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2880823139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.2880823139
Directory	/workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.clkmgr_trans.3934193192
Short name	T407
Test name
Test status
Simulation time	64448803 ps
CPU time	0.93 seconds
Started	Mar 26 12:38:28 PM PDT 24
Finished	Mar 26 12:38:29 PM PDT 24
Peak memory	200592 kb
Host	smart-3038e265-dc8e-49d8-8025-7c7e1c9926a8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934193192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.3934193192
Directory	/workspace/23.clkmgr_trans/latest

Test location	/workspace/coverage/default/24.clkmgr_alert_test.492869788
Short name	T769
Test name
Test status
Simulation time	15952152 ps
CPU time	0.72 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:25 PM PDT 24
Peak memory	200616 kb
Host	smart-0536d8fc-a5b9-4f42-bfb1-a7be1d67471e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492869788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkm gr_alert_test.492869788
Directory	/workspace/24.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3997409594
Short name	T252
Test name
Test status
Simulation time	26245886 ps
CPU time	0.9 seconds
Started	Mar 26 12:38:27 PM PDT 24
Finished	Mar 26 12:38:28 PM PDT 24
Peak memory	200640 kb
Host	smart-4dbd9b45-e262-4da4-9641-a83ca854b269
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997409594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.3997409594
Directory	/workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_status.3195839758
Short name	T161
Test name
Test status
Simulation time	16717966 ps
CPU time	0.73 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200548 kb
Host	smart-43021e64-0499-48e0-b9a4-541cdef3d06a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195839758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.3195839758
Directory	/workspace/24.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/24.clkmgr_div_intersig_mubi.1547278813
Short name	T534
Test name
Test status
Simulation time	37306667 ps
CPU time	0.81 seconds
Started	Mar 26 12:38:31 PM PDT 24
Finished	Mar 26 12:38:32 PM PDT 24
Peak memory	200644 kb
Host	smart-cf7f5b1c-84d2-40b9-947f-acc7c787315d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547278813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.1547278813
Directory	/workspace/24.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_extclk.3414931012
Short name	T530
Test name
Test status
Simulation time	24229538 ps
CPU time	0.86 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200628 kb
Host	smart-788bf997-1637-4782-983f-dc2a525a473d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414931012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.3414931012
Directory	/workspace/24.clkmgr_extclk/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency.2566735711
Short name	T410
Test name
Test status
Simulation time	1608647730 ps
CPU time	7.23 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:33 PM PDT 24
Peak memory	200504 kb
Host	smart-fe0d848f-ef7c-4c87-abaa-29c2aeaecc66
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566735711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.2566735711
Directory	/workspace/24.clkmgr_frequency/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency_timeout.2785651689
Short name	T839
Test name
Test status
Simulation time	1094467285 ps
CPU time	8.2 seconds
Started	Mar 26 12:38:31 PM PDT 24
Finished	Mar 26 12:38:39 PM PDT 24
Peak memory	200716 kb
Host	smart-0c598e1a-641c-42e3-8c16-3223cb8ff549
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785651689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t imeout.2785651689
Directory	/workspace/24.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/24.clkmgr_idle_intersig_mubi.1361569579
Short name	T281
Test name
Test status
Simulation time	30061118 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:31 PM PDT 24
Finished	Mar 26 12:38:32 PM PDT 24
Peak memory	200524 kb
Host	smart-40827892-1374-41b8-beb2-77df1e7fd3c3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361569579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.1361569579
Directory	/workspace/24.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.2614492997
Short name	T349
Test name
Test status
Simulation time	11275296 ps
CPU time	0.8 seconds
Started	Mar 26 12:38:31 PM PDT 24
Finished	Mar 26 12:38:31 PM PDT 24
Peak memory	200644 kb
Host	smart-1e3f22cf-d52a-4618-97fc-3371b314c038
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614492997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.clkmgr_lc_clk_byp_req_intersig_mubi.2614492997
Directory	/workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.538208528
Short name	T731
Test name
Test status
Simulation time	107645360 ps
CPU time	1.09 seconds
Started	Mar 26 12:38:31 PM PDT 24
Finished	Mar 26 12:38:32 PM PDT 24
Peak memory	200648 kb
Host	smart-2ded344c-80cc-4d21-a2eb-7c8e60f5d603
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538208528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 24.clkmgr_lc_ctrl_intersig_mubi.538208528
Directory	/workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_peri.2919162150
Short name	T820
Test name
Test status
Simulation time	64563760 ps
CPU time	0.86 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200596 kb
Host	smart-e18ac52b-2372-4ad2-89a7-0db0401eae7e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919162150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.2919162150
Directory	/workspace/24.clkmgr_peri/latest

Test location	/workspace/coverage/default/24.clkmgr_regwen.2008323972
Short name	T543
Test name
Test status
Simulation time	1115338629 ps
CPU time	6.13 seconds
Started	Mar 26 12:38:25 PM PDT 24
Finished	Mar 26 12:38:31 PM PDT 24
Peak memory	200696 kb
Host	smart-eee51ff1-5211-4e50-bc2a-d9d2e84bd087
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008323972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.2008323972
Directory	/workspace/24.clkmgr_regwen/latest

Test location	/workspace/coverage/default/24.clkmgr_smoke.3122758226
Short name	T426
Test name
Test status
Simulation time	22153510 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:24 PM PDT 24
Peak memory	200580 kb
Host	smart-f720bc45-c4b5-4504-ac25-630aa94bbb8e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122758226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.3122758226
Directory	/workspace/24.clkmgr_smoke/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all.1560555084
Short name	T346
Test name
Test status
Simulation time	9192148445 ps
CPU time	66.72 seconds
Started	Mar 26 12:38:29 PM PDT 24
Finished	Mar 26 12:39:36 PM PDT 24
Peak memory	200828 kb
Host	smart-4733de92-c5c9-4239-87d7-29fe8a66d1ec
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560555084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.1560555084
Directory	/workspace/24.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.2799626273
Short name	T628
Test name
Test status
Simulation time	161344863166 ps
CPU time	889.71 seconds
Started	Mar 26 12:38:29 PM PDT 24
Finished	Mar 26 12:53:19 PM PDT 24
Peak memory	209240 kb
Host	smart-d0f6b705-88a7-4afc-9b96-cee3988d8f5a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2799626273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.2799626273
Directory	/workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.clkmgr_trans.1379691596
Short name	T438
Test name
Test status
Simulation time	94238023 ps
CPU time	1.1 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200548 kb
Host	smart-eb953abb-2bbf-4858-84c1-5c88a5d0cbdc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379691596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.1379691596
Directory	/workspace/24.clkmgr_trans/latest

Test location	/workspace/coverage/default/25.clkmgr_alert_test.695464255
Short name	T467
Test name
Test status
Simulation time	15186183 ps
CPU time	0.73 seconds
Started	Mar 26 12:38:22 PM PDT 24
Finished	Mar 26 12:38:23 PM PDT 24
Peak memory	200612 kb
Host	smart-fe70bf79-ae2a-46e4-996c-7dbbbe4c3172
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695464255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkm gr_alert_test.695464255
Directory	/workspace/25.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_status.437819914
Short name	T357
Test name
Test status
Simulation time	12636649 ps
CPU time	0.71 seconds
Started	Mar 26 12:38:28 PM PDT 24
Finished	Mar 26 12:38:29 PM PDT 24
Peak memory	199544 kb
Host	smart-23492201-f47f-433d-acb2-61294741a5da
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437819914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.437819914
Directory	/workspace/25.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/25.clkmgr_div_intersig_mubi.1043626845
Short name	T269
Test name
Test status
Simulation time	115359060 ps
CPU time	1.03 seconds
Started	Mar 26 12:38:29 PM PDT 24
Finished	Mar 26 12:38:30 PM PDT 24
Peak memory	200552 kb
Host	smart-2f4c4eb6-c792-484c-bf93-b16fd945f4f6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043626845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.1043626845
Directory	/workspace/25.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_extclk.1497060647
Short name	T483
Test name
Test status
Simulation time	74409269 ps
CPU time	1 seconds
Started	Mar 26 12:38:29 PM PDT 24
Finished	Mar 26 12:38:30 PM PDT 24
Peak memory	200556 kb
Host	smart-ecae9e02-e5ea-4124-a261-10f0c48c6b49
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497060647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.1497060647
Directory	/workspace/25.clkmgr_extclk/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency.2197974819
Short name	T17
Test name
Test status
Simulation time	1168533604 ps
CPU time	6.11 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:30 PM PDT 24
Peak memory	200548 kb
Host	smart-f4ed36e5-c715-41b1-92f6-15ccb172b84b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197974819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.2197974819
Directory	/workspace/25.clkmgr_frequency/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency_timeout.1504094552
Short name	T573
Test name
Test status
Simulation time	1949159335 ps
CPU time	10.11 seconds
Started	Mar 26 12:38:29 PM PDT 24
Finished	Mar 26 12:38:40 PM PDT 24
Peak memory	200644 kb
Host	smart-f7dd3b5a-2f04-4cfd-94c8-0f64620af920
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504094552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t imeout.1504094552
Directory	/workspace/25.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/25.clkmgr_idle_intersig_mubi.820398992
Short name	T30
Test name
Test status
Simulation time	53642266 ps
CPU time	0.87 seconds
Started	Mar 26 12:38:22 PM PDT 24
Finished	Mar 26 12:38:24 PM PDT 24
Peak memory	200568 kb
Host	smart-b4d3a034-fe1f-4fc0-b0c0-c8765e84feb3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820398992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.clkmgr_idle_intersig_mubi.820398992
Directory	/workspace/25.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.75694438
Short name	T425
Test name
Test status
Simulation time	55285131 ps
CPU time	0.84 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200616 kb
Host	smart-8fc92148-ba1e-49aa-9f39-c35db2e9f910
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75694438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_clk_byp_req_intersig_mubi.75694438
Directory	/workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.2560429340
Short name	T679
Test name
Test status
Simulation time	22806618 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:27 PM PDT 24
Peak memory	200632 kb
Host	smart-2c0f6c88-874e-4f02-a257-62174e66bde8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560429340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_ctrl_intersig_mubi.2560429340
Directory	/workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_peri.77436016
Short name	T24
Test name
Test status
Simulation time	41591310 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:25 PM PDT 24
Peak memory	200596 kb
Host	smart-c91da6cf-08fe-4764-bbf2-0c644a73b428
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77436016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.77436016
Directory	/workspace/25.clkmgr_peri/latest

Test location	/workspace/coverage/default/25.clkmgr_smoke.4290414019
Short name	T627
Test name
Test status
Simulation time	68490325 ps
CPU time	0.99 seconds
Started	Mar 26 12:38:29 PM PDT 24
Finished	Mar 26 12:38:31 PM PDT 24
Peak memory	200576 kb
Host	smart-40eb2af5-eb2b-42a9-8af8-9c5ce096850a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290414019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.4290414019
Directory	/workspace/25.clkmgr_smoke/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all.388392563
Short name	T536
Test name
Test status
Simulation time	5029553850 ps
CPU time	21.39 seconds
Started	Mar 26 12:38:28 PM PDT 24
Finished	Mar 26 12:38:49 PM PDT 24
Peak memory	201152 kb
Host	smart-acd85e99-bf70-4821-822e-12551484b238
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388392563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.388392563
Directory	/workspace/25.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.4212578838
Short name	T308
Test name
Test status
Simulation time	16922893657 ps
CPU time	259.63 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:42:46 PM PDT 24
Peak memory	209276 kb
Host	smart-1e9daeca-d872-4fe8-bdec-b82b4d3b6a00
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4212578838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.4212578838
Directory	/workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.clkmgr_trans.149728986
Short name	T260
Test name
Test status
Simulation time	57993204 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:23 PM PDT 24
Finished	Mar 26 12:38:24 PM PDT 24
Peak memory	200568 kb
Host	smart-543c8edb-cb42-40c1-849b-a0f5cdabc24e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149728986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.149728986
Directory	/workspace/25.clkmgr_trans/latest

Test location	/workspace/coverage/default/26.clkmgr_alert_test.2780219640
Short name	T540
Test name
Test status
Simulation time	52356444 ps
CPU time	0.8 seconds
Started	Mar 26 12:38:35 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200592 kb
Host	smart-2d0cfe3b-6015-4ae0-87b7-54e320e35e34
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780219640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk mgr_alert_test.2780219640
Directory	/workspace/26.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.4060763375
Short name	T88
Test name
Test status
Simulation time	84611470 ps
CPU time	0.99 seconds
Started	Mar 26 12:38:36 PM PDT 24
Finished	Mar 26 12:38:37 PM PDT 24
Peak memory	200872 kb
Host	smart-b5b49cb5-b9a1-4eeb-ba0e-e829bbd49c9e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060763375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.4060763375
Directory	/workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_status.3810183057
Short name	T399
Test name
Test status
Simulation time	29506698 ps
CPU time	0.71 seconds
Started	Mar 26 12:38:34 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200508 kb
Host	smart-53e90d2a-1d00-427d-91f6-9c0cfe83ae38
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810183057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.3810183057
Directory	/workspace/26.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/26.clkmgr_div_intersig_mubi.1108686541
Short name	T205
Test name
Test status
Simulation time	111423348 ps
CPU time	1.05 seconds
Started	Mar 26 12:38:36 PM PDT 24
Finished	Mar 26 12:38:37 PM PDT 24
Peak memory	200568 kb
Host	smart-0f64de2e-aec3-44e0-b3bc-eb12dc3e0c0e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108686541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.1108686541
Directory	/workspace/26.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_extclk.2972420686
Short name	T341
Test name
Test status
Simulation time	133898087 ps
CPU time	1.13 seconds
Started	Mar 26 12:38:22 PM PDT 24
Finished	Mar 26 12:38:23 PM PDT 24
Peak memory	200564 kb
Host	smart-1d217be5-07f0-47bb-8347-7e9e52b68386
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972420686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.2972420686
Directory	/workspace/26.clkmgr_extclk/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency.4217466431
Short name	T302
Test name
Test status
Simulation time	330246742 ps
CPU time	1.98 seconds
Started	Mar 26 12:38:26 PM PDT 24
Finished	Mar 26 12:38:29 PM PDT 24
Peak memory	200560 kb
Host	smart-8926ea9c-7cda-463a-afb9-c1bbba615c4f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217466431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.4217466431
Directory	/workspace/26.clkmgr_frequency/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency_timeout.3892537024
Short name	T621
Test name
Test status
Simulation time	350339549 ps
CPU time	1.63 seconds
Started	Mar 26 12:38:33 PM PDT 24
Finished	Mar 26 12:38:34 PM PDT 24
Peak memory	200636 kb
Host	smart-655bce8a-8023-438d-9923-0b56b722fe56
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892537024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t imeout.3892537024
Directory	/workspace/26.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/26.clkmgr_idle_intersig_mubi.4131359560
Short name	T776
Test name
Test status
Simulation time	16100143 ps
CPU time	0.76 seconds
Started	Mar 26 12:38:31 PM PDT 24
Finished	Mar 26 12:38:32 PM PDT 24
Peak memory	200404 kb
Host	smart-1be15463-df65-4af2-a82a-9fa8f164b727
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131359560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_idle_intersig_mubi.4131359560
Directory	/workspace/26.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3576705980
Short name	T189
Test name
Test status
Simulation time	28655332 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:34 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200544 kb
Host	smart-c05ece72-a529-41f6-8617-f559937696d5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576705980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 26.clkmgr_lc_clk_byp_req_intersig_mubi.3576705980
Directory	/workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.3204962034
Short name	T442
Test name
Test status
Simulation time	30458298 ps
CPU time	0.86 seconds
Started	Mar 26 12:38:34 PM PDT 24
Finished	Mar 26 12:38:36 PM PDT 24
Peak memory	200588 kb
Host	smart-3f70640f-19e8-4e0d-acaa-3ecb5bf943ff
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204962034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 26.clkmgr_lc_ctrl_intersig_mubi.3204962034
Directory	/workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_peri.1792531711
Short name	T575
Test name
Test status
Simulation time	19438364 ps
CPU time	0.82 seconds
Started	Mar 26 12:38:34 PM PDT 24
Finished	Mar 26 12:38:34 PM PDT 24
Peak memory	200556 kb
Host	smart-0e0157f0-b940-48d4-b830-61a2fde00966
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792531711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.1792531711
Directory	/workspace/26.clkmgr_peri/latest

Test location	/workspace/coverage/default/26.clkmgr_regwen.3679214784
Short name	T481
Test name
Test status
Simulation time	668307559 ps
CPU time	4.13 seconds
Started	Mar 26 12:38:31 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200584 kb
Host	smart-8fa6d172-b658-4795-92a6-47e0ee8442fc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679214784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.3679214784
Directory	/workspace/26.clkmgr_regwen/latest

Test location	/workspace/coverage/default/26.clkmgr_smoke.2690651845
Short name	T141
Test name
Test status
Simulation time	69438741 ps
CPU time	0.99 seconds
Started	Mar 26 12:38:24 PM PDT 24
Finished	Mar 26 12:38:25 PM PDT 24
Peak memory	200580 kb
Host	smart-54f2a021-385c-4c1c-8344-603d1eb3c0b1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690651845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.2690651845
Directory	/workspace/26.clkmgr_smoke/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all.3327371385
Short name	T817
Test name
Test status
Simulation time	2401525561 ps
CPU time	13.72 seconds
Started	Mar 26 12:38:34 PM PDT 24
Finished	Mar 26 12:38:48 PM PDT 24
Peak memory	200852 kb
Host	smart-3080cbf7-11fd-4593-a742-20dc542f8df4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327371385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.3327371385
Directory	/workspace/26.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.2678396856
Short name	T157
Test name
Test status
Simulation time	15326568256 ps
CPU time	210.77 seconds
Started	Mar 26 12:38:36 PM PDT 24
Finished	Mar 26 12:42:07 PM PDT 24
Peak memory	209156 kb
Host	smart-dfaed70f-05ef-4213-b080-3360e032e0cb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2678396856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.2678396856
Directory	/workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.clkmgr_trans.550834604
Short name	T541
Test name
Test status
Simulation time	45395188 ps
CPU time	0.96 seconds
Started	Mar 26 12:38:42 PM PDT 24
Finished	Mar 26 12:38:43 PM PDT 24
Peak memory	200552 kb
Host	smart-01dc47e7-7baf-480e-97cf-683f0460af5e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550834604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.550834604
Directory	/workspace/26.clkmgr_trans/latest

Test location	/workspace/coverage/default/27.clkmgr_alert_test.259150682
Short name	T695
Test name
Test status
Simulation time	31141342 ps
CPU time	0.81 seconds
Started	Mar 26 12:38:37 PM PDT 24
Finished	Mar 26 12:38:38 PM PDT 24
Peak memory	200620 kb
Host	smart-0d96fd55-fdbf-4297-ac38-39246445d261
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259150682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkm gr_alert_test.259150682
Directory	/workspace/27.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1799264936
Short name	T411
Test name
Test status
Simulation time	19662992 ps
CPU time	0.87 seconds
Started	Mar 26 12:38:42 PM PDT 24
Finished	Mar 26 12:38:43 PM PDT 24
Peak memory	200564 kb
Host	smart-5f44ec98-b08c-4ad0-b875-8f7b108a0f56
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799264936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.1799264936
Directory	/workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_status.1537723166
Short name	T829
Test name
Test status
Simulation time	25153409 ps
CPU time	0.73 seconds
Started	Mar 26 12:38:33 PM PDT 24
Finished	Mar 26 12:38:34 PM PDT 24
Peak memory	200508 kb
Host	smart-1fabc3d3-38c1-4818-a74e-23451b4cc1f8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537723166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.1537723166
Directory	/workspace/27.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/27.clkmgr_div_intersig_mubi.151738540
Short name	T254
Test name
Test status
Simulation time	107833705 ps
CPU time	0.96 seconds
Started	Mar 26 12:38:31 PM PDT 24
Finished	Mar 26 12:38:32 PM PDT 24
Peak memory	200592 kb
Host	smart-734e1985-fa5f-49ad-81e4-5d3beb64b6d0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151738540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.clkmgr_div_intersig_mubi.151738540
Directory	/workspace/27.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_extclk.763679331
Short name	T230
Test name
Test status
Simulation time	43456283 ps
CPU time	0.88 seconds
Started	Mar 26 12:38:33 PM PDT 24
Finished	Mar 26 12:38:34 PM PDT 24
Peak memory	200564 kb
Host	smart-df44927f-323d-4753-a3e6-738517d4e757
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763679331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.763679331
Directory	/workspace/27.clkmgr_extclk/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency.848109836
Short name	T434
Test name
Test status
Simulation time	1056247491 ps
CPU time	4.76 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:49 PM PDT 24
Peak memory	200532 kb
Host	smart-feaea6a3-cb27-494f-a6a2-dcf214cd4a26
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848109836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.848109836
Directory	/workspace/27.clkmgr_frequency/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency_timeout.3175661876
Short name	T53
Test name
Test status
Simulation time	809459494 ps
CPU time	3.01 seconds
Started	Mar 26 12:38:32 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200620 kb
Host	smart-b1cb76e0-7c51-4146-9ef0-64c98d91154e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175661876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t imeout.3175661876
Directory	/workspace/27.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/27.clkmgr_idle_intersig_mubi.2448934126
Short name	T785
Test name
Test status
Simulation time	28408914 ps
CPU time	0.8 seconds
Started	Mar 26 12:38:41 PM PDT 24
Finished	Mar 26 12:38:41 PM PDT 24
Peak memory	200560 kb
Host	smart-00558784-b5bb-403c-b2f0-2accc54802da
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448934126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.2448934126
Directory	/workspace/27.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.2957170613
Short name	T382
Test name
Test status
Simulation time	54736428 ps
CPU time	0.93 seconds
Started	Mar 26 12:38:33 PM PDT 24
Finished	Mar 26 12:38:34 PM PDT 24
Peak memory	200564 kb
Host	smart-79636a8c-c898-42ee-bada-026aa53dde94
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957170613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.clkmgr_lc_clk_byp_req_intersig_mubi.2957170613
Directory	/workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.3507214143
Short name	T550
Test name
Test status
Simulation time	29972367 ps
CPU time	0.91 seconds
Started	Mar 26 12:38:51 PM PDT 24
Finished	Mar 26 12:38:52 PM PDT 24
Peak memory	200576 kb
Host	smart-abea8154-094d-451b-bbb5-89531a591e79
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507214143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.clkmgr_lc_ctrl_intersig_mubi.3507214143
Directory	/workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_peri.1791850005
Short name	T822
Test name
Test status
Simulation time	43391571 ps
CPU time	0.8 seconds
Started	Mar 26 12:38:37 PM PDT 24
Finished	Mar 26 12:38:38 PM PDT 24
Peak memory	200540 kb
Host	smart-2e724b25-a111-4b30-97c1-209763d622b4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791850005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.1791850005
Directory	/workspace/27.clkmgr_peri/latest

Test location	/workspace/coverage/default/27.clkmgr_regwen.3926520648
Short name	T663
Test name
Test status
Simulation time	71035484 ps
CPU time	0.88 seconds
Started	Mar 26 12:38:37 PM PDT 24
Finished	Mar 26 12:38:38 PM PDT 24
Peak memory	200548 kb
Host	smart-749820da-b1c3-482f-8a4b-8d76a7cf662d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926520648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.3926520648
Directory	/workspace/27.clkmgr_regwen/latest

Test location	/workspace/coverage/default/27.clkmgr_smoke.3416492565
Short name	T635
Test name
Test status
Simulation time	21288895 ps
CPU time	0.82 seconds
Started	Mar 26 12:38:44 PM PDT 24
Finished	Mar 26 12:38:45 PM PDT 24
Peak memory	200564 kb
Host	smart-958fa10a-4f57-4f20-a0b9-726c077de6ed
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416492565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.3416492565
Directory	/workspace/27.clkmgr_smoke/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all.4243306605
Short name	T441
Test name
Test status
Simulation time	4225704975 ps
CPU time	16.58 seconds
Started	Mar 26 12:38:30 PM PDT 24
Finished	Mar 26 12:38:47 PM PDT 24
Peak memory	200888 kb
Host	smart-e96b56b9-0547-4f3a-9bc2-e78134ab5fd6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243306605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.4243306605
Directory	/workspace/27.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.2561376399
Short name	T515
Test name
Test status
Simulation time	72453554678 ps
CPU time	532.73 seconds
Started	Mar 26 12:38:31 PM PDT 24
Finished	Mar 26 12:47:24 PM PDT 24
Peak memory	217368 kb
Host	smart-49041254-e80d-496c-aac0-a128fab9b97e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2561376399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.2561376399
Directory	/workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.clkmgr_trans.3659568014
Short name	T267
Test name
Test status
Simulation time	45246368 ps
CPU time	0.92 seconds
Started	Mar 26 12:38:32 PM PDT 24
Finished	Mar 26 12:38:33 PM PDT 24
Peak memory	200552 kb
Host	smart-b7bae92c-f1f2-41b7-8021-3e39c6ceb3e6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659568014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.3659568014
Directory	/workspace/27.clkmgr_trans/latest

Test location	/workspace/coverage/default/28.clkmgr_alert_test.1201833709
Short name	T496
Test name
Test status
Simulation time	50050215 ps
CPU time	0.82 seconds
Started	Mar 26 12:38:31 PM PDT 24
Finished	Mar 26 12:38:32 PM PDT 24
Peak memory	200596 kb
Host	smart-c850ea3a-01d9-409f-9967-2486c12d0325
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201833709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk mgr_alert_test.1201833709
Directory	/workspace/28.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.1593747680
Short name	T736
Test name
Test status
Simulation time	25981134 ps
CPU time	0.89 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200576 kb
Host	smart-39522f14-a294-44f7-aa44-9bdf1f431ce8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593747680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.1593747680
Directory	/workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_status.3993291744
Short name	T653
Test name
Test status
Simulation time	83415299 ps
CPU time	0.83 seconds
Started	Mar 26 12:38:35 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200512 kb
Host	smart-d1e92347-2116-4d25-9d3b-04e19ea8c084
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993291744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.3993291744
Directory	/workspace/28.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/28.clkmgr_div_intersig_mubi.3202752252
Short name	T783
Test name
Test status
Simulation time	61267386 ps
CPU time	0.93 seconds
Started	Mar 26 12:38:36 PM PDT 24
Finished	Mar 26 12:38:37 PM PDT 24
Peak memory	200548 kb
Host	smart-25e9572a-e00a-4b61-89ba-31fa09c1d546
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202752252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.3202752252
Directory	/workspace/28.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_extclk.536088551
Short name	T226
Test name
Test status
Simulation time	31190560 ps
CPU time	0.89 seconds
Started	Mar 26 12:38:34 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200608 kb
Host	smart-152a3c4c-44fe-491d-9c2f-41b1b91fa944
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536088551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.536088551
Directory	/workspace/28.clkmgr_extclk/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency.3584900637
Short name	T777
Test name
Test status
Simulation time	1933326539 ps
CPU time	6.46 seconds
Started	Mar 26 12:38:32 PM PDT 24
Finished	Mar 26 12:38:39 PM PDT 24
Peak memory	200540 kb
Host	smart-edbf6eb7-1c8a-4bf4-9a4a-767828c99808
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584900637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.3584900637
Directory	/workspace/28.clkmgr_frequency/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency_timeout.432298335
Short name	T213
Test name
Test status
Simulation time	1908759639 ps
CPU time	7.75 seconds
Started	Mar 26 12:38:37 PM PDT 24
Finished	Mar 26 12:38:45 PM PDT 24
Peak memory	200668 kb
Host	smart-04079303-f2c6-46f7-ae7c-04916b3647c4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432298335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_ti meout.432298335
Directory	/workspace/28.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/28.clkmgr_idle_intersig_mubi.1728616210
Short name	T457
Test name
Test status
Simulation time	41028513 ps
CPU time	0.78 seconds
Started	Mar 26 12:38:31 PM PDT 24
Finished	Mar 26 12:38:32 PM PDT 24
Peak memory	200400 kb
Host	smart-c7247587-bbf3-42a6-96ed-caa200405542
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728616210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_idle_intersig_mubi.1728616210
Directory	/workspace/28.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.2410554590
Short name	T273
Test name
Test status
Simulation time	26228010 ps
CPU time	0.78 seconds
Started	Mar 26 12:38:36 PM PDT 24
Finished	Mar 26 12:38:37 PM PDT 24
Peak memory	200584 kb
Host	smart-7bdc68ee-6275-43c1-b4a9-b4a63f5ea6bc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410554590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.clkmgr_lc_clk_byp_req_intersig_mubi.2410554590
Directory	/workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.255669150
Short name	T742
Test name
Test status
Simulation time	40767788 ps
CPU time	0.8 seconds
Started	Mar 26 12:38:35 PM PDT 24
Finished	Mar 26 12:38:36 PM PDT 24
Peak memory	200596 kb
Host	smart-d5eb9798-a446-4992-b900-9919ae8f0930
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255669150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.clkmgr_lc_ctrl_intersig_mubi.255669150
Directory	/workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_peri.2716767673
Short name	T718
Test name
Test status
Simulation time	16648406 ps
CPU time	0.74 seconds
Started	Mar 26 12:38:46 PM PDT 24
Finished	Mar 26 12:38:47 PM PDT 24
Peak memory	200560 kb
Host	smart-f17a7373-0671-49c6-9f15-d6f32116315d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716767673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.2716767673
Directory	/workspace/28.clkmgr_peri/latest

Test location	/workspace/coverage/default/28.clkmgr_regwen.1436129259
Short name	T768
Test name
Test status
Simulation time	756983320 ps
CPU time	3.59 seconds
Started	Mar 26 12:38:31 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200668 kb
Host	smart-cecebc4a-f51a-452b-a1a6-79baa08e7980
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436129259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.1436129259
Directory	/workspace/28.clkmgr_regwen/latest

Test location	/workspace/coverage/default/28.clkmgr_smoke.3619469113
Short name	T324
Test name
Test status
Simulation time	50901960 ps
CPU time	0.88 seconds
Started	Mar 26 12:38:35 PM PDT 24
Finished	Mar 26 12:38:36 PM PDT 24
Peak memory	200596 kb
Host	smart-4a3d0ce0-8a66-44d0-98f5-620221b835fc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619469113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.3619469113
Directory	/workspace/28.clkmgr_smoke/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all.3086046911
Short name	T404
Test name
Test status
Simulation time	1328436167 ps
CPU time	11.02 seconds
Started	Mar 26 12:38:32 PM PDT 24
Finished	Mar 26 12:38:43 PM PDT 24
Peak memory	200752 kb
Host	smart-013619d8-e17c-4c8a-85a6-6ee2eb203a0a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086046911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.3086046911
Directory	/workspace/28.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.4093499925
Short name	T74
Test name
Test status
Simulation time	38903394793 ps
CPU time	586.6 seconds
Started	Mar 26 12:38:42 PM PDT 24
Finished	Mar 26 12:48:29 PM PDT 24
Peak memory	210144 kb
Host	smart-70e45a44-73da-4890-9b32-d3e53995c732
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4093499925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.4093499925
Directory	/workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.clkmgr_trans.748006784
Short name	T235
Test name
Test status
Simulation time	290398903 ps
CPU time	1.72 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:47 PM PDT 24
Peak memory	200556 kb
Host	smart-d5befd7a-a1b1-4f1c-8c46-5aae2e72880b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748006784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.748006784
Directory	/workspace/28.clkmgr_trans/latest

Test location	/workspace/coverage/default/29.clkmgr_alert_test.2861666302
Short name	T502
Test name
Test status
Simulation time	48013252 ps
CPU time	0.87 seconds
Started	Mar 26 12:38:33 PM PDT 24
Finished	Mar 26 12:38:34 PM PDT 24
Peak memory	200640 kb
Host	smart-c1c365ac-8658-4392-9216-a7d943bc0c73
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861666302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk mgr_alert_test.2861666302
Directory	/workspace/29.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.3834000528
Short name	T418
Test name
Test status
Simulation time	27174502 ps
CPU time	0.92 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200556 kb
Host	smart-60b97c71-d8e3-4281-8457-22f2983ed906
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834000528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.3834000528
Directory	/workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_status.3948622980
Short name	T602
Test name
Test status
Simulation time	17259193 ps
CPU time	0.72 seconds
Started	Mar 26 12:38:36 PM PDT 24
Finished	Mar 26 12:38:36 PM PDT 24
Peak memory	199504 kb
Host	smart-9f278bb3-2e96-442f-914d-af67ba46e11f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948622980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.3948622980
Directory	/workspace/29.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/29.clkmgr_div_intersig_mubi.2930376771
Short name	T246
Test name
Test status
Simulation time	61985843 ps
CPU time	0.89 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200552 kb
Host	smart-cd5eb252-116a-4b6e-a788-4692ee93308d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930376771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.2930376771
Directory	/workspace/29.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_extclk.1599137104
Short name	T712
Test name
Test status
Simulation time	96070300 ps
CPU time	1.08 seconds
Started	Mar 26 12:38:36 PM PDT 24
Finished	Mar 26 12:38:37 PM PDT 24
Peak memory	200560 kb
Host	smart-9d12d9fa-415b-43ac-842f-cfe13f80f8b3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599137104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1599137104
Directory	/workspace/29.clkmgr_extclk/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency.4248008935
Short name	T332
Test name
Test status
Simulation time	2130847894 ps
CPU time	11.63 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:56 PM PDT 24
Peak memory	200664 kb
Host	smart-3834a2d0-1e9a-49f7-b614-4b2c05b63514
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248008935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.4248008935
Directory	/workspace/29.clkmgr_frequency/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency_timeout.4040617674
Short name	T23
Test name
Test status
Simulation time	497297004 ps
CPU time	3.59 seconds
Started	Mar 26 12:38:37 PM PDT 24
Finished	Mar 26 12:38:40 PM PDT 24
Peak memory	200624 kb
Host	smart-e2b2d879-3d50-4571-8915-8afa1a3b19fa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040617674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t imeout.4040617674
Directory	/workspace/29.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/29.clkmgr_idle_intersig_mubi.3531558695
Short name	T831
Test name
Test status
Simulation time	24335719 ps
CPU time	0.84 seconds
Started	Mar 26 12:38:41 PM PDT 24
Finished	Mar 26 12:38:42 PM PDT 24
Peak memory	200624 kb
Host	smart-b8cd1889-1627-4cb3-b41d-f9ff3df319fa
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531558695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.3531558695
Directory	/workspace/29.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.3461273272
Short name	T533
Test name
Test status
Simulation time	82329215 ps
CPU time	0.97 seconds
Started	Mar 26 12:38:35 PM PDT 24
Finished	Mar 26 12:38:36 PM PDT 24
Peak memory	200580 kb
Host	smart-b72c86a8-0dcf-43ab-b96a-b60c054c5673
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461273272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_clk_byp_req_intersig_mubi.3461273272
Directory	/workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.3532633647
Short name	T392
Test name
Test status
Simulation time	60554616 ps
CPU time	0.93 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200564 kb
Host	smart-d767e5b8-8625-4ba1-a4fd-6dd345429c06
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532633647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_ctrl_intersig_mubi.3532633647
Directory	/workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_peri.4065175377
Short name	T606
Test name
Test status
Simulation time	17442343 ps
CPU time	0.79 seconds
Started	Mar 26 12:38:41 PM PDT 24
Finished	Mar 26 12:38:42 PM PDT 24
Peak memory	200624 kb
Host	smart-510846ed-16b3-42db-80cd-d28fa2955a19
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065175377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.4065175377
Directory	/workspace/29.clkmgr_peri/latest

Test location	/workspace/coverage/default/29.clkmgr_regwen.2367366880
Short name	T344
Test name
Test status
Simulation time	315505005 ps
CPU time	1.78 seconds
Started	Mar 26 12:38:40 PM PDT 24
Finished	Mar 26 12:38:42 PM PDT 24
Peak memory	200576 kb
Host	smart-243ea5b9-9934-4df7-ae72-dc226025edd4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367366880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.2367366880
Directory	/workspace/29.clkmgr_regwen/latest

Test location	/workspace/coverage/default/29.clkmgr_smoke.4115853620
Short name	T310
Test name
Test status
Simulation time	17423495 ps
CPU time	0.82 seconds
Started	Mar 26 12:38:46 PM PDT 24
Finished	Mar 26 12:38:47 PM PDT 24
Peak memory	200568 kb
Host	smart-19cbf647-5fe2-4fbe-9841-d53aed4873f8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115853620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.4115853620
Directory	/workspace/29.clkmgr_smoke/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all.1460264535
Short name	T443
Test name
Test status
Simulation time	3516251926 ps
CPU time	26.15 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:39:09 PM PDT 24
Peak memory	200752 kb
Host	smart-ebd4190e-fc9a-4453-9d88-e1c4b4e5d062
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460264535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.1460264535
Directory	/workspace/29.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.638958192
Short name	T432
Test name
Test status
Simulation time	69045838656 ps
CPU time	463.66 seconds
Started	Mar 26 12:38:41 PM PDT 24
Finished	Mar 26 12:46:24 PM PDT 24
Peak memory	209260 kb
Host	smart-d07a5164-6006-453c-ba6e-668aa15b6593
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=638958192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.638958192
Directory	/workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.clkmgr_trans.3100543590
Short name	T275
Test name
Test status
Simulation time	455899945 ps
CPU time	2.2 seconds
Started	Mar 26 12:38:35 PM PDT 24
Finished	Mar 26 12:38:37 PM PDT 24
Peak memory	200580 kb
Host	smart-b5c78144-caae-42ae-ba56-efffa8d06893
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100543590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.3100543590
Directory	/workspace/29.clkmgr_trans/latest

Test location	/workspace/coverage/default/3.clkmgr_alert_test.4245603105
Short name	T797
Test name
Test status
Simulation time	125932893 ps
CPU time	1.05 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200608 kb
Host	smart-5d817c50-18ee-43e6-9b56-066be8d06c1f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245603105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm gr_alert_test.4245603105
Directory	/workspace/3.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1692996777
Short name	T503
Test name
Test status
Simulation time	40225258 ps
CPU time	0.97 seconds
Started	Mar 26 12:37:28 PM PDT 24
Finished	Mar 26 12:37:29 PM PDT 24
Peak memory	200560 kb
Host	smart-661579b7-ef13-4757-93b4-e6aa1333f48e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692996777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.1692996777
Directory	/workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_status.32983080
Short name	T789
Test name
Test status
Simulation time	26951585 ps
CPU time	0.74 seconds
Started	Mar 26 12:37:30 PM PDT 24
Finished	Mar 26 12:37:31 PM PDT 24
Peak memory	199540 kb
Host	smart-936b687e-fdc6-45b3-b082-4294649cc4fa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32983080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.32983080
Directory	/workspace/3.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/3.clkmgr_div_intersig_mubi.3116432220
Short name	T850
Test name
Test status
Simulation time	20967691 ps
CPU time	0.85 seconds
Started	Mar 26 12:37:31 PM PDT 24
Finished	Mar 26 12:37:32 PM PDT 24
Peak memory	200580 kb
Host	smart-4849fb6a-fad9-4c8d-9fbf-5b6a988d1da7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116432220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.3116432220
Directory	/workspace/3.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_extclk.71419018
Short name	T548
Test name
Test status
Simulation time	13877775 ps
CPU time	0.71 seconds
Started	Mar 26 12:37:29 PM PDT 24
Finished	Mar 26 12:37:30 PM PDT 24
Peak memory	200584 kb
Host	smart-d08f2507-725c-484e-b046-6453ab572da0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71419018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.71419018
Directory	/workspace/3.clkmgr_extclk/latest

Test location	/workspace/coverage/default/3.clkmgr_frequency.266635303
Short name	T293
Test name
Test status
Simulation time	2182899430 ps
CPU time	9.51 seconds
Started	Mar 26 12:37:29 PM PDT 24
Finished	Mar 26 12:37:39 PM PDT 24
Peak memory	200860 kb
Host	smart-874f8c09-24ee-4a92-b606-7ee2ed4da100
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266635303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.266635303
Directory	/workspace/3.clkmgr_frequency/latest

Test location	/workspace/coverage/default/3.clkmgr_idle_intersig_mubi.1884308381
Short name	T109
Test name
Test status
Simulation time	43434111 ps
CPU time	0.91 seconds
Started	Mar 26 12:37:29 PM PDT 24
Finished	Mar 26 12:37:30 PM PDT 24
Peak memory	200568 kb
Host	smart-9d48ab3f-b679-41bb-b6b1-5e7a295c5b0e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884308381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.1884308381
Directory	/workspace/3.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.1509539553
Short name	T696
Test name
Test status
Simulation time	39073705 ps
CPU time	0.79 seconds
Started	Mar 26 12:37:29 PM PDT 24
Finished	Mar 26 12:37:30 PM PDT 24
Peak memory	200580 kb
Host	smart-9831dac8-abe9-4ad2-8e03-1a10563c3b46
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509539553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.clkmgr_lc_clk_byp_req_intersig_mubi.1509539553
Directory	/workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.1553903451
Short name	T582
Test name
Test status
Simulation time	23617405 ps
CPU time	0.85 seconds
Started	Mar 26 12:37:31 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200556 kb
Host	smart-5760d6e3-2e30-4bac-b137-e402a43c3b50
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553903451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.clkmgr_lc_ctrl_intersig_mubi.1553903451
Directory	/workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_peri.1659833983
Short name	T625
Test name
Test status
Simulation time	50845965 ps
CPU time	0.85 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200572 kb
Host	smart-6260200e-cb55-4300-bfb6-bf1c06a41f9b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659833983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.1659833983
Directory	/workspace/3.clkmgr_peri/latest

Test location	/workspace/coverage/default/3.clkmgr_regwen.781690181
Short name	T631
Test name
Test status
Simulation time	1153788280 ps
CPU time	5.35 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:38 PM PDT 24
Peak memory	200720 kb
Host	smart-6994e67c-bafd-4f00-a307-b04cc26a0a36
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781690181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.781690181
Directory	/workspace/3.clkmgr_regwen/latest

Test location	/workspace/coverage/default/3.clkmgr_sec_cm.881886002
Short name	T48
Test name
Test status
Simulation time	217339547 ps
CPU time	1.94 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:34 PM PDT 24
Peak memory	215920 kb
Host	smart-25c61056-b939-401a-9ddd-15cf52466199
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881886002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr _sec_cm.881886002
Directory	/workspace/3.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/3.clkmgr_smoke.1860515670
Short name	T795
Test name
Test status
Simulation time	96928729 ps
CPU time	1.05 seconds
Started	Mar 26 12:37:29 PM PDT 24
Finished	Mar 26 12:37:31 PM PDT 24
Peak memory	200584 kb
Host	smart-959abb36-b255-41b4-bf13-ff711c2776bc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860515670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.1860515670
Directory	/workspace/3.clkmgr_smoke/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all.3557925074
Short name	T684
Test name
Test status
Simulation time	58969803 ps
CPU time	1.3 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200556 kb
Host	smart-a65ea4eb-b27d-4c34-904b-de1d5eaf6f57
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557925074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.3557925074
Directory	/workspace/3.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.4082196549
Short name	T833
Test name
Test status
Simulation time	10531814154 ps
CPU time	164.02 seconds
Started	Mar 26 12:37:28 PM PDT 24
Finished	Mar 26 12:40:13 PM PDT 24
Peak memory	209284 kb
Host	smart-bd983b73-15d5-438d-a208-6f8873953387
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4082196549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.4082196549
Directory	/workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.clkmgr_trans.3842916514
Short name	T300
Test name
Test status
Simulation time	25476961 ps
CPU time	0.87 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200568 kb
Host	smart-0542e0d3-322f-4006-8f25-958fb54aad31
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842916514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.3842916514
Directory	/workspace/3.clkmgr_trans/latest

Test location	/workspace/coverage/default/30.clkmgr_alert_test.3750302977
Short name	T754
Test name
Test status
Simulation time	16838838 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200616 kb
Host	smart-96612ee4-5a50-4f3e-99b9-616e747094c2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750302977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk mgr_alert_test.3750302977
Directory	/workspace/30.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.2031488583
Short name	T377
Test name
Test status
Simulation time	112187489 ps
CPU time	1.11 seconds
Started	Mar 26 12:38:34 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200604 kb
Host	smart-4f4fb09b-ab90-48c5-8c14-c7248aece4a6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031488583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.2031488583
Directory	/workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_status.3484738056
Short name	T697
Test name
Test status
Simulation time	25293050 ps
CPU time	0.76 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	199472 kb
Host	smart-fb3a0cc6-17fc-4075-a955-7b27ac66c7af
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484738056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.3484738056
Directory	/workspace/30.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/30.clkmgr_div_intersig_mubi.400442105
Short name	T638
Test name
Test status
Simulation time	20057997 ps
CPU time	0.76 seconds
Started	Mar 26 12:38:39 PM PDT 24
Finished	Mar 26 12:38:40 PM PDT 24
Peak memory	200576 kb
Host	smart-4547bc04-40da-49f4-9926-08c14a37d7c1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400442105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.clkmgr_div_intersig_mubi.400442105
Directory	/workspace/30.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_extclk.3932279419
Short name	T809
Test name
Test status
Simulation time	69358440 ps
CPU time	0.95 seconds
Started	Mar 26 12:38:40 PM PDT 24
Finished	Mar 26 12:38:41 PM PDT 24
Peak memory	200628 kb
Host	smart-8edeab57-58a5-4076-9cc3-3914d490bc54
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932279419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.3932279419
Directory	/workspace/30.clkmgr_extclk/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency.3472673050
Short name	T539
Test name
Test status
Simulation time	1642460751 ps
CPU time	12.52 seconds
Started	Mar 26 12:38:40 PM PDT 24
Finished	Mar 26 12:38:52 PM PDT 24
Peak memory	200640 kb
Host	smart-64cf134f-7cc3-4578-8977-cf88ef272490
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472673050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.3472673050
Directory	/workspace/30.clkmgr_frequency/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency_timeout.737049994
Short name	T554
Test name
Test status
Simulation time	1696280902 ps
CPU time	12.08 seconds
Started	Mar 26 12:38:51 PM PDT 24
Finished	Mar 26 12:39:03 PM PDT 24
Peak memory	200620 kb
Host	smart-c7e8f4de-20ab-413a-bff2-d67404a286b6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737049994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_ti meout.737049994
Directory	/workspace/30.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/30.clkmgr_idle_intersig_mubi.1750269761
Short name	T468
Test name
Test status
Simulation time	20065044 ps
CPU time	0.7 seconds
Started	Mar 26 12:38:32 PM PDT 24
Finished	Mar 26 12:38:33 PM PDT 24
Peak memory	200380 kb
Host	smart-75dfdb3c-ad4f-4444-9a37-779590ae9e03
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750269761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.1750269761
Directory	/workspace/30.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.705803135
Short name	T150
Test name
Test status
Simulation time	156829745 ps
CPU time	1.1 seconds
Started	Mar 26 12:38:35 PM PDT 24
Finished	Mar 26 12:38:37 PM PDT 24
Peak memory	200592 kb
Host	smart-36979ea1-4a9a-4f42-96a2-e8a44ec395f0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705803135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.clkmgr_lc_clk_byp_req_intersig_mubi.705803135
Directory	/workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.867186892
Short name	T788
Test name
Test status
Simulation time	36802180 ps
CPU time	0.84 seconds
Started	Mar 26 12:38:33 PM PDT 24
Finished	Mar 26 12:38:34 PM PDT 24
Peak memory	200588 kb
Host	smart-1a91ab2b-8c02-4d9f-91ce-518859ab2a2e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867186892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.clkmgr_lc_ctrl_intersig_mubi.867186892
Directory	/workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_peri.3341380637
Short name	T562
Test name
Test status
Simulation time	26108083 ps
CPU time	0.79 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200548 kb
Host	smart-24e9425e-eb94-4d96-945b-88e41acadf0c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341380637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.3341380637
Directory	/workspace/30.clkmgr_peri/latest

Test location	/workspace/coverage/default/30.clkmgr_regwen.2538153786
Short name	T80
Test name
Test status
Simulation time	904147846 ps
CPU time	3.73 seconds
Started	Mar 26 12:38:36 PM PDT 24
Finished	Mar 26 12:38:40 PM PDT 24
Peak memory	200724 kb
Host	smart-70f04022-498a-4017-a3bf-5c39b8c1e298
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538153786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.2538153786
Directory	/workspace/30.clkmgr_regwen/latest

Test location	/workspace/coverage/default/30.clkmgr_smoke.2053572987
Short name	T814
Test name
Test status
Simulation time	28482972 ps
CPU time	0.83 seconds
Started	Mar 26 12:38:44 PM PDT 24
Finished	Mar 26 12:38:45 PM PDT 24
Peak memory	200548 kb
Host	smart-6ed44a80-c37e-41fe-bbb3-4845722b7440
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053572987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.2053572987
Directory	/workspace/30.clkmgr_smoke/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all.3057427409
Short name	T746
Test name
Test status
Simulation time	3207944644 ps
CPU time	22.26 seconds
Started	Mar 26 12:38:39 PM PDT 24
Finished	Mar 26 12:39:02 PM PDT 24
Peak memory	200916 kb
Host	smart-7ac92d14-4b3c-4e5a-907d-97d26b23715f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057427409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.3057427409
Directory	/workspace/30.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.2282513196
Short name	T255
Test name
Test status
Simulation time	40243050649 ps
CPU time	213.83 seconds
Started	Mar 26 12:38:39 PM PDT 24
Finished	Mar 26 12:42:13 PM PDT 24
Peak memory	209224 kb
Host	smart-9b2adb0d-897d-4b29-b17d-76092444e052
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2282513196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.2282513196
Directory	/workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.clkmgr_trans.3110677151
Short name	T559
Test name
Test status
Simulation time	30150316 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200532 kb
Host	smart-18677180-eb6c-47a1-8062-c05f6f993442
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110677151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.3110677151
Directory	/workspace/30.clkmgr_trans/latest

Test location	/workspace/coverage/default/31.clkmgr_alert_test.4005375372
Short name	T671
Test name
Test status
Simulation time	14832061 ps
CPU time	0.72 seconds
Started	Mar 26 12:38:41 PM PDT 24
Finished	Mar 26 12:38:42 PM PDT 24
Peak memory	200696 kb
Host	smart-2082f1e0-0ff1-448e-a096-d2cc0f2fd766
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005375372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk mgr_alert_test.4005375372
Directory	/workspace/31.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.2985239321
Short name	T90
Test name
Test status
Simulation time	88803208 ps
CPU time	1.02 seconds
Started	Mar 26 12:38:36 PM PDT 24
Finished	Mar 26 12:38:37 PM PDT 24
Peak memory	200572 kb
Host	smart-b815e968-2c99-4ee0-aa8f-23c2a31e9a8a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985239321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.2985239321
Directory	/workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_status.221280774
Short name	T607
Test name
Test status
Simulation time	27161380 ps
CPU time	0.74 seconds
Started	Mar 26 12:38:34 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200500 kb
Host	smart-5c6e7949-77af-42bb-8d1d-d2c6e024bf6a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221280774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.221280774
Directory	/workspace/31.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/31.clkmgr_div_intersig_mubi.226958372
Short name	T33
Test name
Test status
Simulation time	69768519 ps
CPU time	1 seconds
Started	Mar 26 12:38:36 PM PDT 24
Finished	Mar 26 12:38:37 PM PDT 24
Peak memory	200568 kb
Host	smart-8e5a701d-354c-41d6-89cb-884cba3ebac7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226958372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.clkmgr_div_intersig_mubi.226958372
Directory	/workspace/31.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_extclk.1966044908
Short name	T730
Test name
Test status
Simulation time	53959664 ps
CPU time	1.07 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200560 kb
Host	smart-ff96ff3f-6d13-46fb-9336-100af044ab6d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966044908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.1966044908
Directory	/workspace/31.clkmgr_extclk/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency.3074373897
Short name	T683
Test name
Test status
Simulation time	556970759 ps
CPU time	4.55 seconds
Started	Mar 26 12:38:42 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200520 kb
Host	smart-47da5708-833a-44b5-9358-415242ea0197
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074373897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.3074373897
Directory	/workspace/31.clkmgr_frequency/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency_timeout.2382799143
Short name	T601
Test name
Test status
Simulation time	2423565348 ps
CPU time	12.94 seconds
Started	Mar 26 12:38:37 PM PDT 24
Finished	Mar 26 12:38:50 PM PDT 24
Peak memory	200888 kb
Host	smart-3b7b8677-74c8-4da5-9df0-520c45f0ad51
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382799143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t imeout.2382799143
Directory	/workspace/31.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.2084360481
Short name	T549
Test name
Test status
Simulation time	19380733 ps
CPU time	0.84 seconds
Started	Mar 26 12:38:35 PM PDT 24
Finished	Mar 26 12:38:36 PM PDT 24
Peak memory	200576 kb
Host	smart-a4918fa2-3ec6-406e-8e6e-846515dfdb5f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084360481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 31.clkmgr_lc_clk_byp_req_intersig_mubi.2084360481
Directory	/workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.893887910
Short name	T705
Test name
Test status
Simulation time	20447991 ps
CPU time	0.81 seconds
Started	Mar 26 12:38:41 PM PDT 24
Finished	Mar 26 12:38:41 PM PDT 24
Peak memory	200632 kb
Host	smart-d6a00bb3-d7eb-425c-94ba-559d3c0b1862
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893887910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.clkmgr_lc_ctrl_intersig_mubi.893887910
Directory	/workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_peri.31534998
Short name	T514
Test name
Test status
Simulation time	25603586 ps
CPU time	0.72 seconds
Started	Mar 26 12:38:34 PM PDT 24
Finished	Mar 26 12:38:35 PM PDT 24
Peak memory	200620 kb
Host	smart-c2824ecc-40ff-441c-bb44-b9dee288eebe
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31534998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.31534998
Directory	/workspace/31.clkmgr_peri/latest

Test location	/workspace/coverage/default/31.clkmgr_regwen.838775014
Short name	T351
Test name
Test status
Simulation time	1339377051 ps
CPU time	4.8 seconds
Started	Mar 26 12:38:35 PM PDT 24
Finished	Mar 26 12:38:40 PM PDT 24
Peak memory	200676 kb
Host	smart-68438364-8b3a-4a08-9065-604057cb5e92
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838775014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.838775014
Directory	/workspace/31.clkmgr_regwen/latest

Test location	/workspace/coverage/default/31.clkmgr_smoke.4228810069
Short name	T597
Test name
Test status
Simulation time	66484996 ps
CPU time	0.98 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200580 kb
Host	smart-ed3e2184-bc32-4830-bd22-72942fb345c3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228810069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.4228810069
Directory	/workspace/31.clkmgr_smoke/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all.2477639447
Short name	T336
Test name
Test status
Simulation time	3485474130 ps
CPU time	25.55 seconds
Started	Mar 26 12:38:38 PM PDT 24
Finished	Mar 26 12:39:04 PM PDT 24
Peak memory	200888 kb
Host	smart-2dc8ec93-bf46-4213-8e37-c8ae5fa85b01
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477639447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.2477639447
Directory	/workspace/31.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.3778065452
Short name	T497
Test name
Test status
Simulation time	28721805724 ps
CPU time	460.07 seconds
Started	Mar 26 12:38:37 PM PDT 24
Finished	Mar 26 12:46:17 PM PDT 24
Peak memory	209252 kb
Host	smart-d211e9a4-8951-4c92-9512-627a87cf8b4e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3778065452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.3778065452
Directory	/workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.clkmgr_trans.3626272177
Short name	T75
Test name
Test status
Simulation time	237278835 ps
CPU time	1.47 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200556 kb
Host	smart-d3d50edc-c490-4d2a-9c71-d137061c3593
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626272177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.3626272177
Directory	/workspace/31.clkmgr_trans/latest

Test location	/workspace/coverage/default/32.clkmgr_alert_test.2802112212
Short name	T510
Test name
Test status
Simulation time	45314444 ps
CPU time	0.74 seconds
Started	Mar 26 12:38:44 PM PDT 24
Finished	Mar 26 12:38:45 PM PDT 24
Peak memory	200648 kb
Host	smart-67130f43-30b6-4077-82fe-60b0198a9a7b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802112212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk mgr_alert_test.2802112212
Directory	/workspace/32.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.3951004173
Short name	T89
Test name
Test status
Simulation time	21589243 ps
CPU time	0.84 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:43 PM PDT 24
Peak memory	200596 kb
Host	smart-55289863-f806-410a-ba11-8befd28f4e25
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951004173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.3951004173
Directory	/workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_status.3893354754
Short name	T792
Test name
Test status
Simulation time	17699648 ps
CPU time	0.73 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200508 kb
Host	smart-d76868b2-9224-4455-a10e-91e8b03743dd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893354754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.3893354754
Directory	/workspace/32.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/32.clkmgr_div_intersig_mubi.738868967
Short name	T615
Test name
Test status
Simulation time	42658689 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:42 PM PDT 24
Finished	Mar 26 12:38:42 PM PDT 24
Peak memory	200568 kb
Host	smart-7f7496cc-4023-408e-9d33-3671e01e2daf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738868967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.clkmgr_div_intersig_mubi.738868967
Directory	/workspace/32.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_extclk.3977917095
Short name	T174
Test name
Test status
Simulation time	61491484 ps
CPU time	0.91 seconds
Started	Mar 26 12:38:41 PM PDT 24
Finished	Mar 26 12:38:42 PM PDT 24
Peak memory	200564 kb
Host	smart-93759329-b0ee-4f01-955a-27dec0fb42db
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977917095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.3977917095
Directory	/workspace/32.clkmgr_extclk/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency.668276030
Short name	T345
Test name
Test status
Simulation time	1886685195 ps
CPU time	10.57 seconds
Started	Mar 26 12:38:46 PM PDT 24
Finished	Mar 26 12:38:57 PM PDT 24
Peak memory	200652 kb
Host	smart-50f00ebb-b648-42ab-9f82-0b69079e2ed1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668276030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.668276030
Directory	/workspace/32.clkmgr_frequency/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency_timeout.686655970
Short name	T658
Test name
Test status
Simulation time	2423995439 ps
CPU time	15.4 seconds
Started	Mar 26 12:38:44 PM PDT 24
Finished	Mar 26 12:39:00 PM PDT 24
Peak memory	200908 kb
Host	smart-118d75fb-3979-4a03-a56d-4daa799a44c8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686655970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_ti meout.686655970
Directory	/workspace/32.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/32.clkmgr_idle_intersig_mubi.2272055485
Short name	T446
Test name
Test status
Simulation time	27470445 ps
CPU time	0.78 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200616 kb
Host	smart-280d2329-9c0b-4c7f-881e-0a281f43c7e1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272055485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_idle_intersig_mubi.2272055485
Directory	/workspace/32.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.2250644328
Short name	T570
Test name
Test status
Simulation time	26608165 ps
CPU time	0.78 seconds
Started	Mar 26 12:38:44 PM PDT 24
Finished	Mar 26 12:38:45 PM PDT 24
Peak memory	200632 kb
Host	smart-1a1b96c0-161b-4305-9af9-3995c60bec69
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250644328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.clkmgr_lc_clk_byp_req_intersig_mubi.2250644328
Directory	/workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.1806237707
Short name	T234
Test name
Test status
Simulation time	17752752 ps
CPU time	0.75 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200568 kb
Host	smart-9e4c5ced-9dbf-4ac3-a98e-a5aaf29aedcb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806237707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.clkmgr_lc_ctrl_intersig_mubi.1806237707
Directory	/workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_peri.1177850348
Short name	T387
Test name
Test status
Simulation time	19203312 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:54 PM PDT 24
Finished	Mar 26 12:38:55 PM PDT 24
Peak memory	200288 kb
Host	smart-b8681946-b832-49d2-8444-774de284f159
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177850348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.1177850348
Directory	/workspace/32.clkmgr_peri/latest

Test location	/workspace/coverage/default/32.clkmgr_regwen.1113569819
Short name	T278
Test name
Test status
Simulation time	773809385 ps
CPU time	3.3 seconds
Started	Mar 26 12:38:46 PM PDT 24
Finished	Mar 26 12:38:49 PM PDT 24
Peak memory	200652 kb
Host	smart-353a7dd2-883a-4094-9432-ee83645d1e08
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113569819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.1113569819
Directory	/workspace/32.clkmgr_regwen/latest

Test location	/workspace/coverage/default/32.clkmgr_smoke.1621734517
Short name	T142
Test name
Test status
Simulation time	22497376 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:49 PM PDT 24
Finished	Mar 26 12:38:50 PM PDT 24
Peak memory	200664 kb
Host	smart-5015eb9a-29ff-4895-a4d3-be1b99636d48
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621734517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.1621734517
Directory	/workspace/32.clkmgr_smoke/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all.1218376266
Short name	T670
Test name
Test status
Simulation time	7731189463 ps
CPU time	57.07 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:39:42 PM PDT 24
Peak memory	200772 kb
Host	smart-8c27d16b-bcbb-465d-9b4a-f468347d5ed5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218376266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.1218376266
Directory	/workspace/32.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.3949534408
Short name	T531
Test name
Test status
Simulation time	33723008974 ps
CPU time	254.01 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:42:57 PM PDT 24
Peak memory	209212 kb
Host	smart-f84700a6-61f1-4152-80a2-e7f65ae214f4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3949534408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.3949534408
Directory	/workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.clkmgr_trans.1026852231
Short name	T693
Test name
Test status
Simulation time	32315067 ps
CPU time	0.97 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200644 kb
Host	smart-cafcb8a0-1684-418e-9ae0-7f6b66c372bc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026852231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.1026852231
Directory	/workspace/32.clkmgr_trans/latest

Test location	/workspace/coverage/default/33.clkmgr_alert_test.775442190
Short name	T238
Test name
Test status
Simulation time	26358489 ps
CPU time	0.81 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200596 kb
Host	smart-1e5f57b8-8e03-4551-91cb-55ecd884a739
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775442190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkm gr_alert_test.775442190
Directory	/workspace/33.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.1601359672
Short name	T767
Test name
Test status
Simulation time	90744210 ps
CPU time	1.06 seconds
Started	Mar 26 12:38:49 PM PDT 24
Finished	Mar 26 12:38:50 PM PDT 24
Peak memory	200656 kb
Host	smart-ff89ff79-43a7-4957-872b-7db593fab051
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601359672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.1601359672
Directory	/workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_status.2010924075
Short name	T464
Test name
Test status
Simulation time	62288103 ps
CPU time	0.8 seconds
Started	Mar 26 12:38:47 PM PDT 24
Finished	Mar 26 12:38:48 PM PDT 24
Peak memory	199492 kb
Host	smart-bb57386f-e2e0-4143-9455-342f9cf4ebe5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010924075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.2010924075
Directory	/workspace/33.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/33.clkmgr_div_intersig_mubi.1032788540
Short name	T397
Test name
Test status
Simulation time	58966055 ps
CPU time	0.93 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:47 PM PDT 24
Peak memory	200640 kb
Host	smart-61d95d57-5ee8-49c5-b008-17a96535b4ad
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032788540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.1032788540
Directory	/workspace/33.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_extclk.1906962532
Short name	T210
Test name
Test status
Simulation time	34849562 ps
CPU time	0.82 seconds
Started	Mar 26 12:38:47 PM PDT 24
Finished	Mar 26 12:38:48 PM PDT 24
Peak memory	200496 kb
Host	smart-7eeb9e7d-8ca7-4066-9918-54b15f6294be
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906962532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.1906962532
Directory	/workspace/33.clkmgr_extclk/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency.655023606
Short name	T415
Test name
Test status
Simulation time	1283788077 ps
CPU time	7.66 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:51 PM PDT 24
Peak memory	200564 kb
Host	smart-1a331a98-793f-478c-aea5-c6d22750391f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655023606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.655023606
Directory	/workspace/33.clkmgr_frequency/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency_timeout.3504236827
Short name	T721
Test name
Test status
Simulation time	1229541542 ps
CPU time	6.51 seconds
Started	Mar 26 12:38:47 PM PDT 24
Finished	Mar 26 12:38:54 PM PDT 24
Peak memory	200648 kb
Host	smart-2800dd1b-08bf-4dc0-934b-5fc027782f13
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504236827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t imeout.3504236827
Directory	/workspace/33.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/33.clkmgr_idle_intersig_mubi.2721481038
Short name	T303
Test name
Test status
Simulation time	28620210 ps
CPU time	0.86 seconds
Started	Mar 26 12:38:44 PM PDT 24
Finished	Mar 26 12:38:45 PM PDT 24
Peak memory	200600 kb
Host	smart-1fe85715-49e5-4e52-b73c-318286e35481
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721481038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.2721481038
Directory	/workspace/33.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.3182625454
Short name	T751
Test name
Test status
Simulation time	17034588 ps
CPU time	0.79 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200188 kb
Host	smart-c5f2a077-502d-4eb2-bc0e-100bcb9791e9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182625454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_clk_byp_req_intersig_mubi.3182625454
Directory	/workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1166630438
Short name	T416
Test name
Test status
Simulation time	35601915 ps
CPU time	0.86 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200564 kb
Host	smart-b15212d1-c2b0-425d-b0a4-6a14c624a56f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166630438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_ctrl_intersig_mubi.1166630438
Directory	/workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_peri.2420368718
Short name	T456
Test name
Test status
Simulation time	156488165 ps
CPU time	1.13 seconds
Started	Mar 26 12:38:54 PM PDT 24
Finished	Mar 26 12:38:55 PM PDT 24
Peak memory	200404 kb
Host	smart-e60da45d-d8a1-4d94-b70e-2890b534be86
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420368718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.2420368718
Directory	/workspace/33.clkmgr_peri/latest

Test location	/workspace/coverage/default/33.clkmgr_regwen.3334530115
Short name	T723
Test name
Test status
Simulation time	290960608 ps
CPU time	1.76 seconds
Started	Mar 26 12:38:52 PM PDT 24
Finished	Mar 26 12:38:54 PM PDT 24
Peak memory	200504 kb
Host	smart-17b85bb4-7116-4cf8-bdec-79f187c69802
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334530115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.3334530115
Directory	/workspace/33.clkmgr_regwen/latest

Test location	/workspace/coverage/default/33.clkmgr_smoke.1676512537
Short name	T461
Test name
Test status
Simulation time	40893581 ps
CPU time	0.95 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200180 kb
Host	smart-e372702f-267b-4c95-9b41-6698e8f88a02
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676512537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.1676512537
Directory	/workspace/33.clkmgr_smoke/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all.4175828945
Short name	T454
Test name
Test status
Simulation time	6681821863 ps
CPU time	49.21 seconds
Started	Mar 26 12:38:44 PM PDT 24
Finished	Mar 26 12:39:34 PM PDT 24
Peak memory	201148 kb
Host	smart-d3658a9f-cf35-401f-8755-65841921a178
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175828945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.4175828945
Directory	/workspace/33.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.2651881750
Short name	T630
Test name
Test status
Simulation time	50986122997 ps
CPU time	553.28 seconds
Started	Mar 26 12:38:44 PM PDT 24
Finished	Mar 26 12:47:57 PM PDT 24
Peak memory	209252 kb
Host	smart-d38d1573-ce1f-40a7-82a0-199711e3792e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2651881750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.2651881750
Directory	/workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.clkmgr_trans.4015758113
Short name	T623
Test name
Test status
Simulation time	14581722 ps
CPU time	0.72 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200492 kb
Host	smart-2fc69254-2fd7-425f-831b-122560a9c463
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015758113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.4015758113
Directory	/workspace/33.clkmgr_trans/latest

Test location	/workspace/coverage/default/34.clkmgr_alert_test.2747467667
Short name	T224
Test name
Test status
Simulation time	27484494 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:46 PM PDT 24
Finished	Mar 26 12:38:47 PM PDT 24
Peak memory	200620 kb
Host	smart-cb27e3f8-f411-4667-a46b-089e47753d46
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747467667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk mgr_alert_test.2747467667
Directory	/workspace/34.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.903315039
Short name	T21
Test name
Test status
Simulation time	31099560 ps
CPU time	0.95 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200584 kb
Host	smart-deb5455f-7dba-446a-b420-a0e92368f5ca
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903315039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.903315039
Directory	/workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_status.4155105334
Short name	T162
Test name
Test status
Simulation time	37730311 ps
CPU time	0.7 seconds
Started	Mar 26 12:38:42 PM PDT 24
Finished	Mar 26 12:38:43 PM PDT 24
Peak memory	199512 kb
Host	smart-e9fad42e-7d5a-43ab-821b-0102d00c5bb6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155105334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.4155105334
Directory	/workspace/34.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/34.clkmgr_div_intersig_mubi.500169395
Short name	T364
Test name
Test status
Simulation time	62854509 ps
CPU time	0.99 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200660 kb
Host	smart-3bd4c7e7-147e-4647-a559-d1b211b6a64e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500169395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.clkmgr_div_intersig_mubi.500169395
Directory	/workspace/34.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_extclk.3580820463
Short name	T307
Test name
Test status
Simulation time	16531396 ps
CPU time	0.74 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200544 kb
Host	smart-9c5e0e2e-c5b8-43da-a9f2-c2869e0e20d8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580820463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.3580820463
Directory	/workspace/34.clkmgr_extclk/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency.3193997737
Short name	T640
Test name
Test status
Simulation time	1638461190 ps
CPU time	12.84 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:58 PM PDT 24
Peak memory	200660 kb
Host	smart-a6b4c921-4810-456d-855a-499b0dcc920f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193997737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.3193997737
Directory	/workspace/34.clkmgr_frequency/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency_timeout.2827307175
Short name	T433
Test name
Test status
Simulation time	620330164 ps
CPU time	4.8 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:50 PM PDT 24
Peak memory	200604 kb
Host	smart-dfb8956d-4b55-417c-979d-b22eeb280378
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827307175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t imeout.2827307175
Directory	/workspace/34.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/34.clkmgr_idle_intersig_mubi.3305094870
Short name	T265
Test name
Test status
Simulation time	126684737 ps
CPU time	1.31 seconds
Started	Mar 26 12:38:44 PM PDT 24
Finished	Mar 26 12:38:45 PM PDT 24
Peak memory	200524 kb
Host	smart-4609cf93-2f90-435b-b8d6-8a0c4e9254df
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305094870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.3305094870
Directory	/workspace/34.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.2160050293
Short name	T474
Test name
Test status
Simulation time	23681322 ps
CPU time	0.81 seconds
Started	Mar 26 12:38:44 PM PDT 24
Finished	Mar 26 12:38:45 PM PDT 24
Peak memory	200528 kb
Host	smart-62322482-a1e4-48ef-a7d5-2bbffbdd8594
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160050293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 34.clkmgr_lc_clk_byp_req_intersig_mubi.2160050293
Directory	/workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.2376414424
Short name	T429
Test name
Test status
Simulation time	26079759 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200648 kb
Host	smart-99f83fec-b671-4ec0-af36-2cd42397aa73
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376414424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 34.clkmgr_lc_ctrl_intersig_mubi.2376414424
Directory	/workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_peri.1431815434
Short name	T678
Test name
Test status
Simulation time	65411876 ps
CPU time	0.9 seconds
Started	Mar 26 12:38:47 PM PDT 24
Finished	Mar 26 12:38:48 PM PDT 24
Peak memory	200568 kb
Host	smart-a10e4f74-11ce-4c0b-ad60-755cbe07ceb4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431815434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.1431815434
Directory	/workspace/34.clkmgr_peri/latest

Test location	/workspace/coverage/default/34.clkmgr_regwen.2551418021
Short name	T10
Test name
Test status
Simulation time	582966667 ps
CPU time	3.74 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:49 PM PDT 24
Peak memory	200652 kb
Host	smart-9052242b-cba3-4501-847c-9d7bf384a668
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551418021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.2551418021
Directory	/workspace/34.clkmgr_regwen/latest

Test location	/workspace/coverage/default/34.clkmgr_smoke.1971995087
Short name	T191
Test name
Test status
Simulation time	66235045 ps
CPU time	0.96 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200564 kb
Host	smart-d3fc73fe-1ffc-4c35-8600-f0ae43771ced
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971995087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.1971995087
Directory	/workspace/34.clkmgr_smoke/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all.3814287255
Short name	T813
Test name
Test status
Simulation time	8264032984 ps
CPU time	27.76 seconds
Started	Mar 26 12:38:44 PM PDT 24
Finished	Mar 26 12:39:11 PM PDT 24
Peak memory	200900 kb
Host	smart-6f0a734e-ece1-42a5-9a7d-1cdcdf9710f6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814287255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.3814287255
Directory	/workspace/34.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.2404230462
Short name	T72
Test name
Test status
Simulation time	33994820759 ps
CPU time	522.79 seconds
Started	Mar 26 12:38:44 PM PDT 24
Finished	Mar 26 12:47:26 PM PDT 24
Peak memory	209688 kb
Host	smart-12dc8c72-a80b-42ee-b16f-6026eb1f6ec1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2404230462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.2404230462
Directory	/workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.clkmgr_trans.419129499
Short name	T342
Test name
Test status
Simulation time	24228311 ps
CPU time	0.74 seconds
Started	Mar 26 12:38:47 PM PDT 24
Finished	Mar 26 12:38:48 PM PDT 24
Peak memory	200524 kb
Host	smart-359ec811-acdd-4ddc-a9bd-1edd7f979b1f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419129499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.419129499
Directory	/workspace/34.clkmgr_trans/latest

Test location	/workspace/coverage/default/35.clkmgr_alert_test.1029562221
Short name	T667
Test name
Test status
Simulation time	15200970 ps
CPU time	0.74 seconds
Started	Mar 26 12:38:54 PM PDT 24
Finished	Mar 26 12:39:00 PM PDT 24
Peak memory	200636 kb
Host	smart-daecc91b-a822-4aa3-8e11-a1dc515b96bd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029562221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk mgr_alert_test.1029562221
Directory	/workspace/35.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.328436578
Short name	T832
Test name
Test status
Simulation time	31519366 ps
CPU time	0.84 seconds
Started	Mar 26 12:38:54 PM PDT 24
Finished	Mar 26 12:38:55 PM PDT 24
Peak memory	200464 kb
Host	smart-6950064b-ba4c-41ce-af1c-b258d308e5f2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328436578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.328436578
Directory	/workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_status.3628513006
Short name	T360
Test name
Test status
Simulation time	19229099 ps
CPU time	0.73 seconds
Started	Mar 26 12:38:43 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	200496 kb
Host	smart-44692cfa-cc47-4c6c-a13e-e240598f6170
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628513006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.3628513006
Directory	/workspace/35.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/35.clkmgr_div_intersig_mubi.1191075292
Short name	T504
Test name
Test status
Simulation time	15632486 ps
CPU time	0.72 seconds
Started	Mar 26 12:38:53 PM PDT 24
Finished	Mar 26 12:38:53 PM PDT 24
Peak memory	200404 kb
Host	smart-68933347-b2e2-402a-8a8e-d9c745ff4a84
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191075292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.1191075292
Directory	/workspace/35.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_extclk.136764865
Short name	T247
Test name
Test status
Simulation time	14537210 ps
CPU time	0.74 seconds
Started	Mar 26 12:38:53 PM PDT 24
Finished	Mar 26 12:38:54 PM PDT 24
Peak memory	200596 kb
Host	smart-a363852c-05b5-4998-b7ce-1e0d39a45030
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136764865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.136764865
Directory	/workspace/35.clkmgr_extclk/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency.1353453308
Short name	T113
Test name
Test status
Simulation time	1393473411 ps
CPU time	11.15 seconds
Started	Mar 26 12:38:52 PM PDT 24
Finished	Mar 26 12:39:03 PM PDT 24
Peak memory	200572 kb
Host	smart-777095d1-1b87-40b2-9f13-249ddd7eb69b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353453308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.1353453308
Directory	/workspace/35.clkmgr_frequency/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency_timeout.2247685528
Short name	T479
Test name
Test status
Simulation time	862396825 ps
CPU time	6.47 seconds
Started	Mar 26 12:38:46 PM PDT 24
Finished	Mar 26 12:38:53 PM PDT 24
Peak memory	200668 kb
Host	smart-2aa6af7c-8eab-46a7-9f23-f4e718169dea
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247685528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t imeout.2247685528
Directory	/workspace/35.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/35.clkmgr_idle_intersig_mubi.924809793
Short name	T490
Test name
Test status
Simulation time	87386680 ps
CPU time	1 seconds
Started	Mar 26 12:38:51 PM PDT 24
Finished	Mar 26 12:38:53 PM PDT 24
Peak memory	200012 kb
Host	smart-e5340309-b20e-4875-b1ce-765b91f4e800
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924809793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.clkmgr_idle_intersig_mubi.924809793
Directory	/workspace/35.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.392588800
Short name	T436
Test name
Test status
Simulation time	41564928 ps
CPU time	0.89 seconds
Started	Mar 26 12:38:54 PM PDT 24
Finished	Mar 26 12:38:55 PM PDT 24
Peak memory	200592 kb
Host	smart-a409271a-d25e-43bc-9299-c93332a470bf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392588800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.clkmgr_lc_clk_byp_req_intersig_mubi.392588800
Directory	/workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.1261562411
Short name	T22
Test name
Test status
Simulation time	64698683 ps
CPU time	0.97 seconds
Started	Mar 26 12:38:53 PM PDT 24
Finished	Mar 26 12:38:54 PM PDT 24
Peak memory	200572 kb
Host	smart-656d8e30-1d3c-4674-af96-44f581edb65a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261562411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.clkmgr_lc_ctrl_intersig_mubi.1261562411
Directory	/workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_peri.1422254147
Short name	T812
Test name
Test status
Simulation time	14850216 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:45 PM PDT 24
Finished	Mar 26 12:38:46 PM PDT 24
Peak memory	200636 kb
Host	smart-7b180416-cdeb-4866-9bc2-238648e2e7f0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422254147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.1422254147
Directory	/workspace/35.clkmgr_peri/latest

Test location	/workspace/coverage/default/35.clkmgr_regwen.1334292022
Short name	T634
Test name
Test status
Simulation time	99240273 ps
CPU time	1.15 seconds
Started	Mar 26 12:38:53 PM PDT 24
Finished	Mar 26 12:38:54 PM PDT 24
Peak memory	200536 kb
Host	smart-4ef1c87d-4dc0-411f-accd-419af58d15ae
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334292022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.1334292022
Directory	/workspace/35.clkmgr_regwen/latest

Test location	/workspace/coverage/default/35.clkmgr_smoke.478612381
Short name	T568
Test name
Test status
Simulation time	17879658 ps
CPU time	0.99 seconds
Started	Mar 26 12:38:46 PM PDT 24
Finished	Mar 26 12:38:47 PM PDT 24
Peak memory	200584 kb
Host	smart-f1446799-9000-49e3-b62d-fea40a68d69f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478612381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.478612381
Directory	/workspace/35.clkmgr_smoke/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all.3233234173
Short name	T78
Test name
Test status
Simulation time	1360721320 ps
CPU time	10.19 seconds
Started	Mar 26 12:38:53 PM PDT 24
Finished	Mar 26 12:39:04 PM PDT 24
Peak memory	200644 kb
Host	smart-f19aa758-eabe-4987-98ec-760fe28f2cd6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233234173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.3233234173
Directory	/workspace/35.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.626588890
Short name	T306
Test name
Test status
Simulation time	88722159479 ps
CPU time	651.7 seconds
Started	Mar 26 12:38:52 PM PDT 24
Finished	Mar 26 12:49:44 PM PDT 24
Peak memory	209188 kb
Host	smart-9c8baf55-166c-4fcc-b3b1-a8374fe68672
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=626588890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.626588890
Directory	/workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.clkmgr_trans.2182804146
Short name	T299
Test name
Test status
Simulation time	18199274 ps
CPU time	0.69 seconds
Started	Mar 26 12:38:49 PM PDT 24
Finished	Mar 26 12:38:50 PM PDT 24
Peak memory	200648 kb
Host	smart-496ac04c-d1a9-4b4e-b63f-9657ebb0f52d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182804146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.2182804146
Directory	/workspace/35.clkmgr_trans/latest

Test location	/workspace/coverage/default/36.clkmgr_alert_test.1553048720
Short name	T779
Test name
Test status
Simulation time	14023106 ps
CPU time	0.73 seconds
Started	Mar 26 12:39:01 PM PDT 24
Finished	Mar 26 12:39:03 PM PDT 24
Peak memory	200500 kb
Host	smart-f2e3af22-0ac3-4496-980e-b5266b5ecf21
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553048720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk mgr_alert_test.1553048720
Directory	/workspace/36.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.1793075819
Short name	T728
Test name
Test status
Simulation time	36183247 ps
CPU time	0.91 seconds
Started	Mar 26 12:38:50 PM PDT 24
Finished	Mar 26 12:38:51 PM PDT 24
Peak memory	199796 kb
Host	smart-09834c0f-0af5-4f85-bca7-0aa621cfda42
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793075819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.1793075819
Directory	/workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_status.50238031
Short name	T363
Test name
Test status
Simulation time	15665421 ps
CPU time	0.74 seconds
Started	Mar 26 12:38:50 PM PDT 24
Finished	Mar 26 12:38:51 PM PDT 24
Peak memory	199500 kb
Host	smart-90b7020e-28fc-4479-8a12-6efffa0b059c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50238031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.50238031
Directory	/workspace/36.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/36.clkmgr_div_intersig_mubi.4017334507
Short name	T289
Test name
Test status
Simulation time	188554563 ps
CPU time	1.24 seconds
Started	Mar 26 12:38:57 PM PDT 24
Finished	Mar 26 12:38:58 PM PDT 24
Peak memory	200548 kb
Host	smart-b1eae85b-df5e-4359-85fc-2f3dee170fca
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017334507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.4017334507
Directory	/workspace/36.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_extclk.3464606059
Short name	T561
Test name
Test status
Simulation time	216106323 ps
CPU time	1.28 seconds
Started	Mar 26 12:38:51 PM PDT 24
Finished	Mar 26 12:38:53 PM PDT 24
Peak memory	200028 kb
Host	smart-5292d76d-a4ad-452e-85fb-ea0163740cf1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464606059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.3464606059
Directory	/workspace/36.clkmgr_extclk/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency.2067974742
Short name	T251
Test name
Test status
Simulation time	328004038 ps
CPU time	1.73 seconds
Started	Mar 26 12:38:53 PM PDT 24
Finished	Mar 26 12:38:54 PM PDT 24
Peak memory	200404 kb
Host	smart-239a74cb-085e-49f2-a1d4-14c7ab84e6d9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067974742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.2067974742
Directory	/workspace/36.clkmgr_frequency/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency_timeout.3767188976
Short name	T270
Test name
Test status
Simulation time	381693516 ps
CPU time	2.63 seconds
Started	Mar 26 12:38:51 PM PDT 24
Finished	Mar 26 12:38:54 PM PDT 24
Peak memory	200620 kb
Host	smart-1348244a-22a4-4d51-9ebf-539dee6659d8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767188976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t imeout.3767188976
Directory	/workspace/36.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/36.clkmgr_idle_intersig_mubi.2628462176
Short name	T762
Test name
Test status
Simulation time	30901127 ps
CPU time	1.07 seconds
Started	Mar 26 12:38:53 PM PDT 24
Finished	Mar 26 12:38:55 PM PDT 24
Peak memory	200512 kb
Host	smart-2eafc22c-c6f3-4387-8d43-9a290ecb8571
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628462176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.2628462176
Directory	/workspace/36.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.3357283308
Short name	T216
Test name
Test status
Simulation time	87880482 ps
CPU time	1.1 seconds
Started	Mar 26 12:38:51 PM PDT 24
Finished	Mar 26 12:38:53 PM PDT 24
Peak memory	200564 kb
Host	smart-d06a3d61-1688-46b3-83cc-6d31ec5709b5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357283308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 36.clkmgr_lc_clk_byp_req_intersig_mubi.3357283308
Directory	/workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.248061581
Short name	T720
Test name
Test status
Simulation time	76682871 ps
CPU time	0.97 seconds
Started	Mar 26 12:38:44 PM PDT 24
Finished	Mar 26 12:38:45 PM PDT 24
Peak memory	200540 kb
Host	smart-b6219e50-a78c-4201-b13c-80fd5ca6b72a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248061581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.clkmgr_lc_ctrl_intersig_mubi.248061581
Directory	/workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_peri.4282011982
Short name	T249
Test name
Test status
Simulation time	24974578 ps
CPU time	0.81 seconds
Started	Mar 26 12:38:50 PM PDT 24
Finished	Mar 26 12:38:51 PM PDT 24
Peak memory	199644 kb
Host	smart-a13c84c1-b6bc-407a-b986-ac92c1096219
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282011982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.4282011982
Directory	/workspace/36.clkmgr_peri/latest

Test location	/workspace/coverage/default/36.clkmgr_regwen.2162322471
Short name	T586
Test name
Test status
Simulation time	94150642 ps
CPU time	1.11 seconds
Started	Mar 26 12:38:57 PM PDT 24
Finished	Mar 26 12:38:58 PM PDT 24
Peak memory	200568 kb
Host	smart-4387c8ee-9193-4003-9a03-d29efe9233c3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162322471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.2162322471
Directory	/workspace/36.clkmgr_regwen/latest

Test location	/workspace/coverage/default/36.clkmgr_smoke.3332374397
Short name	T279
Test name
Test status
Simulation time	176236122 ps
CPU time	1.21 seconds
Started	Mar 26 12:38:53 PM PDT 24
Finished	Mar 26 12:38:54 PM PDT 24
Peak memory	200584 kb
Host	smart-378dcdef-ea8d-4ba4-8f06-f9a4c7703f3e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332374397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.3332374397
Directory	/workspace/36.clkmgr_smoke/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all.2666314052
Short name	T343
Test name
Test status
Simulation time	7886656959 ps
CPU time	37.11 seconds
Started	Mar 26 12:38:57 PM PDT 24
Finished	Mar 26 12:39:34 PM PDT 24
Peak memory	200832 kb
Host	smart-fd0be4c0-f3f0-48d7-85e1-f52006103547
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666314052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.2666314052
Directory	/workspace/36.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.154244627
Short name	T555
Test name
Test status
Simulation time	14486385031 ps
CPU time	249.7 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:43:08 PM PDT 24
Peak memory	209156 kb
Host	smart-d0b062ba-ac9a-40b1-82db-8a78afd59984
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=154244627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.154244627
Directory	/workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.clkmgr_trans.3627975157
Short name	T802
Test name
Test status
Simulation time	98109093 ps
CPU time	1.16 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:38:59 PM PDT 24
Peak memory	200568 kb
Host	smart-9f14cc0d-a497-4996-898e-f5c80e3decdb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627975157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.3627975157
Directory	/workspace/36.clkmgr_trans/latest

Test location	/workspace/coverage/default/37.clkmgr_alert_test.3953619793
Short name	T551
Test name
Test status
Simulation time	13620898 ps
CPU time	0.75 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:38:59 PM PDT 24
Peak memory	200636 kb
Host	smart-84719920-1c43-4730-9ce3-df330230fdab
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953619793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk mgr_alert_test.3953619793
Directory	/workspace/37.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.2506690268
Short name	T600
Test name
Test status
Simulation time	110563210 ps
CPU time	0.99 seconds
Started	Mar 26 12:38:59 PM PDT 24
Finished	Mar 26 12:39:00 PM PDT 24
Peak memory	200556 kb
Host	smart-38ce5368-5140-4558-ba46-e16774080628
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506690268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.2506690268
Directory	/workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_status.617459292
Short name	T164
Test name
Test status
Simulation time	51497450 ps
CPU time	0.77 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:38:59 PM PDT 24
Peak memory	200484 kb
Host	smart-7bdff294-9dfa-4820-9330-cd6be5df0eeb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617459292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.617459292
Directory	/workspace/37.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/37.clkmgr_div_intersig_mubi.1310602709
Short name	T471
Test name
Test status
Simulation time	50945606 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:57 PM PDT 24
Finished	Mar 26 12:38:59 PM PDT 24
Peak memory	200564 kb
Host	smart-cf191e2f-8bfa-4e19-a690-de93ac99f804
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310602709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.1310602709
Directory	/workspace/37.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_extclk.2681789157
Short name	T420
Test name
Test status
Simulation time	71117229 ps
CPU time	0.98 seconds
Started	Mar 26 12:39:00 PM PDT 24
Finished	Mar 26 12:39:01 PM PDT 24
Peak memory	200560 kb
Host	smart-b80c8ed7-924a-4c7a-8da7-dcd2687e2c5d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681789157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.2681789157
Directory	/workspace/37.clkmgr_extclk/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency.2408447444
Short name	T578
Test name
Test status
Simulation time	2422227307 ps
CPU time	10.59 seconds
Started	Mar 26 12:39:03 PM PDT 24
Finished	Mar 26 12:39:14 PM PDT 24
Peak memory	200772 kb
Host	smart-12813b81-289f-4368-8a54-214c444cd7c6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408447444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.2408447444
Directory	/workspace/37.clkmgr_frequency/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency_timeout.1863308051
Short name	T763
Test name
Test status
Simulation time	1819723252 ps
CPU time	12.83 seconds
Started	Mar 26 12:38:57 PM PDT 24
Finished	Mar 26 12:39:10 PM PDT 24
Peak memory	200640 kb
Host	smart-69f001df-64ee-46ec-af01-2c70ec0e1bd5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863308051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t imeout.1863308051
Directory	/workspace/37.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/37.clkmgr_idle_intersig_mubi.34195471
Short name	T376
Test name
Test status
Simulation time	18155314 ps
CPU time	0.84 seconds
Started	Mar 26 12:38:59 PM PDT 24
Finished	Mar 26 12:39:00 PM PDT 24
Peak memory	200656 kb
Host	smart-0b1b0b05-dbd1-4bd4-8b0a-2164bc52c638
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34195471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .clkmgr_idle_intersig_mubi.34195471
Directory	/workspace/37.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1323494373
Short name	T694
Test name
Test status
Simulation time	18996931 ps
CPU time	0.8 seconds
Started	Mar 26 12:39:00 PM PDT 24
Finished	Mar 26 12:39:01 PM PDT 24
Peak memory	200640 kb
Host	smart-1b8f8ba5-f8cc-4299-8f99-cf5ee8ec38f9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323494373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.clkmgr_lc_clk_byp_req_intersig_mubi.1323494373
Directory	/workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.3449678161
Short name	T180
Test name
Test status
Simulation time	32837053 ps
CPU time	0.74 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:38:59 PM PDT 24
Peak memory	200628 kb
Host	smart-9b0d5a0d-1f4c-40c1-9b4b-e1042e4186f9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449678161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.clkmgr_lc_ctrl_intersig_mubi.3449678161
Directory	/workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_peri.1605658894
Short name	T288
Test name
Test status
Simulation time	15375274 ps
CPU time	0.7 seconds
Started	Mar 26 12:38:55 PM PDT 24
Finished	Mar 26 12:38:56 PM PDT 24
Peak memory	200540 kb
Host	smart-f0983d13-fe84-4cf8-abb1-f717ea9fb62e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605658894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.1605658894
Directory	/workspace/37.clkmgr_peri/latest

Test location	/workspace/coverage/default/37.clkmgr_regwen.853478371
Short name	T647
Test name
Test status
Simulation time	148313848 ps
CPU time	1.12 seconds
Started	Mar 26 12:38:59 PM PDT 24
Finished	Mar 26 12:39:00 PM PDT 24
Peak memory	200548 kb
Host	smart-b0a77b49-9a82-4afa-9e42-02320caf4a46
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853478371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.853478371
Directory	/workspace/37.clkmgr_regwen/latest

Test location	/workspace/coverage/default/37.clkmgr_smoke.1324761089
Short name	T758
Test name
Test status
Simulation time	71233971 ps
CPU time	0.95 seconds
Started	Mar 26 12:38:59 PM PDT 24
Finished	Mar 26 12:39:01 PM PDT 24
Peak memory	200600 kb
Host	smart-45874bcf-e68a-46ba-aca2-3545103d9c82
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324761089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.1324761089
Directory	/workspace/37.clkmgr_smoke/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all.3936824156
Short name	T40
Test name
Test status
Simulation time	8419361539 ps
CPU time	59.81 seconds
Started	Mar 26 12:38:59 PM PDT 24
Finished	Mar 26 12:39:59 PM PDT 24
Peak memory	200840 kb
Host	smart-c724f17e-9926-4b8f-ad91-e9ce1dcc9d60
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936824156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.3936824156
Directory	/workspace/37.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.3518324653
Short name	T158
Test name
Test status
Simulation time	26309969280 ps
CPU time	394.26 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:45:33 PM PDT 24
Peak memory	209244 kb
Host	smart-1b3bcbdc-848d-4d1f-9903-0efdab47a607
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3518324653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.3518324653
Directory	/workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.clkmgr_trans.3516633534
Short name	T237
Test name
Test status
Simulation time	73351659 ps
CPU time	1.21 seconds
Started	Mar 26 12:39:00 PM PDT 24
Finished	Mar 26 12:39:02 PM PDT 24
Peak memory	200572 kb
Host	smart-c0bffd3e-777f-443a-b48a-f4b82652a330
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516633534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.3516633534
Directory	/workspace/37.clkmgr_trans/latest

Test location	/workspace/coverage/default/38.clkmgr_alert_test.2475747374
Short name	T38
Test name
Test status
Simulation time	16027616 ps
CPU time	0.74 seconds
Started	Mar 26 12:38:55 PM PDT 24
Finished	Mar 26 12:38:56 PM PDT 24
Peak memory	200636 kb
Host	smart-2b7c9939-44cd-4348-b2f6-0e92e1460149
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475747374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk mgr_alert_test.2475747374
Directory	/workspace/38.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.3483982612
Short name	T808
Test name
Test status
Simulation time	172129547 ps
CPU time	1.25 seconds
Started	Mar 26 12:38:59 PM PDT 24
Finished	Mar 26 12:39:00 PM PDT 24
Peak memory	200596 kb
Host	smart-962ae0d5-5fcb-4061-84f2-a61345f28a24
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483982612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.3483982612
Directory	/workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_status.1464529969
Short name	T165
Test name
Test status
Simulation time	16672503 ps
CPU time	0.73 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:38:59 PM PDT 24
Peak memory	199512 kb
Host	smart-20478113-07c5-441f-8989-86d5e7099a9f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464529969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.1464529969
Directory	/workspace/38.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/38.clkmgr_div_intersig_mubi.4071832859
Short name	T823
Test name
Test status
Simulation time	24890972 ps
CPU time	0.95 seconds
Started	Mar 26 12:39:02 PM PDT 24
Finished	Mar 26 12:39:03 PM PDT 24
Peak memory	200572 kb
Host	smart-b945e7d0-43bf-46af-a38d-998662035bd2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071832859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.4071832859
Directory	/workspace/38.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_extclk.1505677974
Short name	T713
Test name
Test status
Simulation time	41164741 ps
CPU time	0.78 seconds
Started	Mar 26 12:38:56 PM PDT 24
Finished	Mar 26 12:38:57 PM PDT 24
Peak memory	200544 kb
Host	smart-07c44ec4-3f6f-496a-81dd-38b3408ed722
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505677974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.1505677974
Directory	/workspace/38.clkmgr_extclk/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency.1640268032
Short name	T547
Test name
Test status
Simulation time	807982739 ps
CPU time	5.86 seconds
Started	Mar 26 12:39:02 PM PDT 24
Finished	Mar 26 12:39:09 PM PDT 24
Peak memory	200472 kb
Host	smart-b232488a-b22e-4bf0-9707-d657aee3a902
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640268032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.1640268032
Directory	/workspace/38.clkmgr_frequency/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency_timeout.237043230
Short name	T190
Test name
Test status
Simulation time	1459220494 ps
CPU time	10.34 seconds
Started	Mar 26 12:38:59 PM PDT 24
Finished	Mar 26 12:39:09 PM PDT 24
Peak memory	200648 kb
Host	smart-e949dc85-e25c-4eb8-b12b-1040fc6aed03
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237043230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_ti meout.237043230
Directory	/workspace/38.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/38.clkmgr_idle_intersig_mubi.1250940394
Short name	T815
Test name
Test status
Simulation time	22213976 ps
CPU time	0.85 seconds
Started	Mar 26 12:38:59 PM PDT 24
Finished	Mar 26 12:39:00 PM PDT 24
Peak memory	200584 kb
Host	smart-37cf9dfc-946c-4908-837f-7c9a670c972a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250940394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.1250940394
Directory	/workspace/38.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.1416017662
Short name	T840
Test name
Test status
Simulation time	14732871 ps
CPU time	0.84 seconds
Started	Mar 26 12:39:02 PM PDT 24
Finished	Mar 26 12:39:03 PM PDT 24
Peak memory	200580 kb
Host	smart-402a3fef-234a-4c97-8b38-aa928e15dcff
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416017662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 38.clkmgr_lc_clk_byp_req_intersig_mubi.1416017662
Directory	/workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.1630872691
Short name	T617
Test name
Test status
Simulation time	70181659 ps
CPU time	1.01 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:39:00 PM PDT 24
Peak memory	200544 kb
Host	smart-7637c6de-b738-4bf5-9e56-6d4c69714f63
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630872691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 38.clkmgr_lc_ctrl_intersig_mubi.1630872691
Directory	/workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_peri.701590117
Short name	T155
Test name
Test status
Simulation time	22267867 ps
CPU time	0.78 seconds
Started	Mar 26 12:38:56 PM PDT 24
Finished	Mar 26 12:38:56 PM PDT 24
Peak memory	200608 kb
Host	smart-96c6f4f4-e6eb-4b3e-b49f-6ea29fb163ec
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701590117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.701590117
Directory	/workspace/38.clkmgr_peri/latest

Test location	/workspace/coverage/default/38.clkmgr_regwen.2221508093
Short name	T218
Test name
Test status
Simulation time	717853946 ps
CPU time	3.96 seconds
Started	Mar 26 12:38:57 PM PDT 24
Finished	Mar 26 12:39:01 PM PDT 24
Peak memory	200728 kb
Host	smart-8027d01b-490a-48d1-beb3-c403ed6b98f4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221508093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.2221508093
Directory	/workspace/38.clkmgr_regwen/latest

Test location	/workspace/coverage/default/38.clkmgr_smoke.959111044
Short name	T227
Test name
Test status
Simulation time	27665203 ps
CPU time	0.91 seconds
Started	Mar 26 12:39:00 PM PDT 24
Finished	Mar 26 12:39:01 PM PDT 24
Peak memory	200592 kb
Host	smart-d608b875-c10f-4207-a5b5-dc661c44128a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959111044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.959111044
Directory	/workspace/38.clkmgr_smoke/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all.500801345
Short name	T52
Test name
Test status
Simulation time	13284109160 ps
CPU time	65.2 seconds
Started	Mar 26 12:38:57 PM PDT 24
Finished	Mar 26 12:40:03 PM PDT 24
Peak memory	200852 kb
Host	smart-e29688fe-611b-43e3-96c6-b28180a217c2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500801345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.500801345
Directory	/workspace/38.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.1129646829
Short name	T92
Test name
Test status
Simulation time	32891044126 ps
CPU time	599.17 seconds
Started	Mar 26 12:38:56 PM PDT 24
Finished	Mar 26 12:48:56 PM PDT 24
Peak memory	209152 kb
Host	smart-a3aeaa60-502c-430d-b338-84460cd78785
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1129646829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.1129646829
Directory	/workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.clkmgr_trans.3304595508
Short name	T444
Test name
Test status
Simulation time	25691624 ps
CPU time	0.79 seconds
Started	Mar 26 12:38:59 PM PDT 24
Finished	Mar 26 12:39:00 PM PDT 24
Peak memory	200644 kb
Host	smart-f2f96f37-51be-4143-9a47-0eeef382ce63
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304595508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.3304595508
Directory	/workspace/38.clkmgr_trans/latest

Test location	/workspace/coverage/default/39.clkmgr_alert_test.2212889905
Short name	T478
Test name
Test status
Simulation time	44887293 ps
CPU time	0.81 seconds
Started	Mar 26 12:38:56 PM PDT 24
Finished	Mar 26 12:38:57 PM PDT 24
Peak memory	200544 kb
Host	smart-7622bf74-1cbd-4e5f-90dc-00c36cc3df55
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212889905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk mgr_alert_test.2212889905
Directory	/workspace/39.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.347938550
Short name	T499
Test name
Test status
Simulation time	19999932 ps
CPU time	0.85 seconds
Started	Mar 26 12:39:00 PM PDT 24
Finished	Mar 26 12:39:01 PM PDT 24
Peak memory	200596 kb
Host	smart-5a58fa76-4fcc-47ad-a2c6-0c5ac1fbc963
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347938550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.347938550
Directory	/workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_status.1235207570
Short name	T843
Test name
Test status
Simulation time	18084681 ps
CPU time	0.69 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:38:59 PM PDT 24
Peak memory	199584 kb
Host	smart-ecbf9bc8-ad72-4d28-89bb-33145e95c466
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235207570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.1235207570
Directory	/workspace/39.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/39.clkmgr_div_intersig_mubi.559023506
Short name	T309
Test name
Test status
Simulation time	19588934 ps
CPU time	0.87 seconds
Started	Mar 26 12:39:03 PM PDT 24
Finished	Mar 26 12:39:04 PM PDT 24
Peak memory	200532 kb
Host	smart-083bae0f-7123-4fef-a514-4b88c0f4eff7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559023506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.clkmgr_div_intersig_mubi.559023506
Directory	/workspace/39.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_extclk.158409788
Short name	T744
Test name
Test status
Simulation time	70022340 ps
CPU time	0.92 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:38:59 PM PDT 24
Peak memory	200644 kb
Host	smart-3853f603-06c5-45e0-b7be-9cf69a78fe0c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158409788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.158409788
Directory	/workspace/39.clkmgr_extclk/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency.2946143532
Short name	T567
Test name
Test status
Simulation time	1226592724 ps
CPU time	5.71 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:39:04 PM PDT 24
Peak memory	200512 kb
Host	smart-1e63164b-cb7c-4368-b7b0-e9b98214c9aa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946143532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.2946143532
Directory	/workspace/39.clkmgr_frequency/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency_timeout.2520695919
Short name	T529
Test name
Test status
Simulation time	1223742869 ps
CPU time	6.65 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:39:05 PM PDT 24
Peak memory	200652 kb
Host	smart-b7a0de94-b398-435d-81a2-dec361703405
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520695919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t imeout.2520695919
Directory	/workspace/39.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/39.clkmgr_idle_intersig_mubi.1686702840
Short name	T29
Test name
Test status
Simulation time	102902176 ps
CPU time	1.22 seconds
Started	Mar 26 12:38:56 PM PDT 24
Finished	Mar 26 12:38:58 PM PDT 24
Peak memory	200568 kb
Host	smart-ab03ec04-1338-463e-87aa-422219820ed7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686702840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.1686702840
Directory	/workspace/39.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.570324237
Short name	T834
Test name
Test status
Simulation time	27832695 ps
CPU time	0.79 seconds
Started	Mar 26 12:39:00 PM PDT 24
Finished	Mar 26 12:39:01 PM PDT 24
Peak memory	200608 kb
Host	smart-a3793d96-5b31-400a-8acd-7fa650e6a70b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570324237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.clkmgr_lc_clk_byp_req_intersig_mubi.570324237
Directory	/workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.1764485396
Short name	T329
Test name
Test status
Simulation time	65501181 ps
CPU time	0.91 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:38:59 PM PDT 24
Peak memory	200552 kb
Host	smart-6a73d137-60b1-445f-bc13-68b08f2e3126
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764485396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.clkmgr_lc_ctrl_intersig_mubi.1764485396
Directory	/workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_peri.2163759732
Short name	T620
Test name
Test status
Simulation time	20244951 ps
CPU time	0.7 seconds
Started	Mar 26 12:38:59 PM PDT 24
Finished	Mar 26 12:39:00 PM PDT 24
Peak memory	200532 kb
Host	smart-cd85e94f-4c35-495e-83b0-d36ae1777ed8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163759732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.2163759732
Directory	/workspace/39.clkmgr_peri/latest

Test location	/workspace/coverage/default/39.clkmgr_regwen.1962098434
Short name	T608
Test name
Test status
Simulation time	206035046 ps
CPU time	1.83 seconds
Started	Mar 26 12:39:00 PM PDT 24
Finished	Mar 26 12:39:02 PM PDT 24
Peak memory	200504 kb
Host	smart-bca347d8-495c-4f91-931a-8fab95bab418
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962098434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1962098434
Directory	/workspace/39.clkmgr_regwen/latest

Test location	/workspace/coverage/default/39.clkmgr_smoke.1716083294
Short name	T818
Test name
Test status
Simulation time	17688076 ps
CPU time	0.82 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:38:59 PM PDT 24
Peak memory	200492 kb
Host	smart-9dbcacd2-5e59-472d-9c59-f4c47322d942
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716083294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.1716083294
Directory	/workspace/39.clkmgr_smoke/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all.949029557
Short name	T590
Test name
Test status
Simulation time	654431629 ps
CPU time	5.31 seconds
Started	Mar 26 12:38:59 PM PDT 24
Finished	Mar 26 12:39:04 PM PDT 24
Peak memory	200588 kb
Host	smart-7eccc5ce-bef3-439a-9a30-4dcd29c3d1fa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949029557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.949029557
Directory	/workspace/39.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.930100932
Short name	T463
Test name
Test status
Simulation time	74671950444 ps
CPU time	835.64 seconds
Started	Mar 26 12:38:57 PM PDT 24
Finished	Mar 26 12:52:53 PM PDT 24
Peak memory	209188 kb
Host	smart-8420b00f-d30f-49aa-848c-5ca4d37cd618
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=930100932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.930100932
Directory	/workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.clkmgr_trans.4236402870
Short name	T537
Test name
Test status
Simulation time	15940350 ps
CPU time	0.77 seconds
Started	Mar 26 12:39:02 PM PDT 24
Finished	Mar 26 12:39:04 PM PDT 24
Peak memory	200472 kb
Host	smart-d6e4cebd-f5ea-4422-9c83-8912403a867a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236402870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.4236402870
Directory	/workspace/39.clkmgr_trans/latest

Test location	/workspace/coverage/default/4.clkmgr_alert_test.3653769710
Short name	T473
Test name
Test status
Simulation time	27062190 ps
CPU time	0.82 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	200616 kb
Host	smart-80fd3d87-1a90-4693-b3bf-c1bc67bf6a6e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653769710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm gr_alert_test.3653769710
Directory	/workspace/4.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.4249771502
Short name	T77
Test name
Test status
Simulation time	94294831 ps
CPU time	1.08 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:34 PM PDT 24
Peak memory	200596 kb
Host	smart-9dbca1cb-f27b-41c7-9b52-3106bc707444
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249771502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.4249771502
Directory	/workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_status.3629482380
Short name	T163
Test name
Test status
Simulation time	31370273 ps
CPU time	0.69 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	199092 kb
Host	smart-1db5db10-046e-4177-aecd-bdd6e67aae1b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629482380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.3629482380
Directory	/workspace/4.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/4.clkmgr_div_intersig_mubi.349096351
Short name	T417
Test name
Test status
Simulation time	70462721 ps
CPU time	1.02 seconds
Started	Mar 26 12:37:30 PM PDT 24
Finished	Mar 26 12:37:31 PM PDT 24
Peak memory	200624 kb
Host	smart-5cbd4c3f-eefd-47fe-88c7-6feecdff237c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349096351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .clkmgr_div_intersig_mubi.349096351
Directory	/workspace/4.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_extclk.2111838004
Short name	T200
Test name
Test status
Simulation time	31865122 ps
CPU time	0.79 seconds
Started	Mar 26 12:37:29 PM PDT 24
Finished	Mar 26 12:37:30 PM PDT 24
Peak memory	200628 kb
Host	smart-0ef2ffff-1599-4b55-a097-eccc15b1deb7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111838004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.2111838004
Directory	/workspace/4.clkmgr_extclk/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency.3934438679
Short name	T114
Test name
Test status
Simulation time	1374626858 ps
CPU time	6 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:38 PM PDT 24
Peak memory	200524 kb
Host	smart-0cdccd13-1215-45df-ace0-8bbb17273c28
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934438679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.3934438679
Directory	/workspace/4.clkmgr_frequency/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency_timeout.3382115388
Short name	T280
Test name
Test status
Simulation time	2065712449 ps
CPU time	10.42 seconds
Started	Mar 26 12:37:31 PM PDT 24
Finished	Mar 26 12:37:41 PM PDT 24
Peak memory	200712 kb
Host	smart-6f40f490-93e4-48d2-92b5-3deaf71448de
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382115388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti meout.3382115388
Directory	/workspace/4.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/4.clkmgr_idle_intersig_mubi.3658512584
Short name	T325
Test name
Test status
Simulation time	24237598 ps
CPU time	0.83 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200556 kb
Host	smart-93e59742-ab58-4941-abd5-baf876221079
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658512584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.3658512584
Directory	/workspace/4.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.1752431293
Short name	T7
Test name
Test status
Simulation time	103557994 ps
CPU time	0.95 seconds
Started	Mar 26 12:37:28 PM PDT 24
Finished	Mar 26 12:37:29 PM PDT 24
Peak memory	200576 kb
Host	smart-b2635a0c-2802-49c5-898b-cdff4494f3ef
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752431293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.clkmgr_lc_clk_byp_req_intersig_mubi.1752431293
Directory	/workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.3899140316
Short name	T826
Test name
Test status
Simulation time	16813166 ps
CPU time	0.73 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	200272 kb
Host	smart-e4bb8a5b-d870-458a-86a7-1ca7d14ed199
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899140316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.clkmgr_lc_ctrl_intersig_mubi.3899140316
Directory	/workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_peri.914317246
Short name	T528
Test name
Test status
Simulation time	20705776 ps
CPU time	0.76 seconds
Started	Mar 26 12:37:31 PM PDT 24
Finished	Mar 26 12:37:32 PM PDT 24
Peak memory	200572 kb
Host	smart-d361fd05-7c1d-4e7b-983a-0f4a6f170a44
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914317246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.914317246
Directory	/workspace/4.clkmgr_peri/latest

Test location	/workspace/coverage/default/4.clkmgr_regwen.2561064655
Short name	T327
Test name
Test status
Simulation time	831974441 ps
CPU time	3.85 seconds
Started	Mar 26 12:37:34 PM PDT 24
Finished	Mar 26 12:37:38 PM PDT 24
Peak memory	200668 kb
Host	smart-e2b42386-f9c0-426a-9cf0-95a44766625f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561064655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.2561064655
Directory	/workspace/4.clkmgr_regwen/latest

Test location	/workspace/coverage/default/4.clkmgr_sec_cm.52807684
Short name	T49
Test name
Test status
Simulation time	391465692 ps
CPU time	3.19 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	217192 kb
Host	smart-94e62074-ffef-4c6e-b7bc-285f31a14e33
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52807684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_ sec_cm.52807684
Directory	/workspace/4.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/4.clkmgr_smoke.1397638946
Short name	T633
Test name
Test status
Simulation time	34709723 ps
CPU time	0.86 seconds
Started	Mar 26 12:37:30 PM PDT 24
Finished	Mar 26 12:37:31 PM PDT 24
Peak memory	200656 kb
Host	smart-69cc00a2-c42e-48f9-8aa9-16edd4800682
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397638946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.1397638946
Directory	/workspace/4.clkmgr_smoke/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all.3840037825
Short name	T595
Test name
Test status
Simulation time	1410880985 ps
CPU time	6.83 seconds
Started	Mar 26 12:37:39 PM PDT 24
Finished	Mar 26 12:37:46 PM PDT 24
Peak memory	200732 kb
Host	smart-8b125ed0-e122-4d67-beb6-47730806bbcf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840037825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.3840037825
Directory	/workspace/4.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.930586560
Short name	T691
Test name
Test status
Simulation time	64254587887 ps
CPU time	582.79 seconds
Started	Mar 26 12:37:34 PM PDT 24
Finished	Mar 26 12:47:18 PM PDT 24
Peak memory	211248 kb
Host	smart-84a99287-2be7-48df-a4a2-08b08a889684
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=930586560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.930586560
Directory	/workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.clkmgr_trans.3327268487
Short name	T182
Test name
Test status
Simulation time	26270214 ps
CPU time	0.88 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200576 kb
Host	smart-ad65ef38-201c-40f2-a091-d87028df065b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327268487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.3327268487
Directory	/workspace/4.clkmgr_trans/latest

Test location	/workspace/coverage/default/40.clkmgr_alert_test.125265369
Short name	T591
Test name
Test status
Simulation time	16368472 ps
CPU time	0.8 seconds
Started	Mar 26 12:39:01 PM PDT 24
Finished	Mar 26 12:39:02 PM PDT 24
Peak memory	200692 kb
Host	smart-d77d6a18-9eec-43b5-a6a2-eff6aba8e839
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125265369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkm gr_alert_test.125265369
Directory	/workspace/40.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.2825302893
Short name	T618
Test name
Test status
Simulation time	75431107 ps
CPU time	0.96 seconds
Started	Mar 26 12:39:02 PM PDT 24
Finished	Mar 26 12:39:03 PM PDT 24
Peak memory	200620 kb
Host	smart-57986f6d-f071-4dc1-9dfa-6979cdf5b981
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825302893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.2825302893
Directory	/workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_status.269458580
Short name	T527
Test name
Test status
Simulation time	14181025 ps
CPU time	0.72 seconds
Started	Mar 26 12:39:00 PM PDT 24
Finished	Mar 26 12:39:00 PM PDT 24
Peak memory	199536 kb
Host	smart-7d0315b9-348b-4a04-96df-37fcd05d6b9e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269458580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.269458580
Directory	/workspace/40.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/40.clkmgr_div_intersig_mubi.3571502862
Short name	T488
Test name
Test status
Simulation time	40929227 ps
CPU time	0.86 seconds
Started	Mar 26 12:39:04 PM PDT 24
Finished	Mar 26 12:39:05 PM PDT 24
Peak memory	200560 kb
Host	smart-8af669de-6a69-425b-b2e4-d3bd09ad76ff
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571502862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_div_intersig_mubi.3571502862
Directory	/workspace/40.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_extclk.3326527459
Short name	T203
Test name
Test status
Simulation time	26815235 ps
CPU time	0.81 seconds
Started	Mar 26 12:39:00 PM PDT 24
Finished	Mar 26 12:39:02 PM PDT 24
Peak memory	200556 kb
Host	smart-8fa67b17-3b6e-4ed9-97db-b2c1ae60b60b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326527459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.3326527459
Directory	/workspace/40.clkmgr_extclk/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency.4063016743
Short name	T435
Test name
Test status
Simulation time	502147902 ps
CPU time	2.56 seconds
Started	Mar 26 12:39:01 PM PDT 24
Finished	Mar 26 12:39:04 PM PDT 24
Peak memory	200512 kb
Host	smart-e074a025-3387-4e78-b6fa-10a76dee4a8e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063016743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.4063016743
Directory	/workspace/40.clkmgr_frequency/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency_timeout.4011589809
Short name	T207
Test name
Test status
Simulation time	1823312309 ps
CPU time	9.78 seconds
Started	Mar 26 12:39:01 PM PDT 24
Finished	Mar 26 12:39:12 PM PDT 24
Peak memory	200648 kb
Host	smart-83d6a4df-0993-4268-b19e-376537075c7e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011589809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t imeout.4011589809
Directory	/workspace/40.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/40.clkmgr_idle_intersig_mubi.617659006
Short name	T286
Test name
Test status
Simulation time	53384356 ps
CPU time	0.82 seconds
Started	Mar 26 12:38:55 PM PDT 24
Finished	Mar 26 12:38:56 PM PDT 24
Peak memory	200528 kb
Host	smart-30370a7d-0011-4ebf-a587-8840c68f50f3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617659006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.clkmgr_idle_intersig_mubi.617659006
Directory	/workspace/40.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.3227551591
Short name	T710
Test name
Test status
Simulation time	52199167 ps
CPU time	0.98 seconds
Started	Mar 26 12:39:02 PM PDT 24
Finished	Mar 26 12:39:03 PM PDT 24
Peak memory	200548 kb
Host	smart-b0515810-aff9-4126-a502-71b7df8cb10d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227551591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_clk_byp_req_intersig_mubi.3227551591
Directory	/workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.4140085354
Short name	T579
Test name
Test status
Simulation time	111505396 ps
CPU time	1.08 seconds
Started	Mar 26 12:39:03 PM PDT 24
Finished	Mar 26 12:39:04 PM PDT 24
Peak memory	200572 kb
Host	smart-33d7b89f-e37e-441a-ad7b-290527c6338d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140085354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_ctrl_intersig_mubi.4140085354
Directory	/workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_peri.3598898939
Short name	T714
Test name
Test status
Simulation time	46712838 ps
CPU time	0.91 seconds
Started	Mar 26 12:39:02 PM PDT 24
Finished	Mar 26 12:39:03 PM PDT 24
Peak memory	200620 kb
Host	smart-73b1fe67-e9f8-4d5d-9d88-ebcbfa4418a5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598898939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.3598898939
Directory	/workspace/40.clkmgr_peri/latest

Test location	/workspace/coverage/default/40.clkmgr_regwen.2619804819
Short name	T326
Test name
Test status
Simulation time	953554659 ps
CPU time	4.27 seconds
Started	Mar 26 12:39:01 PM PDT 24
Finished	Mar 26 12:39:06 PM PDT 24
Peak memory	200536 kb
Host	smart-57124228-6953-4994-b017-1c1755ad2285
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619804819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.2619804819
Directory	/workspace/40.clkmgr_regwen/latest

Test location	/workspace/coverage/default/40.clkmgr_smoke.1072498840
Short name	T532
Test name
Test status
Simulation time	26660236 ps
CPU time	0.79 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:38:59 PM PDT 24
Peak memory	200648 kb
Host	smart-ef4d0ef3-b6ac-4313-bc3c-82803eaa701c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072498840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.1072498840
Directory	/workspace/40.clkmgr_smoke/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all.1590031519
Short name	T240
Test name
Test status
Simulation time	8289629800 ps
CPU time	38.86 seconds
Started	Mar 26 12:39:03 PM PDT 24
Finished	Mar 26 12:39:42 PM PDT 24
Peak memory	200816 kb
Host	smart-9236ba33-3204-49da-84f7-6a124b56105e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590031519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.1590031519
Directory	/workspace/40.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.2386676306
Short name	T339
Test name
Test status
Simulation time	98307692135 ps
CPU time	923.01 seconds
Started	Mar 26 12:38:58 PM PDT 24
Finished	Mar 26 12:54:21 PM PDT 24
Peak memory	209184 kb
Host	smart-693790de-24e4-4d9c-ad25-1fa80ed89329
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2386676306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.2386676306
Directory	/workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.clkmgr_trans.3858821508
Short name	T690
Test name
Test status
Simulation time	22916778 ps
CPU time	0.8 seconds
Started	Mar 26 12:39:01 PM PDT 24
Finished	Mar 26 12:39:02 PM PDT 24
Peak memory	200572 kb
Host	smart-092b1548-4cae-44e3-9650-37d111f6726f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858821508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.3858821508
Directory	/workspace/40.clkmgr_trans/latest

Test location	/workspace/coverage/default/41.clkmgr_alert_test.3404644736
Short name	T460
Test name
Test status
Simulation time	36034405 ps
CPU time	0.82 seconds
Started	Mar 26 12:39:15 PM PDT 24
Finished	Mar 26 12:39:16 PM PDT 24
Peak memory	200536 kb
Host	smart-c5c45904-624f-4fbd-a130-2e3dadb2f237
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404644736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk mgr_alert_test.3404644736
Directory	/workspace/41.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.2796950674
Short name	T526
Test name
Test status
Simulation time	24107178 ps
CPU time	0.88 seconds
Started	Mar 26 12:39:26 PM PDT 24
Finished	Mar 26 12:39:27 PM PDT 24
Peak memory	200472 kb
Host	smart-fc00d687-2b16-4aa8-b21e-b8f4a2544c56
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796950674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.2796950674
Directory	/workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_status.2149000212
Short name	T852
Test name
Test status
Simulation time	22890728 ps
CPU time	0.75 seconds
Started	Mar 26 12:39:25 PM PDT 24
Finished	Mar 26 12:39:26 PM PDT 24
Peak memory	199380 kb
Host	smart-29cc2de6-e8e9-437b-9d4f-7eace85cf72a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149000212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.2149000212
Directory	/workspace/41.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/41.clkmgr_div_intersig_mubi.1499352771
Short name	T614
Test name
Test status
Simulation time	57589197 ps
CPU time	0.86 seconds
Started	Mar 26 12:39:12 PM PDT 24
Finished	Mar 26 12:39:13 PM PDT 24
Peak memory	200572 kb
Host	smart-a1bda232-5faa-4e7e-b1bb-10766b1763b0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499352771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.1499352771
Directory	/workspace/41.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_extclk.4214517849
Short name	T476
Test name
Test status
Simulation time	47258242 ps
CPU time	0.93 seconds
Started	Mar 26 12:39:15 PM PDT 24
Finished	Mar 26 12:39:16 PM PDT 24
Peak memory	200584 kb
Host	smart-28850d75-be76-449b-8332-ae7b69f2dd3b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214517849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.4214517849
Directory	/workspace/41.clkmgr_extclk/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency.2029461771
Short name	T13
Test name
Test status
Simulation time	2025263249 ps
CPU time	8.8 seconds
Started	Mar 26 12:39:15 PM PDT 24
Finished	Mar 26 12:39:24 PM PDT 24
Peak memory	200624 kb
Host	smart-826097cc-e7c0-4ff3-9875-8ac688a3fe4f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029461771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.2029461771
Directory	/workspace/41.clkmgr_frequency/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency_timeout.747406500
Short name	T656
Test name
Test status
Simulation time	158492723 ps
CPU time	1.3 seconds
Started	Mar 26 12:39:29 PM PDT 24
Finished	Mar 26 12:39:31 PM PDT 24
Peak memory	200568 kb
Host	smart-c9c0144a-e9d3-482b-9fe1-ff8eb599d6f7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747406500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_ti meout.747406500
Directory	/workspace/41.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/41.clkmgr_idle_intersig_mubi.2245977038
Short name	T365
Test name
Test status
Simulation time	91836858 ps
CPU time	1.15 seconds
Started	Mar 26 12:39:13 PM PDT 24
Finished	Mar 26 12:39:15 PM PDT 24
Peak memory	200580 kb
Host	smart-b765cc0e-4555-488e-8296-d9d231411178
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245977038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.2245977038
Directory	/workspace/41.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3688222390
Short name	T807
Test name
Test status
Simulation time	98743418 ps
CPU time	0.99 seconds
Started	Mar 26 12:39:14 PM PDT 24
Finished	Mar 26 12:39:15 PM PDT 24
Peak memory	200592 kb
Host	smart-0bd689c4-ec96-4f39-ae4d-78276b3878dc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688222390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_clk_byp_req_intersig_mubi.3688222390
Directory	/workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.1455648360
Short name	T27
Test name
Test status
Simulation time	59678373 ps
CPU time	1.02 seconds
Started	Mar 26 12:39:17 PM PDT 24
Finished	Mar 26 12:39:18 PM PDT 24
Peak memory	200616 kb
Host	smart-882e25af-482d-4002-aa20-6dd2cf8e3d12
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455648360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_ctrl_intersig_mubi.1455648360
Directory	/workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_peri.2118890122
Short name	T538
Test name
Test status
Simulation time	29367504 ps
CPU time	0.76 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:17 PM PDT 24
Peak memory	200572 kb
Host	smart-44c0e39d-ac6f-4711-af69-e9d1631ae5e4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118890122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.2118890122
Directory	/workspace/41.clkmgr_peri/latest

Test location	/workspace/coverage/default/41.clkmgr_regwen.3091593201
Short name	T753
Test name
Test status
Simulation time	1120913322 ps
CPU time	6.65 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:23 PM PDT 24
Peak memory	200672 kb
Host	smart-df55cf83-3684-458e-8db4-9336c595e1cb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091593201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.3091593201
Directory	/workspace/41.clkmgr_regwen/latest

Test location	/workspace/coverage/default/41.clkmgr_smoke.3486386002
Short name	T46
Test name
Test status
Simulation time	89553964 ps
CPU time	1.02 seconds
Started	Mar 26 12:39:01 PM PDT 24
Finished	Mar 26 12:39:03 PM PDT 24
Peak memory	200568 kb
Host	smart-3b528022-4b21-4b84-9764-2c8f05810645
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486386002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.3486386002
Directory	/workspace/41.clkmgr_smoke/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all.1949692175
Short name	T487
Test name
Test status
Simulation time	1299485776 ps
CPU time	6.57 seconds
Started	Mar 26 12:39:15 PM PDT 24
Finished	Mar 26 12:39:22 PM PDT 24
Peak memory	200664 kb
Host	smart-f4582fd2-5a80-42d5-bf4b-621b9aee06e7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949692175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.1949692175
Directory	/workspace/41.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.655195825
Short name	T566
Test name
Test status
Simulation time	178272319529 ps
CPU time	1316.73 seconds
Started	Mar 26 12:39:14 PM PDT 24
Finished	Mar 26 01:01:11 PM PDT 24
Peak memory	209184 kb
Host	smart-ed434205-2176-4557-a4f8-448275a205f7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=655195825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.655195825
Directory	/workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.clkmgr_trans.2405781265
Short name	T624
Test name
Test status
Simulation time	17648867 ps
CPU time	0.77 seconds
Started	Mar 26 12:39:25 PM PDT 24
Finished	Mar 26 12:39:26 PM PDT 24
Peak memory	200436 kb
Host	smart-f1ff1341-ef9e-48d9-9a0c-e9fd2f0a3297
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405781265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.2405781265
Directory	/workspace/41.clkmgr_trans/latest

Test location	/workspace/coverage/default/42.clkmgr_alert_test.2201375382
Short name	T215
Test name
Test status
Simulation time	128015499 ps
CPU time	1.09 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:17 PM PDT 24
Peak memory	200632 kb
Host	smart-c99c776a-f24d-4027-b1f3-f670be0591b8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201375382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk mgr_alert_test.2201375382
Directory	/workspace/42.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.1761655276
Short name	T858
Test name
Test status
Simulation time	53306702 ps
CPU time	1.06 seconds
Started	Mar 26 12:39:17 PM PDT 24
Finished	Mar 26 12:39:18 PM PDT 24
Peak memory	200580 kb
Host	smart-8dbd627a-a184-4e35-8423-4616e02eae62
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761655276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.1761655276
Directory	/workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_status.4113907820
Short name	T855
Test name
Test status
Simulation time	15671970 ps
CPU time	0.7 seconds
Started	Mar 26 12:39:27 PM PDT 24
Finished	Mar 26 12:39:29 PM PDT 24
Peak memory	199576 kb
Host	smart-177f8853-900b-4c30-961e-505401dddaf5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113907820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.4113907820
Directory	/workspace/42.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/42.clkmgr_div_intersig_mubi.4175139286
Short name	T192
Test name
Test status
Simulation time	13936149 ps
CPU time	0.75 seconds
Started	Mar 26 12:39:15 PM PDT 24
Finished	Mar 26 12:39:16 PM PDT 24
Peak memory	200644 kb
Host	smart-eae7667b-fa66-4e8b-8e09-806bd57e98d1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175139286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.4175139286
Directory	/workspace/42.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_extclk.3983604449
Short name	T228
Test name
Test status
Simulation time	17046448 ps
CPU time	0.74 seconds
Started	Mar 26 12:39:13 PM PDT 24
Finished	Mar 26 12:39:14 PM PDT 24
Peak memory	200560 kb
Host	smart-91524e19-c12b-481b-b14a-22675521a4f0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983604449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.3983604449
Directory	/workspace/42.clkmgr_extclk/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency.2197708652
Short name	T748
Test name
Test status
Simulation time	560878640 ps
CPU time	4.94 seconds
Started	Mar 26 12:39:15 PM PDT 24
Finished	Mar 26 12:39:20 PM PDT 24
Peak memory	200600 kb
Host	smart-07945bc6-7f21-4596-97e7-10190adb3a9d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197708652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.2197708652
Directory	/workspace/42.clkmgr_frequency/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency_timeout.893175010
Short name	T81
Test name
Test status
Simulation time	378716693 ps
CPU time	3.35 seconds
Started	Mar 26 12:39:14 PM PDT 24
Finished	Mar 26 12:39:18 PM PDT 24
Peak memory	200628 kb
Host	smart-e63e521e-8967-4b9c-ac7e-922422a76c5d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893175010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_ti meout.893175010
Directory	/workspace/42.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/42.clkmgr_idle_intersig_mubi.4120824502
Short name	T761
Test name
Test status
Simulation time	26392589 ps
CPU time	0.91 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:18 PM PDT 24
Peak memory	200636 kb
Host	smart-ff5d701e-c9ea-41a5-a137-8357e26c744e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120824502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.4120824502
Directory	/workspace/42.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.2597214058
Short name	T465
Test name
Test status
Simulation time	19078169 ps
CPU time	0.77 seconds
Started	Mar 26 12:39:14 PM PDT 24
Finished	Mar 26 12:39:15 PM PDT 24
Peak memory	200648 kb
Host	smart-c55ef968-3559-4eb8-b99a-0d3beca15d7b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597214058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 42.clkmgr_lc_clk_byp_req_intersig_mubi.2597214058
Directory	/workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.3911852849
Short name	T268
Test name
Test status
Simulation time	26699785 ps
CPU time	0.89 seconds
Started	Mar 26 12:39:14 PM PDT 24
Finished	Mar 26 12:39:15 PM PDT 24
Peak memory	200584 kb
Host	smart-0790fdf1-8f52-4a50-9efd-3ddb8c9136a6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911852849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 42.clkmgr_lc_ctrl_intersig_mubi.3911852849
Directory	/workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_peri.1602587071
Short name	T361
Test name
Test status
Simulation time	17708024 ps
CPU time	0.7 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:17 PM PDT 24
Peak memory	200512 kb
Host	smart-841b67d7-8f9a-47f4-851e-e81190918681
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602587071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.1602587071
Directory	/workspace/42.clkmgr_peri/latest

Test location	/workspace/coverage/default/42.clkmgr_regwen.198247898
Short name	T848
Test name
Test status
Simulation time	597561055 ps
CPU time	2.69 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:19 PM PDT 24
Peak memory	200524 kb
Host	smart-b08e087c-adc1-4030-8028-0b03058b6db8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198247898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.198247898
Directory	/workspace/42.clkmgr_regwen/latest

Test location	/workspace/coverage/default/42.clkmgr_smoke.3836673381
Short name	T501
Test name
Test status
Simulation time	238423218 ps
CPU time	1.48 seconds
Started	Mar 26 12:39:14 PM PDT 24
Finished	Mar 26 12:39:15 PM PDT 24
Peak memory	200580 kb
Host	smart-2ede004c-ae7a-4d12-8fc0-2be05f51dced
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836673381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.3836673381
Directory	/workspace/42.clkmgr_smoke/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all.3752392276
Short name	T181
Test name
Test status
Simulation time	2046438531 ps
CPU time	8.3 seconds
Started	Mar 26 12:39:17 PM PDT 24
Finished	Mar 26 12:39:26 PM PDT 24
Peak memory	200764 kb
Host	smart-86057ee7-7ed8-412b-aba4-f6d192d6b067
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752392276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.3752392276
Directory	/workspace/42.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.3988876225
Short name	T755
Test name
Test status
Simulation time	37634556480 ps
CPU time	709.86 seconds
Started	Mar 26 12:39:13 PM PDT 24
Finished	Mar 26 12:51:03 PM PDT 24
Peak memory	209184 kb
Host	smart-8096c11c-446a-4a88-a3aa-a7ffae4a1c73
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3988876225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.3988876225
Directory	/workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.clkmgr_trans.2178370066
Short name	T352
Test name
Test status
Simulation time	23027742 ps
CPU time	0.93 seconds
Started	Mar 26 12:39:18 PM PDT 24
Finished	Mar 26 12:39:19 PM PDT 24
Peak memory	200568 kb
Host	smart-a0f13d49-b630-4566-bfa5-7b0d72082d38
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178370066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.2178370066
Directory	/workspace/42.clkmgr_trans/latest

Test location	/workspace/coverage/default/43.clkmgr_alert_test.4215274142
Short name	T209
Test name
Test status
Simulation time	107152791 ps
CPU time	1.06 seconds
Started	Mar 26 12:39:17 PM PDT 24
Finished	Mar 26 12:39:18 PM PDT 24
Peak memory	200620 kb
Host	smart-5494fcce-37ff-4409-82c0-7d7007b9fe6f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215274142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk mgr_alert_test.4215274142
Directory	/workspace/43.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.2819172990
Short name	T856
Test name
Test status
Simulation time	73994647 ps
CPU time	1 seconds
Started	Mar 26 12:39:21 PM PDT 24
Finished	Mar 26 12:39:23 PM PDT 24
Peak memory	200504 kb
Host	smart-94e8662c-0cf5-48da-bae4-857083f512d5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819172990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.2819172990
Directory	/workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_status.2563909159
Short name	T677
Test name
Test status
Simulation time	19647105 ps
CPU time	0.77 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:17 PM PDT 24
Peak memory	199520 kb
Host	smart-67c4a2a1-b225-4559-a723-fa3214d581dc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563909159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.2563909159
Directory	/workspace/43.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/43.clkmgr_div_intersig_mubi.3462478816
Short name	T422
Test name
Test status
Simulation time	167138549 ps
CPU time	1.33 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:17 PM PDT 24
Peak memory	200572 kb
Host	smart-9181673c-79b6-43fb-aae6-2d33d4ba0a99
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462478816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_div_intersig_mubi.3462478816
Directory	/workspace/43.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_extclk.3840463972
Short name	T657
Test name
Test status
Simulation time	18433034 ps
CPU time	0.8 seconds
Started	Mar 26 12:39:17 PM PDT 24
Finished	Mar 26 12:39:18 PM PDT 24
Peak memory	200552 kb
Host	smart-f4a1a3bd-c998-4e15-b513-547eae217dab
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840463972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.3840463972
Directory	/workspace/43.clkmgr_extclk/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency.797584242
Short name	T248
Test name
Test status
Simulation time	1921762356 ps
CPU time	8.75 seconds
Started	Mar 26 12:39:17 PM PDT 24
Finished	Mar 26 12:39:26 PM PDT 24
Peak memory	200744 kb
Host	smart-c946b35d-f057-45bc-9252-1f5af766b529
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797584242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.797584242
Directory	/workspace/43.clkmgr_frequency/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency_timeout.2583033257
Short name	T197
Test name
Test status
Simulation time	890230799 ps
CPU time	4.07 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:20 PM PDT 24
Peak memory	200704 kb
Host	smart-d75f50a4-e76b-4d46-a582-4f4a26397f57
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583033257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t imeout.2583033257
Directory	/workspace/43.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1720518432
Short name	T857
Test name
Test status
Simulation time	71082521 ps
CPU time	0.92 seconds
Started	Mar 26 12:39:15 PM PDT 24
Finished	Mar 26 12:39:17 PM PDT 24
Peak memory	200560 kb
Host	smart-b0148b91-1690-4100-ae82-76414e217779
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720518432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.1720518432
Directory	/workspace/43.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.2044824131
Short name	T545
Test name
Test status
Simulation time	26854047 ps
CPU time	0.81 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:17 PM PDT 24
Peak memory	200640 kb
Host	smart-9a516851-8386-43f8-a3b6-728f23f8af2c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044824131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.clkmgr_lc_clk_byp_req_intersig_mubi.2044824131
Directory	/workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.1348202860
Short name	T830
Test name
Test status
Simulation time	41304845 ps
CPU time	0.85 seconds
Started	Mar 26 12:39:23 PM PDT 24
Finished	Mar 26 12:39:25 PM PDT 24
Peak memory	200636 kb
Host	smart-ec14b64e-752d-40b1-8928-3f95478fd176
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348202860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.clkmgr_lc_ctrl_intersig_mubi.1348202860
Directory	/workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_peri.27006902
Short name	T491
Test name
Test status
Simulation time	89130164 ps
CPU time	0.89 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:17 PM PDT 24
Peak memory	200572 kb
Host	smart-dcff61bd-314f-4951-8ecc-b7eac31b8c3b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27006902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.27006902
Directory	/workspace/43.clkmgr_peri/latest

Test location	/workspace/coverage/default/43.clkmgr_regwen.3171708088
Short name	T152
Test name
Test status
Simulation time	649717382 ps
CPU time	2.78 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:19 PM PDT 24
Peak memory	200612 kb
Host	smart-9e52e599-e086-4441-8e27-f2af72a7c35a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171708088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.3171708088
Directory	/workspace/43.clkmgr_regwen/latest

Test location	/workspace/coverage/default/43.clkmgr_smoke.267686121
Short name	T563
Test name
Test status
Simulation time	28876447 ps
CPU time	0.84 seconds
Started	Mar 26 12:39:12 PM PDT 24
Finished	Mar 26 12:39:13 PM PDT 24
Peak memory	200536 kb
Host	smart-4d190a49-8dd3-48fc-a22b-8dd13410a75c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267686121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.267686121
Directory	/workspace/43.clkmgr_smoke/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all.805738447
Short name	T354
Test name
Test status
Simulation time	4193606579 ps
CPU time	32.19 seconds
Started	Mar 26 12:39:27 PM PDT 24
Finished	Mar 26 12:39:59 PM PDT 24
Peak memory	200956 kb
Host	smart-9e764175-eb28-4ce9-b0ee-0b0a6d3caac9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805738447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.805738447
Directory	/workspace/43.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/43.clkmgr_trans.3019838648
Short name	T745
Test name
Test status
Simulation time	129887511 ps
CPU time	1.27 seconds
Started	Mar 26 12:39:11 PM PDT 24
Finished	Mar 26 12:39:13 PM PDT 24
Peak memory	200544 kb
Host	smart-60a25878-890a-4f17-95fd-9986290c0785
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019838648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.3019838648
Directory	/workspace/43.clkmgr_trans/latest

Test location	/workspace/coverage/default/44.clkmgr_alert_test.1210156340
Short name	T844
Test name
Test status
Simulation time	44704077 ps
CPU time	0.84 seconds
Started	Mar 26 12:39:22 PM PDT 24
Finished	Mar 26 12:39:23 PM PDT 24
Peak memory	200624 kb
Host	smart-d29b5bb7-7dbd-415d-b4e7-f938e242e636
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210156340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk mgr_alert_test.1210156340
Directory	/workspace/44.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.2997360479
Short name	T201
Test name
Test status
Simulation time	44747014 ps
CPU time	0.84 seconds
Started	Mar 26 12:39:18 PM PDT 24
Finished	Mar 26 12:39:19 PM PDT 24
Peak memory	200628 kb
Host	smart-c2660d1f-eca8-476d-a732-871b5ab54c3c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997360479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.2997360479
Directory	/workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_status.597837118
Short name	T383
Test name
Test status
Simulation time	16556997 ps
CPU time	0.72 seconds
Started	Mar 26 12:39:17 PM PDT 24
Finished	Mar 26 12:39:18 PM PDT 24
Peak memory	199600 kb
Host	smart-6437df9a-7a0f-483c-ba4d-e5a7f7344643
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597837118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.597837118
Directory	/workspace/44.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/44.clkmgr_div_intersig_mubi.2389671172
Short name	T375
Test name
Test status
Simulation time	36229501 ps
CPU time	0.92 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:17 PM PDT 24
Peak memory	200556 kb
Host	smart-aaa225e9-93fe-46c5-9471-0c858a1c34bb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389671172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.2389671172
Directory	/workspace/44.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_extclk.3986032430
Short name	T680
Test name
Test status
Simulation time	30654219 ps
CPU time	0.8 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:17 PM PDT 24
Peak memory	200580 kb
Host	smart-e4d52ec6-70cd-4413-91f9-70651f011207
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986032430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.3986032430
Directory	/workspace/44.clkmgr_extclk/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency.2855887768
Short name	T445
Test name
Test status
Simulation time	1644531525 ps
CPU time	9.48 seconds
Started	Mar 26 12:39:14 PM PDT 24
Finished	Mar 26 12:39:24 PM PDT 24
Peak memory	200576 kb
Host	smart-26df8e37-7e3d-47a8-8c41-1fe33fd048d2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855887768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.2855887768
Directory	/workspace/44.clkmgr_frequency/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency_timeout.3338133830
Short name	T297
Test name
Test status
Simulation time	505214106 ps
CPU time	3.05 seconds
Started	Mar 26 12:39:25 PM PDT 24
Finished	Mar 26 12:39:28 PM PDT 24
Peak memory	200696 kb
Host	smart-59a678dd-307c-4c39-a353-448d0e0d6d3a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338133830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t imeout.3338133830
Directory	/workspace/44.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/44.clkmgr_idle_intersig_mubi.2641973586
Short name	T659
Test name
Test status
Simulation time	12672765 ps
CPU time	0.71 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:17 PM PDT 24
Peak memory	200396 kb
Host	smart-ca0490c0-9b43-4807-a04e-22d9abe5dbc5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641973586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_idle_intersig_mubi.2641973586
Directory	/workspace/44.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.69982066
Short name	T173
Test name
Test status
Simulation time	33019039 ps
CPU time	0.85 seconds
Started	Mar 26 12:39:17 PM PDT 24
Finished	Mar 26 12:39:19 PM PDT 24
Peak memory	200592 kb
Host	smart-a0d10a54-4c65-4660-baba-457b5ad883a8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69982066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_clk_byp_req_intersig_mubi.69982066
Directory	/workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.3588008815
Short name	T421
Test name
Test status
Simulation time	26197176 ps
CPU time	0.91 seconds
Started	Mar 26 12:39:15 PM PDT 24
Finished	Mar 26 12:39:16 PM PDT 24
Peak memory	200596 kb
Host	smart-0c7894b7-535e-4369-8847-50883b1b272d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588008815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.clkmgr_lc_ctrl_intersig_mubi.3588008815
Directory	/workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_peri.2874233232
Short name	T558
Test name
Test status
Simulation time	31125993 ps
CPU time	0.74 seconds
Started	Mar 26 12:39:26 PM PDT 24
Finished	Mar 26 12:39:27 PM PDT 24
Peak memory	200416 kb
Host	smart-22c5cb6b-ab7d-407c-981f-d4ea0e1eafca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874233232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.2874233232
Directory	/workspace/44.clkmgr_peri/latest

Test location	/workspace/coverage/default/44.clkmgr_regwen.3523046066
Short name	T580
Test name
Test status
Simulation time	1144125268 ps
CPU time	4.37 seconds
Started	Mar 26 12:39:18 PM PDT 24
Finished	Mar 26 12:39:23 PM PDT 24
Peak memory	200696 kb
Host	smart-291ef392-ea7a-4b9a-8a34-98912063f46c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523046066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.3523046066
Directory	/workspace/44.clkmgr_regwen/latest

Test location	/workspace/coverage/default/44.clkmgr_smoke.4282776968
Short name	T804
Test name
Test status
Simulation time	62190624 ps
CPU time	0.99 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:17 PM PDT 24
Peak memory	200608 kb
Host	smart-82d3f33e-30f2-40cb-af4f-32b29efb232a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282776968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.4282776968
Directory	/workspace/44.clkmgr_smoke/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all.936473946
Short name	T626
Test name
Test status
Simulation time	1423178451 ps
CPU time	10.34 seconds
Started	Mar 26 12:39:18 PM PDT 24
Finished	Mar 26 12:39:29 PM PDT 24
Peak memory	200664 kb
Host	smart-26f00246-8d53-49c0-afc6-4f6c2ecbba4d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936473946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.936473946
Directory	/workspace/44.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.518426961
Short name	T160
Test name
Test status
Simulation time	22732274634 ps
CPU time	311.09 seconds
Started	Mar 26 12:39:25 PM PDT 24
Finished	Mar 26 12:44:37 PM PDT 24
Peak memory	217356 kb
Host	smart-6a49c987-82e0-4916-ac92-bdccad06574b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=518426961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.518426961
Directory	/workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.clkmgr_trans.1649068683
Short name	T542
Test name
Test status
Simulation time	54836378 ps
CPU time	1.04 seconds
Started	Mar 26 12:39:15 PM PDT 24
Finished	Mar 26 12:39:16 PM PDT 24
Peak memory	200584 kb
Host	smart-b941e489-2c9a-4344-a101-18de43d8beff
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649068683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.1649068683
Directory	/workspace/44.clkmgr_trans/latest

Test location	/workspace/coverage/default/45.clkmgr_alert_test.1631131030
Short name	T587
Test name
Test status
Simulation time	45638036 ps
CPU time	0.81 seconds
Started	Mar 26 12:39:18 PM PDT 24
Finished	Mar 26 12:39:19 PM PDT 24
Peak memory	200604 kb
Host	smart-28f7f8c5-314a-4cbd-bc19-6ccbb9542296
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631131030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk mgr_alert_test.1631131030
Directory	/workspace/45.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.707226517
Short name	T199
Test name
Test status
Simulation time	66432753 ps
CPU time	0.85 seconds
Started	Mar 26 12:39:27 PM PDT 24
Finished	Mar 26 12:39:28 PM PDT 24
Peak memory	200552 kb
Host	smart-78abbc10-67ab-47a2-88e5-9a8edab6858f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707226517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.707226517
Directory	/workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_status.3369437242
Short name	T455
Test name
Test status
Simulation time	17212522 ps
CPU time	0.73 seconds
Started	Mar 26 12:39:18 PM PDT 24
Finished	Mar 26 12:39:19 PM PDT 24
Peak memory	199508 kb
Host	smart-1c994f97-614d-4ad1-99dd-31c6e5910027
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369437242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.3369437242
Directory	/workspace/45.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/45.clkmgr_div_intersig_mubi.1015476905
Short name	T650
Test name
Test status
Simulation time	22700957 ps
CPU time	0.85 seconds
Started	Mar 26 12:39:21 PM PDT 24
Finished	Mar 26 12:39:23 PM PDT 24
Peak memory	200568 kb
Host	smart-79939c1d-3d35-4fcd-b269-a0360ea965d5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015476905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.1015476905
Directory	/workspace/45.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_extclk.1292456231
Short name	T819
Test name
Test status
Simulation time	51294885 ps
CPU time	0.88 seconds
Started	Mar 26 12:39:25 PM PDT 24
Finished	Mar 26 12:39:26 PM PDT 24
Peak memory	200568 kb
Host	smart-098ef719-56ba-4f88-b832-53e89910d3ec
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292456231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.1292456231
Directory	/workspace/45.clkmgr_extclk/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency.187282287
Short name	T112
Test name
Test status
Simulation time	563852712 ps
CPU time	3.54 seconds
Started	Mar 26 12:39:18 PM PDT 24
Finished	Mar 26 12:39:22 PM PDT 24
Peak memory	200588 kb
Host	smart-ab839180-ef43-48f4-891e-b8461bc766ef
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187282287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.187282287
Directory	/workspace/45.clkmgr_frequency/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency_timeout.3491968416
Short name	T219
Test name
Test status
Simulation time	660908434 ps
CPU time	3.17 seconds
Started	Mar 26 12:39:15 PM PDT 24
Finished	Mar 26 12:39:19 PM PDT 24
Peak memory	200700 kb
Host	smart-dbf5a123-191b-4e1d-a7d4-73736cad78c0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491968416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t imeout.3491968416
Directory	/workspace/45.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/45.clkmgr_idle_intersig_mubi.1075523464
Short name	T842
Test name
Test status
Simulation time	26023203 ps
CPU time	0.91 seconds
Started	Mar 26 12:39:27 PM PDT 24
Finished	Mar 26 12:39:28 PM PDT 24
Peak memory	200552 kb
Host	smart-f1f6d33a-a238-4041-b7e5-9f659ea1c080
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075523464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.1075523464
Directory	/workspace/45.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.2562849245
Short name	T372
Test name
Test status
Simulation time	35817394 ps
CPU time	0.87 seconds
Started	Mar 26 12:39:18 PM PDT 24
Finished	Mar 26 12:39:19 PM PDT 24
Peak memory	200548 kb
Host	smart-d68ce3cb-76d3-47e6-81de-b4e8c7ade2d4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562849245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.clkmgr_lc_clk_byp_req_intersig_mubi.2562849245
Directory	/workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.1394908763
Short name	T780
Test name
Test status
Simulation time	17555224 ps
CPU time	0.76 seconds
Started	Mar 26 12:39:18 PM PDT 24
Finished	Mar 26 12:39:19 PM PDT 24
Peak memory	200560 kb
Host	smart-1041b506-7cee-44de-a9ea-65cf14ae1020
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394908763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.clkmgr_lc_ctrl_intersig_mubi.1394908763
Directory	/workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_peri.3413522207
Short name	T250
Test name
Test status
Simulation time	19566329 ps
CPU time	0.79 seconds
Started	Mar 26 12:39:18 PM PDT 24
Finished	Mar 26 12:39:19 PM PDT 24
Peak memory	200560 kb
Host	smart-00f7195e-39c1-459b-9287-2bccfc5108a4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413522207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.3413522207
Directory	/workspace/45.clkmgr_peri/latest

Test location	/workspace/coverage/default/45.clkmgr_regwen.3696215046
Short name	T35
Test name
Test status
Simulation time	164406900 ps
CPU time	1.28 seconds
Started	Mar 26 12:39:28 PM PDT 24
Finished	Mar 26 12:39:29 PM PDT 24
Peak memory	200508 kb
Host	smart-19ddbb69-1ffc-4bdb-8e4b-531153e9a6f6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696215046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.3696215046
Directory	/workspace/45.clkmgr_regwen/latest

Test location	/workspace/coverage/default/45.clkmgr_smoke.1711077130
Short name	T8
Test name
Test status
Simulation time	21460479 ps
CPU time	0.88 seconds
Started	Mar 26 12:39:17 PM PDT 24
Finished	Mar 26 12:39:18 PM PDT 24
Peak memory	200596 kb
Host	smart-de76a14d-afe0-4b64-b732-def57cf121ab
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711077130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.1711077130
Directory	/workspace/45.clkmgr_smoke/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all.2069741347
Short name	T195
Test name
Test status
Simulation time	156899916 ps
CPU time	1.46 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:18 PM PDT 24
Peak memory	200516 kb
Host	smart-bb9a2efa-8df9-4622-b16e-9514cb2a4bc6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069741347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.2069741347
Directory	/workspace/45.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.2002962337
Short name	T319
Test name
Test status
Simulation time	26945645178 ps
CPU time	408.55 seconds
Started	Mar 26 12:39:28 PM PDT 24
Finished	Mar 26 12:46:17 PM PDT 24
Peak memory	209184 kb
Host	smart-d83a0ee5-48c5-47d8-9638-c4f5ce03082b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2002962337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.2002962337
Directory	/workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.clkmgr_trans.2866099225
Short name	T242
Test name
Test status
Simulation time	20499303 ps
CPU time	0.85 seconds
Started	Mar 26 12:39:17 PM PDT 24
Finished	Mar 26 12:39:18 PM PDT 24
Peak memory	200596 kb
Host	smart-fe9a42bf-0e60-4db3-ad00-a333a0c7d216
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866099225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.2866099225
Directory	/workspace/45.clkmgr_trans/latest

Test location	/workspace/coverage/default/46.clkmgr_alert_test.1761491265
Short name	T185
Test name
Test status
Simulation time	13263025 ps
CPU time	0.7 seconds
Started	Mar 26 12:39:22 PM PDT 24
Finished	Mar 26 12:39:22 PM PDT 24
Peak memory	200632 kb
Host	smart-d6744d03-2eb8-4302-9ef6-8efdafc3648e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761491265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk mgr_alert_test.1761491265
Directory	/workspace/46.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.3599532883
Short name	T495
Test name
Test status
Simulation time	19124897 ps
CPU time	0.79 seconds
Started	Mar 26 12:39:26 PM PDT 24
Finished	Mar 26 12:39:27 PM PDT 24
Peak memory	200636 kb
Host	smart-0f0d80cc-6c32-47c2-a5ac-dab3ef0fa61d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599532883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.3599532883
Directory	/workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_status.1062146702
Short name	T673
Test name
Test status
Simulation time	14708043 ps
CPU time	0.67 seconds
Started	Mar 26 12:39:21 PM PDT 24
Finished	Mar 26 12:39:22 PM PDT 24
Peak memory	199512 kb
Host	smart-230d7475-8e5c-45d9-99b2-daed3f2219cb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062146702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1062146702
Directory	/workspace/46.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/46.clkmgr_div_intersig_mubi.3999893131
Short name	T801
Test name
Test status
Simulation time	15732087 ps
CPU time	0.73 seconds
Started	Mar 26 12:39:26 PM PDT 24
Finished	Mar 26 12:39:27 PM PDT 24
Peak memory	200356 kb
Host	smart-0c7e3097-a2f8-4bf6-96db-4f784659dd48
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999893131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.3999893131
Directory	/workspace/46.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_extclk.1111627653
Short name	T20
Test name
Test status
Simulation time	32199250 ps
CPU time	0.79 seconds
Started	Mar 26 12:39:17 PM PDT 24
Finished	Mar 26 12:39:18 PM PDT 24
Peak memory	200556 kb
Host	smart-a54d12c6-c9df-4464-ad48-c476af75151f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111627653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.1111627653
Directory	/workspace/46.clkmgr_extclk/latest

Test location	/workspace/coverage/default/46.clkmgr_frequency.2513307488
Short name	T646
Test name
Test status
Simulation time	2368501615 ps
CPU time	13.41 seconds
Started	Mar 26 12:39:20 PM PDT 24
Finished	Mar 26 12:39:34 PM PDT 24
Peak memory	200760 kb
Host	smart-3c89d818-85e2-4d3f-ba25-d85e63dbe8cf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513307488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.2513307488
Directory	/workspace/46.clkmgr_frequency/latest

Test location	/workspace/coverage/default/46.clkmgr_frequency_timeout.2505820404
Short name	T427
Test name
Test status
Simulation time	620822640 ps
CPU time	4.91 seconds
Started	Mar 26 12:39:20 PM PDT 24
Finished	Mar 26 12:39:25 PM PDT 24
Peak memory	200648 kb
Host	smart-e381e84c-5890-4cbd-a5cf-47553140b8e2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505820404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t imeout.2505820404
Directory	/workspace/46.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/46.clkmgr_idle_intersig_mubi.3205754829
Short name	T259
Test name
Test status
Simulation time	22750161 ps
CPU time	0.85 seconds
Started	Mar 26 12:39:20 PM PDT 24
Finished	Mar 26 12:39:21 PM PDT 24
Peak memory	200640 kb
Host	smart-16e44c6b-9f80-44da-be13-eb236fc6545a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205754829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.3205754829
Directory	/workspace/46.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.4216397338
Short name	T385
Test name
Test status
Simulation time	51709568 ps
CPU time	0.86 seconds
Started	Mar 26 12:39:26 PM PDT 24
Finished	Mar 26 12:39:27 PM PDT 24
Peak memory	200576 kb
Host	smart-52486a7e-eaac-4ec5-ab2b-1ec6d842bf66
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216397338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_clk_byp_req_intersig_mubi.4216397338
Directory	/workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.2653434031
Short name	T277
Test name
Test status
Simulation time	28455502 ps
CPU time	0.74 seconds
Started	Mar 26 12:39:21 PM PDT 24
Finished	Mar 26 12:39:22 PM PDT 24
Peak memory	200636 kb
Host	smart-7ec793bd-d962-4f60-a5f0-65b4e35a851d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653434031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_ctrl_intersig_mubi.2653434031
Directory	/workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_peri.3842664663
Short name	T651
Test name
Test status
Simulation time	17819632 ps
CPU time	0.8 seconds
Started	Mar 26 12:39:27 PM PDT 24
Finished	Mar 26 12:39:28 PM PDT 24
Peak memory	200528 kb
Host	smart-c1add30b-8eec-40b2-afb5-4ac2b930e066
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842664663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.3842664663
Directory	/workspace/46.clkmgr_peri/latest

Test location	/workspace/coverage/default/46.clkmgr_regwen.2213582103
Short name	T485
Test name
Test status
Simulation time	1306370318 ps
CPU time	4.97 seconds
Started	Mar 26 12:39:30 PM PDT 24
Finished	Mar 26 12:39:37 PM PDT 24
Peak memory	200660 kb
Host	smart-1c3f00f0-1567-4eed-a66b-80961e7dbb1c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213582103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.2213582103
Directory	/workspace/46.clkmgr_regwen/latest

Test location	/workspace/coverage/default/46.clkmgr_smoke.2305932811
Short name	T672
Test name
Test status
Simulation time	29104013 ps
CPU time	0.86 seconds
Started	Mar 26 12:39:22 PM PDT 24
Finished	Mar 26 12:39:23 PM PDT 24
Peak memory	200576 kb
Host	smart-931d1374-707a-4c5e-8fdf-1f24bedd1dfa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305932811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.2305932811
Directory	/workspace/46.clkmgr_smoke/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all.1203865702
Short name	T347
Test name
Test status
Simulation time	4663778727 ps
CPU time	31.88 seconds
Started	Mar 26 12:39:18 PM PDT 24
Finished	Mar 26 12:39:50 PM PDT 24
Peak memory	200884 kb
Host	smart-178ddbc6-5ea7-4b07-90b6-63fa478c7e7f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203865702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.1203865702
Directory	/workspace/46.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.2147796771
Short name	T69
Test name
Test status
Simulation time	76102285484 ps
CPU time	657.86 seconds
Started	Mar 26 12:39:26 PM PDT 24
Finished	Mar 26 12:50:24 PM PDT 24
Peak memory	217152 kb
Host	smart-d3b92c50-a039-4edc-b3f4-de339b8a1cea
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2147796771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.2147796771
Directory	/workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.clkmgr_trans.2392459049
Short name	T733
Test name
Test status
Simulation time	13176423 ps
CPU time	0.72 seconds
Started	Mar 26 12:39:18 PM PDT 24
Finished	Mar 26 12:39:19 PM PDT 24
Peak memory	200648 kb
Host	smart-2b79f8bc-ed99-40f0-8cdb-f12bf7aa7abc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392459049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.2392459049
Directory	/workspace/46.clkmgr_trans/latest

Test location	/workspace/coverage/default/47.clkmgr_alert_test.1000224956
Short name	T619
Test name
Test status
Simulation time	88661944 ps
CPU time	0.99 seconds
Started	Mar 26 12:39:29 PM PDT 24
Finished	Mar 26 12:39:31 PM PDT 24
Peak memory	200636 kb
Host	smart-a3244aef-828b-47f5-8c6e-4d377b56b79d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000224956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk mgr_alert_test.1000224956
Directory	/workspace/47.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.2295487265
Short name	T596
Test name
Test status
Simulation time	53287371 ps
CPU time	0.92 seconds
Started	Mar 26 12:39:29 PM PDT 24
Finished	Mar 26 12:39:31 PM PDT 24
Peak memory	200652 kb
Host	smart-e55b8a5d-e883-40bd-a684-bd7cade80715
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295487265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.2295487265
Directory	/workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_status.2366538675
Short name	T752
Test name
Test status
Simulation time	18044623 ps
CPU time	0.71 seconds
Started	Mar 26 12:39:26 PM PDT 24
Finished	Mar 26 12:39:27 PM PDT 24
Peak memory	199432 kb
Host	smart-1335a3da-7bde-4565-954f-323ac343f617
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366538675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.2366538675
Directory	/workspace/47.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/47.clkmgr_div_intersig_mubi.1196648556
Short name	T845
Test name
Test status
Simulation time	75630061 ps
CPU time	1.06 seconds
Started	Mar 26 12:39:30 PM PDT 24
Finished	Mar 26 12:39:32 PM PDT 24
Peak memory	200596 kb
Host	smart-5fef64fb-07d6-4f2e-8759-c159a9390d2d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196648556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.1196648556
Directory	/workspace/47.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_extclk.2833095606
Short name	T727
Test name
Test status
Simulation time	41208218 ps
CPU time	0.84 seconds
Started	Mar 26 12:39:26 PM PDT 24
Finished	Mar 26 12:39:27 PM PDT 24
Peak memory	200564 kb
Host	smart-481857fc-ff64-46e8-aecc-ec05568af0c9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833095606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.2833095606
Directory	/workspace/47.clkmgr_extclk/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency.148262042
Short name	T283
Test name
Test status
Simulation time	1641415576 ps
CPU time	10.98 seconds
Started	Mar 26 12:39:27 PM PDT 24
Finished	Mar 26 12:39:38 PM PDT 24
Peak memory	200444 kb
Host	smart-4baaf24b-28a8-47a4-b50d-d8ff0ad85a8e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148262042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.148262042
Directory	/workspace/47.clkmgr_frequency/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency_timeout.2094761512
Short name	T494
Test name
Test status
Simulation time	1824642553 ps
CPU time	10.67 seconds
Started	Mar 26 12:39:16 PM PDT 24
Finished	Mar 26 12:39:27 PM PDT 24
Peak memory	200648 kb
Host	smart-7756a608-5a97-48f1-9317-0f5c9855d7a3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094761512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t imeout.2094761512
Directory	/workspace/47.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/47.clkmgr_idle_intersig_mubi.3427003883
Short name	T317
Test name
Test status
Simulation time	105894823 ps
CPU time	1.24 seconds
Started	Mar 26 12:39:31 PM PDT 24
Finished	Mar 26 12:39:33 PM PDT 24
Peak memory	200244 kb
Host	smart-3599e233-2568-453e-99f0-68f6d9fc8007
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427003883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.3427003883
Directory	/workspace/47.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.665510946
Short name	T816
Test name
Test status
Simulation time	70410355 ps
CPU time	1.02 seconds
Started	Mar 26 12:39:33 PM PDT 24
Finished	Mar 26 12:39:34 PM PDT 24
Peak memory	200580 kb
Host	smart-a39b3951-69a9-4cbf-b2e1-ece7a39e8726
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665510946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.clkmgr_lc_clk_byp_req_intersig_mubi.665510946
Directory	/workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.1802113173
Short name	T388
Test name
Test status
Simulation time	39759069 ps
CPU time	0.98 seconds
Started	Mar 26 12:39:31 PM PDT 24
Finished	Mar 26 12:39:33 PM PDT 24
Peak memory	200420 kb
Host	smart-9b0b14b1-aded-4442-8015-fab91644e718
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802113173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.clkmgr_lc_ctrl_intersig_mubi.1802113173
Directory	/workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_peri.4066351360
Short name	T796
Test name
Test status
Simulation time	16574597 ps
CPU time	0.75 seconds
Started	Mar 26 12:39:27 PM PDT 24
Finished	Mar 26 12:39:28 PM PDT 24
Peak memory	200428 kb
Host	smart-d1aae319-2d75-4089-96ab-bca003394aa8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066351360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.4066351360
Directory	/workspace/47.clkmgr_peri/latest

Test location	/workspace/coverage/default/47.clkmgr_regwen.1511688769
Short name	T79
Test name
Test status
Simulation time	376091013 ps
CPU time	2.07 seconds
Started	Mar 26 12:39:28 PM PDT 24
Finished	Mar 26 12:39:30 PM PDT 24
Peak memory	200532 kb
Host	smart-95c0ea02-dbc1-4738-bee5-7995f7a98a9a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511688769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.1511688769
Directory	/workspace/47.clkmgr_regwen/latest

Test location	/workspace/coverage/default/47.clkmgr_smoke.3081043329
Short name	T666
Test name
Test status
Simulation time	122470083 ps
CPU time	1.21 seconds
Started	Mar 26 12:39:28 PM PDT 24
Finished	Mar 26 12:39:29 PM PDT 24
Peak memory	200604 kb
Host	smart-90d942ec-c615-4d21-8445-099e4701dd98
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081043329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.3081043329
Directory	/workspace/47.clkmgr_smoke/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all.1732570785
Short name	T598
Test name
Test status
Simulation time	9050041072 ps
CPU time	34.67 seconds
Started	Mar 26 12:39:30 PM PDT 24
Finished	Mar 26 12:40:07 PM PDT 24
Peak memory	200888 kb
Host	smart-7ce6759f-f641-4e7e-b287-1df99c94df82
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732570785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.1732570785
Directory	/workspace/47.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.2952993622
Short name	T428
Test name
Test status
Simulation time	51457574493 ps
CPU time	956.13 seconds
Started	Mar 26 12:39:30 PM PDT 24
Finished	Mar 26 12:55:27 PM PDT 24
Peak memory	209228 kb
Host	smart-27dcd074-4a00-4a22-a3e7-937b666174dc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2952993622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.2952993622
Directory	/workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.clkmgr_trans.3567565919
Short name	T257
Test name
Test status
Simulation time	141946145 ps
CPU time	1.21 seconds
Started	Mar 26 12:39:31 PM PDT 24
Finished	Mar 26 12:39:34 PM PDT 24
Peak memory	200600 kb
Host	smart-4c615938-1423-49eb-ad9d-99787aca5178
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567565919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.3567565919
Directory	/workspace/47.clkmgr_trans/latest

Test location	/workspace/coverage/default/48.clkmgr_alert_test.1148135313
Short name	T560
Test name
Test status
Simulation time	24016362 ps
CPU time	0.77 seconds
Started	Mar 26 12:39:29 PM PDT 24
Finished	Mar 26 12:39:30 PM PDT 24
Peak memory	200632 kb
Host	smart-fd5316b3-25f6-466f-827f-dfb2e8296385
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148135313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk mgr_alert_test.1148135313
Directory	/workspace/48.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.1494615208
Short name	T611
Test name
Test status
Simulation time	56750166 ps
CPU time	1.01 seconds
Started	Mar 26 12:39:27 PM PDT 24
Finished	Mar 26 12:39:28 PM PDT 24
Peak memory	200576 kb
Host	smart-43bb2878-5385-40d4-b054-128ee3a9cfe4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494615208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.1494615208
Directory	/workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_status.3966068941
Short name	T645
Test name
Test status
Simulation time	19926418 ps
CPU time	0.74 seconds
Started	Mar 26 12:39:27 PM PDT 24
Finished	Mar 26 12:39:28 PM PDT 24
Peak memory	200512 kb
Host	smart-6d9c4aba-ca83-4ce8-b9ca-ac6cdffed87e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966068941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.3966068941
Directory	/workspace/48.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/48.clkmgr_div_intersig_mubi.2595241247
Short name	T794
Test name
Test status
Simulation time	49162277 ps
CPU time	0.9 seconds
Started	Mar 26 12:39:31 PM PDT 24
Finished	Mar 26 12:39:32 PM PDT 24
Peak memory	200612 kb
Host	smart-2c028c31-bc7e-4ebb-8bb0-1295cda8aa5e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595241247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.2595241247
Directory	/workspace/48.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_extclk.383286732
Short name	T847
Test name
Test status
Simulation time	77224674 ps
CPU time	1 seconds
Started	Mar 26 12:39:32 PM PDT 24
Finished	Mar 26 12:39:34 PM PDT 24
Peak memory	200596 kb
Host	smart-f19e2466-d657-415f-85c1-262475240d37
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383286732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.383286732
Directory	/workspace/48.clkmgr_extclk/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency.1421731912
Short name	T315
Test name
Test status
Simulation time	2637926966 ps
CPU time	9.11 seconds
Started	Mar 26 12:39:30 PM PDT 24
Finished	Mar 26 12:39:40 PM PDT 24
Peak memory	200800 kb
Host	smart-614379c8-5573-4ef7-b63c-b3d81e512c0f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421731912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1421731912
Directory	/workspace/48.clkmgr_frequency/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency_timeout.2743105043
Short name	T824
Test name
Test status
Simulation time	494341826 ps
CPU time	4.08 seconds
Started	Mar 26 12:39:30 PM PDT 24
Finished	Mar 26 12:39:35 PM PDT 24
Peak memory	200664 kb
Host	smart-55247089-194e-4851-b0f4-624a3cf287e9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743105043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t imeout.2743105043
Directory	/workspace/48.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/48.clkmgr_idle_intersig_mubi.2643442986
Short name	T784
Test name
Test status
Simulation time	23024178 ps
CPU time	0.89 seconds
Started	Mar 26 12:39:31 PM PDT 24
Finished	Mar 26 12:39:33 PM PDT 24
Peak memory	200552 kb
Host	smart-434b10b3-8e7a-4242-a1ee-74e1e194c538
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643442986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.2643442986
Directory	/workspace/48.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.1711142393
Short name	T262
Test name
Test status
Simulation time	23137367 ps
CPU time	0.86 seconds
Started	Mar 26 12:39:31 PM PDT 24
Finished	Mar 26 12:39:33 PM PDT 24
Peak memory	200600 kb
Host	smart-5dccd215-1968-47bc-814d-117b349c363a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711142393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.clkmgr_lc_clk_byp_req_intersig_mubi.1711142393
Directory	/workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1195385335
Short name	T775
Test name
Test status
Simulation time	18354622 ps
CPU time	0.8 seconds
Started	Mar 26 12:39:28 PM PDT 24
Finished	Mar 26 12:39:29 PM PDT 24
Peak memory	200588 kb
Host	smart-3c2e08f7-6af5-48aa-a7fc-13feeee130ff
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195385335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.clkmgr_lc_ctrl_intersig_mubi.1195385335
Directory	/workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_peri.2922841762
Short name	T148
Test name
Test status
Simulation time	13110082 ps
CPU time	0.71 seconds
Started	Mar 26 12:39:30 PM PDT 24
Finished	Mar 26 12:39:32 PM PDT 24
Peak memory	200568 kb
Host	smart-5cc14c57-a7ba-4b2f-a3d4-b847168fbf88
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922841762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.2922841762
Directory	/workspace/48.clkmgr_peri/latest

Test location	/workspace/coverage/default/48.clkmgr_regwen.4104183662
Short name	T194
Test name
Test status
Simulation time	462927185 ps
CPU time	2.46 seconds
Started	Mar 26 12:39:30 PM PDT 24
Finished	Mar 26 12:39:33 PM PDT 24
Peak memory	200516 kb
Host	smart-549a8cf2-be24-41e9-8302-6399bffd74a6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104183662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.4104183662
Directory	/workspace/48.clkmgr_regwen/latest

Test location	/workspace/coverage/default/48.clkmgr_smoke.1619610344
Short name	T424
Test name
Test status
Simulation time	27404089 ps
CPU time	0.85 seconds
Started	Mar 26 12:39:30 PM PDT 24
Finished	Mar 26 12:39:32 PM PDT 24
Peak memory	200600 kb
Host	smart-99a2c4c9-77e7-4760-aee5-484a1abb4c0a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619610344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.1619610344
Directory	/workspace/48.clkmgr_smoke/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all.1951570406
Short name	T149
Test name
Test status
Simulation time	7789817632 ps
CPU time	30.86 seconds
Started	Mar 26 12:39:29 PM PDT 24
Finished	Mar 26 12:40:00 PM PDT 24
Peak memory	200816 kb
Host	smart-732b779e-edd0-4432-a0ff-62e1eaac588d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951570406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.1951570406
Directory	/workspace/48.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.2995248925
Short name	T143
Test name
Test status
Simulation time	85785663864 ps
CPU time	756.16 seconds
Started	Mar 26 12:39:27 PM PDT 24
Finished	Mar 26 12:52:03 PM PDT 24
Peak memory	209208 kb
Host	smart-f653fe54-5d1c-41c1-8fa2-20823c94b4be
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2995248925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.2995248925
Directory	/workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.clkmgr_trans.3374522697
Short name	T698
Test name
Test status
Simulation time	23015117 ps
CPU time	0.88 seconds
Started	Mar 26 12:39:26 PM PDT 24
Finished	Mar 26 12:39:27 PM PDT 24
Peak memory	200572 kb
Host	smart-c13c7170-d9f0-43e9-937d-e8f6949def1b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374522697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.3374522697
Directory	/workspace/48.clkmgr_trans/latest

Test location	/workspace/coverage/default/49.clkmgr_alert_test.2169638933
Short name	T450
Test name
Test status
Simulation time	108821683 ps
CPU time	0.99 seconds
Started	Mar 26 12:39:28 PM PDT 24
Finished	Mar 26 12:39:30 PM PDT 24
Peak memory	200632 kb
Host	smart-29c03ae4-780e-4b6a-ba25-24a03e60f1a1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169638933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk mgr_alert_test.2169638933
Directory	/workspace/49.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.1152709958
Short name	T500
Test name
Test status
Simulation time	38277614 ps
CPU time	0.77 seconds
Started	Mar 26 12:39:31 PM PDT 24
Finished	Mar 26 12:39:33 PM PDT 24
Peak memory	200636 kb
Host	smart-b160134a-6af4-4e62-a6c8-f17e803c668c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152709958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.1152709958
Directory	/workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_status.375517050
Short name	T750
Test name
Test status
Simulation time	12671269 ps
CPU time	0.71 seconds
Started	Mar 26 12:39:31 PM PDT 24
Finished	Mar 26 12:39:33 PM PDT 24
Peak memory	199576 kb
Host	smart-4b28fab3-cb3d-4c46-8936-04d1fae4d85f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375517050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.375517050
Directory	/workspace/49.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/49.clkmgr_div_intersig_mubi.3776892294
Short name	T261
Test name
Test status
Simulation time	19652565 ps
CPU time	0.84 seconds
Started	Mar 26 12:39:30 PM PDT 24
Finished	Mar 26 12:39:33 PM PDT 24
Peak memory	200588 kb
Host	smart-e5f401d5-c9be-4b12-ae92-91e054337f41
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776892294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.3776892294
Directory	/workspace/49.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_extclk.442726954
Short name	T290
Test name
Test status
Simulation time	37819507 ps
CPU time	0.89 seconds
Started	Mar 26 12:39:35 PM PDT 24
Finished	Mar 26 12:39:36 PM PDT 24
Peak memory	200664 kb
Host	smart-cd7d8043-03f8-4db3-bf29-f56014393480
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442726954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.442726954
Directory	/workspace/49.clkmgr_extclk/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency.3402954263
Short name	T390
Test name
Test status
Simulation time	2502708172 ps
CPU time	10.99 seconds
Started	Mar 26 12:39:32 PM PDT 24
Finished	Mar 26 12:39:43 PM PDT 24
Peak memory	200868 kb
Host	smart-50dca85c-2796-4cd9-8acb-63ea8725c253
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402954263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.3402954263
Directory	/workspace/49.clkmgr_frequency/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency_timeout.1364825170
Short name	T687
Test name
Test status
Simulation time	742194608 ps
CPU time	6.11 seconds
Started	Mar 26 12:39:27 PM PDT 24
Finished	Mar 26 12:39:33 PM PDT 24
Peak memory	200628 kb
Host	smart-4afef69f-681e-492d-8a36-8b5f75a581d8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364825170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t imeout.1364825170
Directory	/workspace/49.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/49.clkmgr_idle_intersig_mubi.2895509195
Short name	T719
Test name
Test status
Simulation time	80278465 ps
CPU time	1.01 seconds
Started	Mar 26 12:39:29 PM PDT 24
Finished	Mar 26 12:39:31 PM PDT 24
Peak memory	200560 kb
Host	smart-6b634bfd-829e-496e-b5cc-5134c96ec042
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895509195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.2895509195
Directory	/workspace/49.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3969999542
Short name	T116
Test name
Test status
Simulation time	59358178 ps
CPU time	0.88 seconds
Started	Mar 26 12:39:28 PM PDT 24
Finished	Mar 26 12:39:30 PM PDT 24
Peak memory	200648 kb
Host	smart-0863cc18-edc1-477d-8603-a2005a7f7c28
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969999542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.clkmgr_lc_clk_byp_req_intersig_mubi.3969999542
Directory	/workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.1639803614
Short name	T511
Test name
Test status
Simulation time	24517364 ps
CPU time	0.76 seconds
Started	Mar 26 12:39:31 PM PDT 24
Finished	Mar 26 12:39:33 PM PDT 24
Peak memory	200580 kb
Host	smart-62537f1e-dda7-4b90-a2c8-cd0dc4bb52a1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639803614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.clkmgr_lc_ctrl_intersig_mubi.1639803614
Directory	/workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_peri.2869706419
Short name	T408
Test name
Test status
Simulation time	38201262 ps
CPU time	0.82 seconds
Started	Mar 26 12:39:31 PM PDT 24
Finished	Mar 26 12:39:33 PM PDT 24
Peak memory	200616 kb
Host	smart-6f3fac73-6365-426e-b7c0-2c7c077e0b60
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869706419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.2869706419
Directory	/workspace/49.clkmgr_peri/latest

Test location	/workspace/coverage/default/49.clkmgr_regwen.3588696954
Short name	T841
Test name
Test status
Simulation time	1233524425 ps
CPU time	7.28 seconds
Started	Mar 26 12:39:31 PM PDT 24
Finished	Mar 26 12:39:39 PM PDT 24
Peak memory	200728 kb
Host	smart-2862e921-98b8-4d66-90a1-311b7fa9f40e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588696954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.3588696954
Directory	/workspace/49.clkmgr_regwen/latest

Test location	/workspace/coverage/default/49.clkmgr_smoke.3255685181
Short name	T256
Test name
Test status
Simulation time	19077284 ps
CPU time	0.83 seconds
Started	Mar 26 12:39:29 PM PDT 24
Finished	Mar 26 12:39:30 PM PDT 24
Peak memory	200560 kb
Host	smart-d9e59ccf-592b-4bcb-b7f3-6fb6f018f2ec
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255685181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.3255685181
Directory	/workspace/49.clkmgr_smoke/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all.1983412409
Short name	T318
Test name
Test status
Simulation time	2485933212 ps
CPU time	16.56 seconds
Started	Mar 26 12:39:29 PM PDT 24
Finished	Mar 26 12:39:46 PM PDT 24
Peak memory	200820 kb
Host	smart-8c4ba8a5-cf65-478b-bdaa-fe18d13ca82d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983412409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.1983412409
Directory	/workspace/49.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.3487081457
Short name	T144
Test name
Test status
Simulation time	20297968829 ps
CPU time	300.13 seconds
Started	Mar 26 12:39:31 PM PDT 24
Finished	Mar 26 12:44:32 PM PDT 24
Peak memory	215188 kb
Host	smart-45c2cb41-11a3-487b-a06e-e3509b69243b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3487081457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.3487081457
Directory	/workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.clkmgr_trans.78086917
Short name	T316
Test name
Test status
Simulation time	20745261 ps
CPU time	0.88 seconds
Started	Mar 26 12:39:27 PM PDT 24
Finished	Mar 26 12:39:28 PM PDT 24
Peak memory	200512 kb
Host	smart-51d9dfbf-f063-4542-894e-36f4b5d7fd7e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78086917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.78086917
Directory	/workspace/49.clkmgr_trans/latest

Test location	/workspace/coverage/default/5.clkmgr_alert_test.2274345569
Short name	T37
Test name
Test status
Simulation time	123987981 ps
CPU time	1.04 seconds
Started	Mar 26 12:37:31 PM PDT 24
Finished	Mar 26 12:37:32 PM PDT 24
Peak memory	200620 kb
Host	smart-98c2a06b-d2c2-4c7f-8a56-9fcc2de7f9ee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274345569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm gr_alert_test.2274345569
Directory	/workspace/5.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.697537520
Short name	T806
Test name
Test status
Simulation time	28431854 ps
CPU time	0.92 seconds
Started	Mar 26 12:37:34 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	200572 kb
Host	smart-48dbae84-a9b9-4f63-98d4-dfbe80d903d1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697537520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.697537520
Directory	/workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_status.4182226701
Short name	T167
Test name
Test status
Simulation time	25180254 ps
CPU time	0.72 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	199504 kb
Host	smart-11d5eecc-248b-4113-b5e5-311c2da68282
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182226701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.4182226701
Directory	/workspace/5.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/5.clkmgr_div_intersig_mubi.4062771930
Short name	T405
Test name
Test status
Simulation time	57699211 ps
CPU time	0.83 seconds
Started	Mar 26 12:37:30 PM PDT 24
Finished	Mar 26 12:37:31 PM PDT 24
Peak memory	200624 kb
Host	smart-e65fb9d2-2c11-4535-96fb-a10fa079f813
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062771930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.4062771930
Directory	/workspace/5.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_extclk.2650002697
Short name	T452
Test name
Test status
Simulation time	17571099 ps
CPU time	0.77 seconds
Started	Mar 26 12:37:39 PM PDT 24
Finished	Mar 26 12:37:40 PM PDT 24
Peak memory	200648 kb
Host	smart-39c6826e-d703-41a2-aeda-641224b2817f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650002697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.2650002697
Directory	/workspace/5.clkmgr_extclk/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency.4054726942
Short name	T374
Test name
Test status
Simulation time	1518575604 ps
CPU time	11.56 seconds
Started	Mar 26 12:37:33 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200844 kb
Host	smart-5700d06b-638d-40d6-8e9a-162b2ca727f7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054726942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.4054726942
Directory	/workspace/5.clkmgr_frequency/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency_timeout.2855015963
Short name	T321
Test name
Test status
Simulation time	622565598 ps
CPU time	5.2 seconds
Started	Mar 26 12:37:34 PM PDT 24
Finished	Mar 26 12:37:39 PM PDT 24
Peak memory	200940 kb
Host	smart-b4e9e9a0-1c2d-4292-b5b8-23c3d17413b7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855015963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti meout.2855015963
Directory	/workspace/5.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/5.clkmgr_idle_intersig_mubi.3117663588
Short name	T799
Test name
Test status
Simulation time	111059643 ps
CPU time	1.08 seconds
Started	Mar 26 12:37:31 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200576 kb
Host	smart-8b1b928c-b362-4555-9de8-d0c168e948df
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117663588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.3117663588
Directory	/workspace/5.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.333782577
Short name	T214
Test name
Test status
Simulation time	15139187 ps
CPU time	0.73 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	200544 kb
Host	smart-9b230152-b536-4606-9f93-f67458e7f8cd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333782577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.clkmgr_lc_clk_byp_req_intersig_mubi.333782577
Directory	/workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.3294477923
Short name	T305
Test name
Test status
Simulation time	96072284 ps
CPU time	1.13 seconds
Started	Mar 26 12:37:34 PM PDT 24
Finished	Mar 26 12:37:35 PM PDT 24
Peak memory	200884 kb
Host	smart-c23fcb82-fbc2-4f9a-9def-9c8a639e92f4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294477923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.clkmgr_lc_ctrl_intersig_mubi.3294477923
Directory	/workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_peri.2572166275
Short name	T145
Test name
Test status
Simulation time	32819153 ps
CPU time	0.76 seconds
Started	Mar 26 12:37:34 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	200528 kb
Host	smart-b5d1ec50-79ca-4502-a1ea-adda16f50c5c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572166275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.2572166275
Directory	/workspace/5.clkmgr_peri/latest

Test location	/workspace/coverage/default/5.clkmgr_smoke.2442710724
Short name	T486
Test name
Test status
Simulation time	33037684 ps
CPU time	0.87 seconds
Started	Mar 26 12:37:39 PM PDT 24
Finished	Mar 26 12:37:40 PM PDT 24
Peak memory	200628 kb
Host	smart-0dbccf40-bca0-4d4c-b809-2a1357b4ba5b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442710724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.2442710724
Directory	/workspace/5.clkmgr_smoke/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all.3340400034
Short name	T12
Test name
Test status
Simulation time	4635202026 ps
CPU time	20 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:37:55 PM PDT 24
Peak memory	200796 kb
Host	smart-083382aa-abf1-47c0-8003-2a2030e28f9f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340400034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.3340400034
Directory	/workspace/5.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.3024910303
Short name	T717
Test name
Test status
Simulation time	57861351697 ps
CPU time	852.22 seconds
Started	Mar 26 12:37:34 PM PDT 24
Finished	Mar 26 12:51:47 PM PDT 24
Peak memory	209228 kb
Host	smart-f9380f80-c3f2-4143-b65e-d581dae6a57f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3024910303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.3024910303
Directory	/workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.clkmgr_trans.3662661989
Short name	T565
Test name
Test status
Simulation time	39969591 ps
CPU time	0.98 seconds
Started	Mar 26 12:37:33 PM PDT 24
Finished	Mar 26 12:37:34 PM PDT 24
Peak memory	200864 kb
Host	smart-2ad1f38e-a676-46cd-bfb0-0d11192659f5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662661989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.3662661989
Directory	/workspace/5.clkmgr_trans/latest

Test location	/workspace/coverage/default/6.clkmgr_alert_test.3880002973
Short name	T675
Test name
Test status
Simulation time	17382790 ps
CPU time	0.73 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	200612 kb
Host	smart-80db591b-a091-4414-a829-d735f21b033c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880002973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm gr_alert_test.3880002973
Directory	/workspace/6.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.1487050092
Short name	T87
Test name
Test status
Simulation time	146016209 ps
CPU time	1.28 seconds
Started	Mar 26 12:37:36 PM PDT 24
Finished	Mar 26 12:37:37 PM PDT 24
Peak memory	200264 kb
Host	smart-61560ffc-c295-4ba5-9711-cc8e0a92925c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487050092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.1487050092
Directory	/workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_status.4095744683
Short name	T521
Test name
Test status
Simulation time	44854417 ps
CPU time	0.8 seconds
Started	Mar 26 12:37:30 PM PDT 24
Finished	Mar 26 12:37:31 PM PDT 24
Peak memory	199520 kb
Host	smart-1ee4aec4-d1e5-43dd-8467-91d262661661
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095744683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.4095744683
Directory	/workspace/6.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/6.clkmgr_div_intersig_mubi.4076953514
Short name	T291
Test name
Test status
Simulation time	17370706 ps
CPU time	0.75 seconds
Started	Mar 26 12:37:36 PM PDT 24
Finished	Mar 26 12:37:37 PM PDT 24
Peak memory	200572 kb
Host	smart-09bffb53-053a-45af-b4f6-2e51a13f3327
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076953514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.4076953514
Directory	/workspace/6.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_extclk.2052380624
Short name	T738
Test name
Test status
Simulation time	20202175 ps
CPU time	0.79 seconds
Started	Mar 26 12:37:34 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	200572 kb
Host	smart-385b8fad-4101-477c-8cd8-70de35ab47a5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052380624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.2052380624
Directory	/workspace/6.clkmgr_extclk/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency.2132199302
Short name	T263
Test name
Test status
Simulation time	561028023 ps
CPU time	4.82 seconds
Started	Mar 26 12:37:39 PM PDT 24
Finished	Mar 26 12:37:46 PM PDT 24
Peak memory	200632 kb
Host	smart-132d4091-f13e-41ca-8079-13ef3b762f9e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132199302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.2132199302
Directory	/workspace/6.clkmgr_frequency/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency_timeout.1209101048
Short name	T639
Test name
Test status
Simulation time	282396474 ps
CPU time	1.81 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:37:37 PM PDT 24
Peak memory	200660 kb
Host	smart-6fac4fa4-701b-45f1-91ac-ce9ba8d3963c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209101048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti meout.1209101048
Directory	/workspace/6.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/6.clkmgr_idle_intersig_mubi.1425456841
Short name	T386
Test name
Test status
Simulation time	186630437 ps
CPU time	1.59 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:37:37 PM PDT 24
Peak memory	200540 kb
Host	smart-c9268b4c-ce28-40bf-8e66-666163462577
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425456841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.1425456841
Directory	/workspace/6.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.700552060
Short name	T700
Test name
Test status
Simulation time	14478180 ps
CPU time	0.75 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	200572 kb
Host	smart-539bc721-1c49-477b-b759-079149d78698
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700552060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.clkmgr_lc_clk_byp_req_intersig_mubi.700552060
Directory	/workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.1779872211
Short name	T301
Test name
Test status
Simulation time	12830124 ps
CPU time	0.74 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	200492 kb
Host	smart-161cf7c2-09dc-43ad-a74c-ebf7b2fe515b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779872211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 6.clkmgr_lc_ctrl_intersig_mubi.1779872211
Directory	/workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_peri.2771668143
Short name	T212
Test name
Test status
Simulation time	17449150 ps
CPU time	0.75 seconds
Started	Mar 26 12:37:30 PM PDT 24
Finished	Mar 26 12:37:31 PM PDT 24
Peak memory	200552 kb
Host	smart-cee98295-356b-4988-aa9f-ef723be3b124
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771668143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.2771668143
Directory	/workspace/6.clkmgr_peri/latest

Test location	/workspace/coverage/default/6.clkmgr_regwen.3856803923
Short name	T599
Test name
Test status
Simulation time	475455352 ps
CPU time	2.47 seconds
Started	Mar 26 12:37:34 PM PDT 24
Finished	Mar 26 12:37:37 PM PDT 24
Peak memory	200580 kb
Host	smart-81b4dacd-98d7-4942-b373-dacb14b081e7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856803923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.3856803923
Directory	/workspace/6.clkmgr_regwen/latest

Test location	/workspace/coverage/default/6.clkmgr_smoke.1260517729
Short name	T757
Test name
Test status
Simulation time	137102885 ps
CPU time	1.16 seconds
Started	Mar 26 12:37:49 PM PDT 24
Finished	Mar 26 12:37:50 PM PDT 24
Peak memory	200596 kb
Host	smart-290956cb-8814-4f79-96ca-cb3de9f98ace
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260517729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.1260517729
Directory	/workspace/6.clkmgr_smoke/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all.2698028620
Short name	T115
Test name
Test status
Simulation time	6681907779 ps
CPU time	49.58 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:38:25 PM PDT 24
Peak memory	200724 kb
Host	smart-38a221a9-a073-4797-b74b-8871bc68fdc1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698028620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.2698028620
Directory	/workspace/6.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.2027530138
Short name	T176
Test name
Test status
Simulation time	14643748049 ps
CPU time	223.9 seconds
Started	Mar 26 12:37:36 PM PDT 24
Finished	Mar 26 12:41:20 PM PDT 24
Peak memory	208880 kb
Host	smart-c1a89904-7f9c-4b07-bee7-e96c71fe67ca
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2027530138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.2027530138
Directory	/workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.clkmgr_trans.3814761509
Short name	T668
Test name
Test status
Simulation time	15550607 ps
CPU time	0.77 seconds
Started	Mar 26 12:37:35 PM PDT 24
Finished	Mar 26 12:37:36 PM PDT 24
Peak memory	200536 kb
Host	smart-ba66f38f-8c12-4547-b373-582322499436
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814761509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.3814761509
Directory	/workspace/6.clkmgr_trans/latest

Test location	/workspace/coverage/default/7.clkmgr_alert_test.1729214407
Short name	T664
Test name
Test status
Simulation time	14422124 ps
CPU time	0.78 seconds
Started	Mar 26 12:37:44 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200664 kb
Host	smart-a6116a60-8ca0-418d-afdd-66be100b84ea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729214407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm gr_alert_test.1729214407
Directory	/workspace/7.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.2350132069
Short name	T629
Test name
Test status
Simulation time	19499676 ps
CPU time	0.79 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200560 kb
Host	smart-518b3b29-1c09-4142-b9aa-b18877db92dc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350132069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.2350132069
Directory	/workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_status.1771838883
Short name	T340
Test name
Test status
Simulation time	16965782 ps
CPU time	0.74 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200580 kb
Host	smart-6f2634fb-511e-4074-8a21-a7f8c311ac27
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771838883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.1771838883
Directory	/workspace/7.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/7.clkmgr_div_intersig_mubi.1942362588
Short name	T676
Test name
Test status
Simulation time	78857607 ps
CPU time	1.06 seconds
Started	Mar 26 12:37:44 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200620 kb
Host	smart-3d5690bf-d3e0-4abc-8a44-def09f94ff12
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942362588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.1942362588
Directory	/workspace/7.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_extclk.3600998774
Short name	T406
Test name
Test status
Simulation time	48640164 ps
CPU time	0.92 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200560 kb
Host	smart-cb6bd25d-a22b-41f7-a9b4-c92eed292fcd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600998774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.3600998774
Directory	/workspace/7.clkmgr_extclk/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency.120268493
Short name	T14
Test name
Test status
Simulation time	2146309504 ps
CPU time	9.56 seconds
Started	Mar 26 12:37:44 PM PDT 24
Finished	Mar 26 12:37:53 PM PDT 24
Peak memory	200676 kb
Host	smart-bd3d8961-88bd-4478-9a6c-760b8fbf9734
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120268493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.120268493
Directory	/workspace/7.clkmgr_frequency/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency_timeout.2598375866
Short name	T854
Test name
Test status
Simulation time	943390810 ps
CPU time	3.66 seconds
Started	Mar 26 12:37:45 PM PDT 24
Finished	Mar 26 12:37:48 PM PDT 24
Peak memory	200612 kb
Host	smart-fe1cfedd-ef59-4382-b60f-644dc017d3b8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598375866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti meout.2598375866
Directory	/workspace/7.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/7.clkmgr_idle_intersig_mubi.3432551261
Short name	T853
Test name
Test status
Simulation time	19883273 ps
CPU time	0.75 seconds
Started	Mar 26 12:37:44 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200436 kb
Host	smart-c1b8ea21-1faf-40a9-973c-7b93c88c1b56
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432551261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.3432551261
Directory	/workspace/7.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.2371458658
Short name	T571
Test name
Test status
Simulation time	125420219 ps
CPU time	1.08 seconds
Started	Mar 26 12:37:43 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200640 kb
Host	smart-f9ef0735-1df5-4d72-9478-8c3733840e61
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371458658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 7.clkmgr_lc_clk_byp_req_intersig_mubi.2371458658
Directory	/workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.675655533
Short name	T395
Test name
Test status
Simulation time	64152346 ps
CPU time	1.01 seconds
Started	Mar 26 12:37:49 PM PDT 24
Finished	Mar 26 12:37:50 PM PDT 24
Peak memory	200560 kb
Host	smart-7a7cc9aa-e027-44a8-a969-4aabbb9cfa89
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675655533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.clkmgr_lc_ctrl_intersig_mubi.675655533
Directory	/workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_peri.2924092963
Short name	T184
Test name
Test status
Simulation time	16744889 ps
CPU time	0.81 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200624 kb
Host	smart-d46ccf7b-f6dd-43c7-acca-00e4eb92bb94
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924092963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.2924092963
Directory	/workspace/7.clkmgr_peri/latest

Test location	/workspace/coverage/default/7.clkmgr_regwen.1558687070
Short name	T827
Test name
Test status
Simulation time	243246004 ps
CPU time	2.01 seconds
Started	Mar 26 12:37:45 PM PDT 24
Finished	Mar 26 12:37:47 PM PDT 24
Peak memory	200548 kb
Host	smart-664083f6-8538-4d6e-885e-d7b3d0ad8584
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558687070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.1558687070
Directory	/workspace/7.clkmgr_regwen/latest

Test location	/workspace/coverage/default/7.clkmgr_smoke.3695741133
Short name	T689
Test name
Test status
Simulation time	17852228 ps
CPU time	0.81 seconds
Started	Mar 26 12:37:32 PM PDT 24
Finished	Mar 26 12:37:33 PM PDT 24
Peak memory	200560 kb
Host	smart-044914d8-a10c-4df1-ab01-d62677606eed
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695741133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.3695741133
Directory	/workspace/7.clkmgr_smoke/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all.918263972
Short name	T475
Test name
Test status
Simulation time	2083670503 ps
CPU time	14.77 seconds
Started	Mar 26 12:37:41 PM PDT 24
Finished	Mar 26 12:37:57 PM PDT 24
Peak memory	200736 kb
Host	smart-001a8977-e946-48d4-998a-bc4c8e7fb48a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918263972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.918263972
Directory	/workspace/7.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.2024146869
Short name	T860
Test name
Test status
Simulation time	136107416241 ps
CPU time	960.58 seconds
Started	Mar 26 12:37:48 PM PDT 24
Finished	Mar 26 12:53:49 PM PDT 24
Peak memory	209144 kb
Host	smart-c87471bf-7543-4979-9637-d70ef764201c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2024146869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.2024146869
Directory	/workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.clkmgr_trans.2724197193
Short name	T272
Test name
Test status
Simulation time	56723307 ps
CPU time	1.02 seconds
Started	Mar 26 12:37:44 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200860 kb
Host	smart-09f3c9f7-3fca-44e6-af4b-0b1e1173bb5f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724197193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.2724197193
Directory	/workspace/7.clkmgr_trans/latest

Test location	/workspace/coverage/default/8.clkmgr_alert_test.4288751783
Short name	T498
Test name
Test status
Simulation time	32141330 ps
CPU time	0.83 seconds
Started	Mar 26 12:37:43 PM PDT 24
Finished	Mar 26 12:37:44 PM PDT 24
Peak memory	200692 kb
Host	smart-29b853b8-1763-4ed7-8f6d-626113dcd53c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288751783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm gr_alert_test.4288751783
Directory	/workspace/8.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.3271003029
Short name	T778
Test name
Test status
Simulation time	14400178 ps
CPU time	0.72 seconds
Started	Mar 26 12:37:41 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200548 kb
Host	smart-69298967-6ba5-4645-aa5c-640908893c42
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271003029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.3271003029
Directory	/workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_status.3629575393
Short name	T45
Test name
Test status
Simulation time	41836703 ps
CPU time	0.77 seconds
Started	Mar 26 12:37:45 PM PDT 24
Finished	Mar 26 12:37:46 PM PDT 24
Peak memory	199496 kb
Host	smart-505e50a4-9b93-415d-b154-883fb5a7535b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629575393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.3629575393
Directory	/workspace/8.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/8.clkmgr_div_intersig_mubi.1865929579
Short name	T477
Test name
Test status
Simulation time	14637490 ps
CPU time	0.77 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200588 kb
Host	smart-93d8fb73-7435-48b7-bd8a-f7cfe05585da
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865929579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.1865929579
Directory	/workspace/8.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_extclk.1867445738
Short name	T605
Test name
Test status
Simulation time	19345049 ps
CPU time	0.84 seconds
Started	Mar 26 12:37:44 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200624 kb
Host	smart-0faac1c5-65cd-4b7d-ba2f-5cc831f28239
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867445738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.1867445738
Directory	/workspace/8.clkmgr_extclk/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency.700967198
Short name	T636
Test name
Test status
Simulation time	1880776957 ps
CPU time	14.3 seconds
Started	Mar 26 12:37:41 PM PDT 24
Finished	Mar 26 12:37:56 PM PDT 24
Peak memory	200700 kb
Host	smart-92b80c67-ac16-4891-850c-9d08d65ff897
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700967198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.700967198
Directory	/workspace/8.clkmgr_frequency/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency_timeout.989357983
Short name	T287
Test name
Test status
Simulation time	739820678 ps
CPU time	5.79 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:48 PM PDT 24
Peak memory	200664 kb
Host	smart-de141df0-e8fe-4027-b528-403718cea66d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989357983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_tim eout.989357983
Directory	/workspace/8.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/8.clkmgr_idle_intersig_mubi.2869443201
Short name	T821
Test name
Test status
Simulation time	578598928 ps
CPU time	2.56 seconds
Started	Mar 26 12:37:45 PM PDT 24
Finished	Mar 26 12:37:48 PM PDT 24
Peak memory	200496 kb
Host	smart-766c12c2-e100-4e5b-aada-c0e94814a85e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869443201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.2869443201
Directory	/workspace/8.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.2810102182
Short name	T284
Test name
Test status
Simulation time	21613626 ps
CPU time	0.79 seconds
Started	Mar 26 12:37:40 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200616 kb
Host	smart-fd7b8bcc-8f44-49d2-accd-bc330bab9a34
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810102182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_clk_byp_req_intersig_mubi.2810102182
Directory	/workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.2699027271
Short name	T311
Test name
Test status
Simulation time	17807347 ps
CPU time	0.77 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200556 kb
Host	smart-a64f353b-1e0d-419d-8424-6322fc41ced2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699027271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_ctrl_intersig_mubi.2699027271
Directory	/workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_peri.3707107670
Short name	T322
Test name
Test status
Simulation time	60268164 ps
CPU time	0.88 seconds
Started	Mar 26 12:37:43 PM PDT 24
Finished	Mar 26 12:37:44 PM PDT 24
Peak memory	200536 kb
Host	smart-93834966-e81a-4a6a-bed6-77510a06404e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707107670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.3707107670
Directory	/workspace/8.clkmgr_peri/latest

Test location	/workspace/coverage/default/8.clkmgr_regwen.892266818
Short name	T685
Test name
Test status
Simulation time	224102130 ps
CPU time	1.8 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:44 PM PDT 24
Peak memory	200528 kb
Host	smart-6b649115-139e-4a3e-bc30-785806a4b5e9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892266818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.892266818
Directory	/workspace/8.clkmgr_regwen/latest

Test location	/workspace/coverage/default/8.clkmgr_smoke.3652475951
Short name	T313
Test name
Test status
Simulation time	20531483 ps
CPU time	0.86 seconds
Started	Mar 26 12:37:43 PM PDT 24
Finished	Mar 26 12:37:44 PM PDT 24
Peak memory	200548 kb
Host	smart-a04fb965-43f6-4dfe-a8aa-01c4bef70e8c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652475951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.3652475951
Directory	/workspace/8.clkmgr_smoke/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all.1696097831
Short name	T371
Test name
Test status
Simulation time	7532033906 ps
CPU time	30.87 seconds
Started	Mar 26 12:37:46 PM PDT 24
Finished	Mar 26 12:38:17 PM PDT 24
Peak memory	200876 kb
Host	smart-5587ce14-b392-406d-a693-db56a5280270
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696097831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.1696097831
Directory	/workspace/8.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.1585781634
Short name	T368
Test name
Test status
Simulation time	6796865602 ps
CPU time	56.4 seconds
Started	Mar 26 12:37:47 PM PDT 24
Finished	Mar 26 12:38:44 PM PDT 24
Peak memory	217356 kb
Host	smart-4560d153-ef91-4ec1-8eda-269c20b2e654
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1585781634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.1585781634
Directory	/workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.clkmgr_trans.2350712775
Short name	T772
Test name
Test status
Simulation time	18212958 ps
CPU time	0.79 seconds
Started	Mar 26 12:37:43 PM PDT 24
Finished	Mar 26 12:37:44 PM PDT 24
Peak memory	200572 kb
Host	smart-a816de09-869f-4385-8bd5-6388e02e6a87
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350712775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.2350712775
Directory	/workspace/8.clkmgr_trans/latest

Test location	/workspace/coverage/default/9.clkmgr_alert_test.1152751949
Short name	T447
Test name
Test status
Simulation time	71507418 ps
CPU time	0.91 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200636 kb
Host	smart-61dab236-388f-4523-91df-15204c535ada
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152751949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm gr_alert_test.1152751949
Directory	/workspace/9.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.270546610
Short name	T389
Test name
Test status
Simulation time	63386206 ps
CPU time	0.89 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200560 kb
Host	smart-36927403-4257-4186-bca2-52b50eb63367
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270546610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.270546610
Directory	/workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_status.145739753
Short name	T168
Test name
Test status
Simulation time	14038990 ps
CPU time	0.68 seconds
Started	Mar 26 12:37:45 PM PDT 24
Finished	Mar 26 12:37:46 PM PDT 24
Peak memory	199576 kb
Host	smart-6081f3ff-06ec-4851-945e-6cde6f12c30e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145739753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.145739753
Directory	/workspace/9.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/9.clkmgr_div_intersig_mubi.3591532460
Short name	T54
Test name
Test status
Simulation time	31477805 ps
CPU time	0.86 seconds
Started	Mar 26 12:37:44 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200616 kb
Host	smart-2654f52e-82be-4298-aaa1-63a64a82a654
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591532460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.3591532460
Directory	/workspace/9.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_extclk.2456626767
Short name	T572
Test name
Test status
Simulation time	18745493 ps
CPU time	0.8 seconds
Started	Mar 26 12:37:45 PM PDT 24
Finished	Mar 26 12:37:47 PM PDT 24
Peak memory	200588 kb
Host	smart-e3a6b5f9-c4a9-4cd3-94cb-ea46fbf8b49c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456626767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.2456626767
Directory	/workspace/9.clkmgr_extclk/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency.2888331193
Short name	T513
Test name
Test status
Simulation time	596911246 ps
CPU time	3 seconds
Started	Mar 26 12:37:44 PM PDT 24
Finished	Mar 26 12:37:47 PM PDT 24
Peak memory	200544 kb
Host	smart-3423a6f0-d0b7-4bff-8619-2281cdb48d38
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888331193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.2888331193
Directory	/workspace/9.clkmgr_frequency/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency_timeout.37706627
Short name	T223
Test name
Test status
Simulation time	2054895966 ps
CPU time	14.32 seconds
Started	Mar 26 12:37:41 PM PDT 24
Finished	Mar 26 12:37:56 PM PDT 24
Peak memory	200720 kb
Host	smart-413062f8-7399-4837-bbeb-29d38ab3743d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37706627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_time out.37706627
Directory	/workspace/9.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/9.clkmgr_idle_intersig_mubi.1299657449
Short name	T398
Test name
Test status
Simulation time	146637107 ps
CPU time	1.3 seconds
Started	Mar 26 12:37:43 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200556 kb
Host	smart-56e6a1f7-e567-40a8-a25d-9002ce194ac0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299657449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.1299657449
Directory	/workspace/9.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.1006356230
Short name	T722
Test name
Test status
Simulation time	51482198 ps
CPU time	0.88 seconds
Started	Mar 26 12:37:44 PM PDT 24
Finished	Mar 26 12:37:45 PM PDT 24
Peak memory	200584 kb
Host	smart-dc2fe887-ee89-400e-b0aa-a0c434b02862
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006356230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.clkmgr_lc_clk_byp_req_intersig_mubi.1006356230
Directory	/workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.3119288424
Short name	T506
Test name
Test status
Simulation time	19174480 ps
CPU time	0.81 seconds
Started	Mar 26 12:37:41 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200556 kb
Host	smart-7551e64e-ad8b-483b-ad6d-54e9957af39d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119288424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.clkmgr_lc_ctrl_intersig_mubi.3119288424
Directory	/workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_peri.608856831
Short name	T583
Test name
Test status
Simulation time	34984021 ps
CPU time	0.78 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200584 kb
Host	smart-6f5176b6-81f5-40f9-88f0-96e2793861f1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608856831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.608856831
Directory	/workspace/9.clkmgr_peri/latest

Test location	/workspace/coverage/default/9.clkmgr_regwen.1217468822
Short name	T97
Test name
Test status
Simulation time	1129698426 ps
CPU time	6.24 seconds
Started	Mar 26 12:37:56 PM PDT 24
Finished	Mar 26 12:38:02 PM PDT 24
Peak memory	200600 kb
Host	smart-4230d40e-254f-47c8-97a7-2e1fdaccd653
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217468822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1217468822
Directory	/workspace/9.clkmgr_regwen/latest

Test location	/workspace/coverage/default/9.clkmgr_smoke.1647349815
Short name	T699
Test name
Test status
Simulation time	85459190 ps
CPU time	1.05 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200656 kb
Host	smart-f93e42ab-ac88-4739-bbc9-5e9fa45d133a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647349815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.1647349815
Directory	/workspace/9.clkmgr_smoke/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.3243981442
Short name	T159
Test name
Test status
Simulation time	38272163016 ps
CPU time	563.49 seconds
Started	Mar 26 12:37:43 PM PDT 24
Finished	Mar 26 12:47:07 PM PDT 24
Peak memory	217392 kb
Host	smart-e3903b2e-aab5-440b-b171-1371ba44e9f3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3243981442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.3243981442
Directory	/workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.clkmgr_trans.566886282
Short name	T186
Test name
Test status
Simulation time	21321955 ps
CPU time	0.84 seconds
Started	Mar 26 12:37:42 PM PDT 24
Finished	Mar 26 12:37:43 PM PDT 24
Peak memory	200584 kb
Host	smart-a222bb83-3bcb-4156-80da-30a63f217009
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566886282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.566886282
Directory	/workspace/9.clkmgr_trans/latest

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