Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	625411	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3527062

1

T7

26

T8

21

T9

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1015113	1			T7	24		T8	23		T9	9
values[0x0]	1442208	1			T7	15		T8	17		T9	7
values[0x1]	1695152	1			T7	8		T8	10		T9	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	346611	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3805862

1

T7

31

T8

22

T9

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16625	1			T4	1		T1	10		T5	8
valid_sources[0x01]	16406	1			T9	28		T4	4		T1	11
valid_sources[0x02]	17179	1			T4	1		T1	10		T5	2
valid_sources[0x03]	16515	1			T23	1		T24	1		T26	1
valid_sources[0x04]	16860	1			T7	1		T26	1		T4	2
valid_sources[0x05]	16944	1			T4	5		T1	5		T3	155
valid_sources[0x06]	15238	1			T4	5		T1	5		T5	1
valid_sources[0x07]	14976	1			T4	3		T1	11		T5	1
valid_sources[0x08]	16510	1			T4	7		T1	11		T3	223
valid_sources[0x09]	15139	1			T23	2		T26	1		T4	5
valid_sources[0x0a]	19164	1			T4	3		T1	15		T3	279
valid_sources[0x0b]	17339	1			T7	2		T23	1		T4	3
valid_sources[0x0c]	16289	1			T26	1		T4	4		T1	7
valid_sources[0x0d]	16250	1			T4	5		T1	2		T3	339
valid_sources[0x0e]	16021	1			T26	2		T4	1		T1	8
valid_sources[0x0f]	16885	1			T4	4		T1	9		T5	2
valid_sources[0x10]	17143	1			T23	2		T26	1		T4	6
valid_sources[0x11]	18922	1			T25	40		T4	6		T1	9
valid_sources[0x12]	15861	1			T4	9		T1	6		T5	1
valid_sources[0x13]	15402	1			T23	1		T24	2		T26	1
valid_sources[0x14]	16212	1			T4	10		T1	6		T5	1
valid_sources[0x15]	14998	1			T4	7		T1	11		T18	1
valid_sources[0x16]	16522	1			T7	1		T4	3		T1	5
valid_sources[0x17]	15030	1			T24	2		T4	7		T1	6
valid_sources[0x18]	16371	1			T23	1		T26	1		T4	3
valid_sources[0x19]	16957	1			T23	1		T4	3		T1	7
valid_sources[0x1a]	17364	1			T7	1		T27	1		T4	4
valid_sources[0x1b]	16409	1			T7	1		T4	1		T1	5
valid_sources[0x1c]	15359	1			T26	1		T4	6		T1	5
valid_sources[0x1d]	14774	1			T26	1		T4	3		T1	15
valid_sources[0x1e]	15259	1			T7	1		T23	3		T4	1
valid_sources[0x1f]	17033	1			T26	1		T4	3		T1	6
valid_sources[0x20]	16809	1			T4	2		T1	3		T5	1
valid_sources[0x21]	16318	1			T26	1		T4	5		T1	12
valid_sources[0x22]	16752	1			T4	2		T1	7		T5	1
valid_sources[0x23]	15029	1			T7	1		T4	2		T1	8
valid_sources[0x24]	16197	1			T26	1		T4	2		T1	11
valid_sources[0x25]	14456	1			T4	3		T1	2		T5	1
valid_sources[0x26]	16287	1			T4	2		T1	6		T18	1
valid_sources[0x27]	16732	1			T7	1		T27	6		T4	4
valid_sources[0x28]	16740	1			T26	1		T1	4		T3	678
valid_sources[0x29]	16497	1			T7	1		T23	2		T4	3
valid_sources[0x2a]	16725	1			T7	1		T4	2		T1	11
valid_sources[0x2b]	16767	1			T7	1		T27	4		T4	3
valid_sources[0x2c]	15999	1			T7	1		T4	2		T1	14
valid_sources[0x2d]	16394	1			T7	1		T4	3		T1	4
valid_sources[0x2e]	16042	1			T26	1		T4	5		T1	9
valid_sources[0x2f]	16286	1			T26	2		T4	4		T1	6
valid_sources[0x30]	15323	1			T26	1		T4	5		T1	9
valid_sources[0x31]	15040	1			T4	3		T1	5		T3	287
valid_sources[0x32]	16135	1			T7	2		T4	9		T1	4
valid_sources[0x33]	17274	1			T4	4		T1	8		T18	1
valid_sources[0x34]	16673	1			T4	4		T1	10		T5	2
valid_sources[0x35]	15546	1			T4	3		T1	5		T5	1
valid_sources[0x36]	15566	1			T26	1		T4	1		T1	15
valid_sources[0x37]	14925	1			T4	3		T1	11		T3	113
valid_sources[0x38]	16884	1			T4	5		T1	8		T3	463
valid_sources[0x39]	15745	1			T23	1		T4	4		T1	9
valid_sources[0x3a]	16126	1			T4	5		T1	9		T5	1
valid_sources[0x3b]	15914	1			T4	4		T1	5		T5	2
valid_sources[0x3c]	16425	1			T4	4		T1	7		T3	155
valid_sources[0x3d]	16448	1			T7	1		T6	331		T4	3
valid_sources[0x3e]	15430	1			T4	2		T1	9		T5	1
valid_sources[0x3f]	16034	1			T4	7		T1	4		T3	250
valid_sources[0x40]	15904	1			T4	2		T1	10		T20	2
valid_sources[0x41]	14396	1			T4	7		T1	7		T20	1
valid_sources[0x42]	16948	1			T4	3		T1	8		T5	1
valid_sources[0x43]	17161	1			T4	5		T1	5		T18	2
valid_sources[0x44]	16285	1			T4	5		T1	7		T18	1
valid_sources[0x45]	15718	1			T4	2		T1	9		T5	4
valid_sources[0x46]	15757	1			T27	1		T4	4		T1	8
valid_sources[0x47]	16777	1			T4	3		T1	9		T18	1
valid_sources[0x48]	15526	1			T4	3		T1	7		T5	5
valid_sources[0x49]	15923	1			T7	1		T26	1		T4	2
valid_sources[0x4a]	15162	1			T4	4		T1	5		T3	200
valid_sources[0x4b]	15227	1			T7	1		T26	1		T4	5
valid_sources[0x4c]	15847	1			T4	5		T1	10		T3	295
valid_sources[0x4d]	15613	1			T4	4		T1	6		T5	2
valid_sources[0x4e]	15383	1			T4	2		T1	5		T3	241
valid_sources[0x4f]	15258	1			T7	1		T4	3		T1	9
valid_sources[0x50]	15993	1			T1	7		T3	443		T74	1
valid_sources[0x51]	15688	1			T7	1		T26	1		T4	2
valid_sources[0x52]	15715	1			T7	1		T4	2		T1	7
valid_sources[0x53]	15390	1			T4	2		T1	9		T5	3
valid_sources[0x54]	14805	1			T23	2		T26	1		T4	5
valid_sources[0x55]	17206	1			T26	1		T4	2		T1	5
valid_sources[0x56]	16091	1			T4	2		T1	11		T5	1
valid_sources[0x57]	14782	1			T4	4		T1	4		T5	1
valid_sources[0x58]	17158	1			T4	1		T1	6		T3	111
valid_sources[0x59]	17796	1			T23	1		T4	4		T1	11
valid_sources[0x5a]	17146	1			T4	4		T1	10		T5	2
valid_sources[0x5b]	16169	1			T7	1		T8	7		T4	8
valid_sources[0x5c]	16465	1			T4	6		T1	8		T3	313
valid_sources[0x5d]	17775	1			T26	1		T4	5		T1	4
valid_sources[0x5e]	15648	1			T26	1		T4	3		T1	8
valid_sources[0x5f]	15910	1			T4	3		T1	8		T5	2
valid_sources[0x60]	16888	1			T7	1		T26	1		T1	4
valid_sources[0x61]	16582	1			T23	1		T4	5		T1	6
valid_sources[0x62]	15607	1			T4	3		T1	13		T5	1
valid_sources[0x63]	16410	1			T4	7		T1	6		T5	2
valid_sources[0x64]	16823	1			T7	1		T26	1		T4	7
valid_sources[0x65]	16064	1			T4	2		T1	8		T18	1
valid_sources[0x66]	15323	1			T4	1		T1	7		T18	1
valid_sources[0x67]	17160	1			T26	1		T4	2		T1	10
valid_sources[0x68]	19238	1			T26	2		T4	2		T1	5
valid_sources[0x69]	15669	1			T4	3		T1	10		T5	1
valid_sources[0x6a]	14598	1			T7	1		T26	2		T4	4
valid_sources[0x6b]	15894	1			T7	2		T4	4		T1	10
valid_sources[0x6c]	15979	1			T7	1		T26	1		T4	5
valid_sources[0x6d]	17791	1			T4	2		T1	4		T5	1
valid_sources[0x6e]	16059	1			T4	4		T1	10		T3	169
valid_sources[0x6f]	16548	1			T23	1		T4	6		T1	10
valid_sources[0x70]	16605	1			T24	2		T4	3		T1	5
valid_sources[0x71]	15949	1			T4	2		T1	12		T18	1
valid_sources[0x72]	15663	1			T4	2		T1	9		T3	177
valid_sources[0x73]	15651	1			T7	1		T4	3		T1	10
valid_sources[0x74]	15924	1			T26	2		T4	9		T1	5
valid_sources[0x75]	14736	1			T27	2		T4	3		T1	6
valid_sources[0x76]	17520	1			T4	8		T1	7		T3	662
valid_sources[0x77]	15426	1			T4	2		T1	13		T3	537
valid_sources[0x78]	15123	1			T26	1		T4	3		T1	9
valid_sources[0x79]	17042	1			T4	2		T1	15		T3	618
valid_sources[0x7a]	16386	1			T4	1		T1	12		T18	1
valid_sources[0x7b]	16087	1			T23	1		T4	4		T1	7
valid_sources[0x7c]	15493	1			T26	1		T4	2		T1	6
valid_sources[0x7d]	14936	1			T4	1		T1	6		T3	325
valid_sources[0x7e]	17466	1			T23	1		T4	8		T1	4
valid_sources[0x7f]	18656	1			T4	3		T1	9		T3	25
valid_sources[0x80]	16739	1			T4	4		T1	5		T5	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

886827

1

T7

13

T8

11

T9

3

values[0x0]

all_enables

biggest_size

1344684

1

T7

9

T8

9

T9

2

values[0x1]

all_enables

biggest_size

1295551

1

T7

4

T8

1

T9

3