Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	843623190	83988	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	843623190	83988	0	0
T1	2433860	440	0	0
T2	303285	129	0	0
T3	1509485	663	0	0
T5	54875	0	0	0
T11	1496440	332	0	0
T12	0	123	0	0
T13	0	44	0	0
T14	0	1230	0	0
T15	0	236	0	0
T16	0	1042	0	0
T17	0	2838	0	0
T18	15945	0	0	0
T19	7740	0	0	0
T20	3500	0	0	0
T21	6250	0	0	0
T22	6940	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168724638	12164	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168724638	12164	0	0
T1	486772	62	0	0
T2	60657	20	0	0
T3	301897	107	0	0
T5	10975	0	0	0
T11	299288	54	0	0
T12	0	19	0	0
T13	0	7	0	0
T14	0	179	0	0
T15	0	43	0	0
T16	0	165	0	0
T17	0	416	0	0
T18	3189	0	0	0
T19	1548	0	0	0
T20	700	0	0	0
T21	1250	0	0	0
T22	1388	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168724638	16888	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168724638	16888	0	0
T1	486772	86	0	0
T2	60657	26	0	0
T3	301897	135	0	0
T5	10975	0	0	0
T11	299288	67	0	0
T12	0	25	0	0
T13	0	9	0	0
T14	0	247	0	0
T15	0	46	0	0
T16	0	212	0	0
T17	0	570	0	0
T18	3189	0	0	0
T19	1548	0	0	0
T20	700	0	0	0
T21	1250	0	0	0
T22	1388	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168724638	25943	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168724638	25943	0	0
T1	486772	143	0	0
T2	60657	37	0	0
T3	301897	182	0	0
T5	10975	0	0	0
T11	299288	91	0	0
T12	0	36	0	0
T13	0	12	0	0
T14	0	380	0	0
T15	0	58	0	0
T16	0	288	0	0
T17	0	871	0	0
T18	3189	0	0	0
T19	1548	0	0	0
T20	700	0	0	0
T21	1250	0	0	0
T22	1388	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168724638	12100	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168724638	12100	0	0
T1	486772	62	0	0
T2	60657	20	0	0
T3	301897	104	0	0
T5	10975	0	0	0
T11	299288	52	0	0
T12	0	18	0	0
T13	0	7	0	0
T14	0	176	0	0
T15	0	43	0	0
T16	0	166	0	0
T17	0	411	0	0
T18	3189	0	0	0
T19	1548	0	0	0
T20	700	0	0	0
T21	1250	0	0	0
T22	1388	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168724638	16893	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168724638	16893	0	0
T1	486772	87	0	0
T2	60657	26	0	0
T3	301897	135	0	0
T5	10975	0	0	0
T11	299288	68	0	0
T12	0	25	0	0
T13	0	9	0	0
T14	0	248	0	0
T15	0	46	0	0
T16	0	211	0	0
T17	0	570	0	0
T18	3189	0	0	0
T19	1548	0	0	0
T20	700	0	0	0
T21	1250	0	0	0
T22	1388	0	0	0