Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T7,T4,T1

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	168724638	166090042	0	0
AllClkBypReqTrue_A	168724638	138733	0	0
IoClkBypReqFalse_A	168724638	166010941	0	2415
IoClkBypReqTrue_A	168724638	213284	0	0
LcClkBypAckFalse_A	168724638	166102668	0	0
LcClkBypAckTrue_A	168724638	126107	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168724638	166090042	0	0
T4	15444	3514	0	0
T6	179722	179511	0	0
T7	5122	1244	0	0
T8	1679	1473	0	0
T9	1452	1298	0	0
T23	1341	1292	0	0
T24	1083	955	0	0
T25	2344	2011	0	0
T26	2775	2272	0	0
T27	1596	1509	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168724638	138733	0	0
T1	0	325	0	0
T3	0	5064	0	0
T4	15444	0	0	0
T6	179722	0	0	0
T8	1679	174	0	0
T9	1452	140	0	0
T11	0	265	0	0
T19	0	107	0	0
T23	1341	0	0	0
T24	1083	121	0	0
T25	2344	211	0	0
T26	2775	435	0	0
T27	1596	0	0	0
T36	784	0	0	0
T71	0	147	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168724638	166010941	0	2415
T4	15444	3472	0	3
T6	179722	179509	0	3
T7	5122	1240	0	3
T8	1679	1341	0	3
T9	1452	1220	0	3
T23	1341	1290	0	3
T24	1083	934	0	3
T25	2344	1963	0	3
T26	2775	2029	0	3
T27	1596	1507	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168724638	213284	0	0
T1	0	594	0	0
T3	0	6877	0	0
T4	15444	0	0	0
T6	179722	0	0	0
T8	1679	304	0	0
T9	1452	216	0	0
T11	0	377	0	0
T19	0	74	0	0
T23	1341	0	0	0
T24	1083	140	0	0
T25	2344	257	0	0
T26	2775	676	0	0
T27	1596	0	0	0
T36	784	0	0	0
T72	0	481	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168724638	166102668	0	0
T4	15444	3514	0	0
T6	179722	179511	0	0
T7	5122	1244	0	0
T8	1679	1536	0	0
T9	1452	1320	0	0
T23	1341	1292	0	0
T24	1083	966	0	0
T25	2344	2082	0	0
T26	2775	2321	0	0
T27	1596	1509	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168724638	126107	0	0
T1	0	434	0	0
T3	0	4315	0	0
T4	15444	0	0	0
T6	179722	0	0	0
T8	1679	111	0	0
T9	1452	118	0	0
T11	0	242	0	0
T19	0	67	0	0
T23	1341	0	0	0
T24	1083	110	0	0
T25	2344	140	0	0
T26	2775	386	0	0
T27	1596	0	0	0
T36	784	0	0	0
T72	0	223	0	0