Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1779998584	15915	0	0
TransStop_A	1779998584	8092	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1779998584	15915	0	0
T1	2926236	46	0	0
T2	1010980	0	0	0
T3	499564	224	0	0
T5	175612	0	0	0
T11	529764	55	0	0
T18	60752	0	0	0
T19	12392	0	0	0
T20	31108	0	0	0
T21	18512	4	0	0
T22	9916	0	0	0
T73	0	21	0	0
T96	0	4	0	0
T105	0	5	0	0
T106	0	30	0	0
T107	0	30	0	0
T108	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1779998584	8092	0	0
T1	2926236	28	0	0
T2	1010980	0	0	0
T3	499564	121	0	0
T5	175612	0	0	0
T11	529764	37	0	0
T18	60752	0	0	0
T19	12392	0	0	0
T20	31108	0	0	0
T21	18512	4	0	0
T22	9916	0	0	0
T73	0	8	0	0
T96	0	4	0	0
T105	0	5	0	0
T106	0	16	0	0
T107	0	19	0	0
T108	0	4	0	0
T109	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	444999646	3955	0	0
TransStop_A	444999646	1999	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999646	3955	0	0
T1	731559	8	0	0
T2	252745	0	0	0
T3	124891	66	0	0
T5	43903	0	0	0
T11	132441	10	0	0
T18	15188	0	0	0
T19	3098	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2479	0	0	0
T73	0	7	0	0
T96	0	1	0	0
T105	0	2	0	0
T106	0	6	0	0
T107	0	7	0	0
T108	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999646	1999	0	0
T1	731559	6	0	0
T2	252745	0	0	0
T3	124891	30	0	0
T5	43903	0	0	0
T11	132441	8	0	0
T18	15188	0	0	0
T19	3098	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2479	0	0	0
T73	0	3	0	0
T96	0	1	0	0
T105	0	2	0	0
T106	0	3	0	0
T107	0	5	0	0
T108	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	444999646	4046	0	0
TransStop_A	444999646	2074	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999646	4046	0	0
T1	731559	11	0	0
T2	252745	0	0	0
T3	124891	55	0	0
T5	43903	0	0	0
T11	132441	18	0	0
T18	15188	0	0	0
T19	3098	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2479	0	0	0
T73	0	6	0	0
T96	0	1	0	0
T105	0	1	0	0
T106	0	8	0	0
T107	0	10	0	0
T108	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999646	2074	0	0
T1	731559	8	0	0
T2	252745	0	0	0
T3	124891	30	0	0
T5	43903	0	0	0
T11	132441	12	0	0
T18	15188	0	0	0
T19	3098	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2479	0	0	0
T73	0	2	0	0
T96	0	1	0	0
T105	0	1	0	0
T106	0	5	0	0
T107	0	6	0	0
T108	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	444999646	4015	0	0
TransStop_A	444999646	2058	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999646	4015	0	0
T1	731559	11	0	0
T2	252745	0	0	0
T3	124891	53	0	0
T5	43903	0	0	0
T11	132441	13	0	0
T18	15188	0	0	0
T19	3098	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2479	0	0	0
T73	0	5	0	0
T96	0	1	0	0
T105	0	1	0	0
T106	0	7	0	0
T107	0	6	0	0
T108	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999646	2058	0	0
T1	731559	5	0	0
T2	252745	0	0	0
T3	124891	33	0	0
T5	43903	0	0	0
T11	132441	8	0	0
T18	15188	0	0	0
T19	3098	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2479	0	0	0
T73	0	3	0	0
T96	0	1	0	0
T105	0	1	0	0
T106	0	4	0	0
T107	0	5	0	0
T108	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	444999646	3899	0	0
TransStop_A	444999646	1961	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999646	3899	0	0
T1	731559	16	0	0
T2	252745	0	0	0
T3	124891	50	0	0
T5	43903	0	0	0
T11	132441	14	0	0
T18	15188	0	0	0
T19	3098	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2479	0	0	0
T73	0	3	0	0
T96	0	1	0	0
T105	0	1	0	0
T106	0	9	0	0
T107	0	7	0	0
T108	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999646	1961	0	0
T1	731559	9	0	0
T2	252745	0	0	0
T3	124891	28	0	0
T5	43903	0	0	0
T11	132441	9	0	0
T18	15188	0	0	0
T19	3098	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2479	0	0	0
T96	0	1	0	0
T105	0	1	0	0
T106	0	4	0	0
T107	0	3	0	0
T108	0	1	0	0
T109	0	1	0	0