Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1000200	0	0
SrcPulseCheck_M	2147483647	995933	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1000200
T1	1920167	2126
T2	0	566
T3	0	6865
T4	437264	201
T5	104647	50
T6	717466	762
T7	12424	10
T8	8893	0
T9	20884	0
T11	0	4708
T12	0	452
T13	0	256
T14	0	8525
T15	0	308
T18	0	10
T23	11069	0
T24	84430	0
T25	11427	0
T26	25481	0
T27	9045	0
T29	0	212
T36	10569	0
T54	7078	1
T57	9186	1
T58	6306	2
T59	6477	1
T60	9627	2
T62	5724	0
T63	5435	2
T115	5801	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	995933
T1	11300	2126
T2	0	566
T3	0	6865
T4	74020	201
T5	404	50
T6	427618	762
T7	13895	10
T8	6965	0
T9	12620	0
T11	0	4708
T12	0	452
T13	0	256
T14	0	8525
T15	0	308
T18	0	10
T23	4710	0
T24	19909	0
T25	6600	0
T26	10416	0
T27	4740	0
T29	0	212
T36	1156	0
T54	2862	1
T57	3994	1
T58	2619	2
T59	5811	1
T60	4016	2
T62	10781	0
T63	2250	2
T115	2590	3

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	418184762	26969	0	0
SrcPulseCheck_M	169618918	26969	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	418184762	26969
T1	0	122
T2	0	42
T3	0	342
T4	134781	40
T5	0	10
T6	133953	30
T7	9835	2
T8	6451	0
T9	17440	0
T11	0	216
T18	0	2
T23	2577	0
T24	20816	0
T25	2344	0
T26	5550	0
T27	1989	0
T29	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169618918	26969
T1	0	122
T2	0	42
T3	0	342
T4	15444	40
T5	0	10
T6	179722	30
T7	5122	2
T8	1679	0
T9	1452	0
T11	0	216
T18	0	2
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	418184762	32652	0	0
SrcPulseCheck_M	169618918	32674	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	418184762	32652
T1	0	122
T2	0	42
T3	0	351
T4	134781	80
T5	0	20
T6	133953	30
T7	9835	4
T8	6451	0
T9	17440	0
T11	0	216
T18	0	4
T23	2577	0
T24	20816	0
T25	2344	0
T26	5550	0
T27	1989	0
T29	0	80

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169618918	32674
T1	0	122
T2	0	42
T3	0	351
T4	15444	80
T5	0	20
T6	179722	30
T7	5122	4
T8	1679	0
T9	1452	0
T11	0	216
T18	0	4
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	80

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	32648	0	0
SrcPulseCheck_M	418184762	32656	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	32648
T1	0	122
T2	0	42
T3	0	351
T4	15444	80
T5	0	20
T6	179722	30
T7	5122	4
T8	1679	0
T9	1452	0
T11	0	216
T18	0	4
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	80

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	418184762	32656
T1	0	122
T2	0	42
T3	0	351
T4	134781	80
T5	0	20
T6	133953	30
T7	9835	4
T8	6451	0
T9	17440	0
T11	0	216
T18	0	4
T23	2577	0
T24	20816	0
T25	2344	0
T26	5550	0
T27	1989	0
T29	0	80

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	208240366	26969	0	0
SrcPulseCheck_M	169618918	26969	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	208240366	26969
T1	0	122
T2	0	42
T3	0	342
T4	41896	40
T5	0	10
T6	66930	30
T7	3651	2
T8	3607	0
T9	9716	0
T11	0	216
T18	0	2
T23	1276	0
T24	11671	0
T25	1228	0
T26	3250	0
T27	968	0
T29	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169618918	26969
T1	0	122
T2	0	42
T3	0	342
T4	15444	40
T5	0	10
T6	179722	30
T7	5122	2
T8	1679	0
T9	1452	0
T11	0	216
T18	0	2
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	208240366	32625	0	0
SrcPulseCheck_M	169618918	32652	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	208240366	32625
T1	0	122
T2	0	42
T3	0	351
T4	41896	80
T5	0	20
T6	66930	30
T7	3651	4
T8	3607	0
T9	9716	0
T11	0	216
T18	0	4
T23	1276	0
T24	11671	0
T25	1228	0
T26	3250	0
T27	968	0
T29	0	80

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169618918	32652
T1	0	122
T2	0	42
T3	0	351
T4	15444	80
T5	0	20
T6	179722	30
T7	5122	4
T8	1679	0
T9	1452	0
T11	0	216
T18	0	4
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	80

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	32622	0	0
SrcPulseCheck_M	208240366	32631	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	32622
T1	0	122
T2	0	42
T3	0	351
T4	15444	80
T5	0	20
T6	179722	30
T7	5122	4
T8	1679	0
T9	1452	0
T11	0	216
T18	0	4
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	80

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	208240366	32631
T1	0	122
T2	0	42
T3	0	351
T4	41896	80
T5	0	20
T6	66930	30
T7	3651	4
T8	3607	0
T9	9716	0
T11	0	216
T18	0	4
T23	1276	0
T24	11671	0
T25	1228	0
T26	3250	0
T27	968	0
T29	0	80

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	104119562	26969	0	0
SrcPulseCheck_M	169618918	26969	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	104119562	26969
T1	0	122
T2	0	42
T3	0	342
T4	20950	40
T5	0	10
T6	33465	30
T7	1825	2
T8	1803	0
T9	4858	0
T11	0	216
T18	0	2
T23	638	0
T24	5834	0
T25	613	0
T26	1625	0
T27	484	0
T29	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169618918	26969
T1	0	122
T2	0	42
T3	0	342
T4	15444	40
T5	0	10
T6	179722	30
T7	5122	2
T8	1679	0
T9	1452	0
T11	0	216
T18	0	2
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	40

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	104119562	32686	0	0
SrcPulseCheck_M	169618918	32737	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	104119562	32686
T1	0	122
T2	0	42
T3	0	351
T4	20950	80
T5	0	20
T6	33465	30
T7	1825	4
T8	1803	0
T9	4858	0
T11	0	216
T18	0	4
T23	638	0
T24	5834	0
T25	613	0
T26	1625	0
T27	484	0
T29	0	80

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169618918	32737
T1	0	122
T2	0	42
T3	0	351
T4	15444	80
T5	0	20
T6	179722	30
T7	5122	4
T8	1679	0
T9	1452	0
T11	0	216
T18	0	4
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	80

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	32682	0	0
SrcPulseCheck_M	104119562	32691	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	32682
T1	0	122
T2	0	42
T3	0	351
T4	15444	80
T5	0	20
T6	179722	30
T7	5122	4
T8	1679	0
T9	1452	0
T11	0	216
T18	0	4
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	80

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	104119562	32691
T1	0	122
T2	0	42
T3	0	351
T4	20950	80
T5	0	20
T6	33465	30
T7	1825	4
T8	1803	0
T9	4858	0
T11	0	216
T18	0	4
T23	638	0
T24	5834	0
T25	613	0
T26	1625	0
T27	484	0
T29	0	80

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	447454333	26969	0	0
SrcPulseCheck_M	169618918	26969	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	447454333	26969
T1	0	122
T2	0	42
T3	0	342
T4	140401	40
T5	0	10
T6	169536	30
T7	10245	2
T8	6720	0
T9	18167	0
T11	0	216
T18	0	2
T23	2685	0
T24	21684	0
T25	2442	0
T26	5781	0
T27	2072	0
T29	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169618918	26969
T1	0	122
T2	0	42
T3	0	342
T4	15444	40
T5	0	10
T6	179722	30
T7	5122	2
T8	1679	0
T9	1452	0
T11	0	216
T18	0	2
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	40

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	447454333	32807	0	0
SrcPulseCheck_M	169618918	32823	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	447454333	32807
T1	0	122
T2	0	42
T3	0	351
T4	140401	80
T5	0	20
T6	169536	30
T7	10245	4
T8	6720	0
T9	18167	0
T11	0	216
T18	0	4
T23	2685	0
T24	21684	0
T25	2442	0
T26	5781	0
T27	2072	0
T29	0	80

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169618918	32823
T1	0	122
T2	0	42
T3	0	351
T4	15444	80
T5	0	20
T6	179722	30
T7	5122	4
T8	1679	0
T9	1452	0
T11	0	216
T18	0	4
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	80

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	32799	0	0
SrcPulseCheck_M	447454333	32810	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	32799
T1	0	122
T2	0	42
T3	0	351
T4	15444	80
T5	0	20
T6	179722	30
T7	5122	4
T8	1679	0
T9	1452	0
T11	0	216
T18	0	4
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	80

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	447454333	32810
T1	0	122
T2	0	42
T3	0	351
T4	140401	80
T5	0	20
T6	169536	30
T7	10245	4
T8	6720	0
T9	18167	0
T11	0	216
T18	0	4
T23	2685	0
T24	21684	0
T25	2442	0
T26	5781	0
T27	2072	0
T29	0	80

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	214575857	26620	0	0
SrcPulseCheck_M	169618918	26969	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	214575857	26620
T1	0	122
T2	0	42
T3	0	342
T4	67393	34
T5	0	5
T6	72739	30
T7	4918	2
T8	3225	0
T9	8720	0
T11	0	216
T18	0	1
T23	1289	0
T24	10409	0
T25	1172	0
T26	2775	0
T27	994	0
T29	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169618918	26969
T1	0	122
T2	0	42
T3	0	342
T4	15444	40
T5	0	10
T6	179722	30
T7	5122	2
T8	1679	0
T9	1452	0
T11	0	216
T18	0	2
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	40

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	214575857	32510	0	0
SrcPulseCheck_M	169618918	32675	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	214575857	32510
T1	0	122
T2	0	42
T3	0	351
T4	67393	80
T5	0	20
T6	72739	30
T7	4918	4
T8	3225	0
T9	8720	0
T11	0	216
T18	0	4
T23	1289	0
T24	10409	0
T25	1172	0
T26	2775	0
T27	994	0
T29	0	80

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	169618918	32675
T1	0	122
T2	0	42
T3	0	351
T4	15444	80
T5	0	20
T6	179722	30
T7	5122	4
T8	1679	0
T9	1452	0
T11	0	216
T18	0	4
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	80

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T6,T4
1	0	Covered	T7,T6,T4
1	1	Covered	T7,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	32402	0	0
SrcPulseCheck_M	214575857	32545	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	32402
T1	0	122
T2	0	42
T3	0	351
T4	15444	60
T5	0	15
T6	179722	30
T7	5122	4
T8	1679	0
T9	1452	0
T11	0	216
T18	0	3
T23	1341	0
T24	1083	0
T25	2344	0
T26	2775	0
T27	1596	0
T29	0	78

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	214575857	32545
T1	0	122
T2	0	42
T3	0	351
T4	67393	80
T5	0	20
T6	72739	30
T7	4918	4
T8	3225	0
T9	8720	0
T11	0	216
T18	0	4
T23	1289	0
T24	10409	0
T25	1172	0
T26	2775	0
T27	994	0
T29	0	80

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T58,T55
1	0	Covered	T54,T58,T55
1	1	Covered	T116,T65,T117

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T58,T55
1	0	Covered	T116,T65,T117
1	1	Covered	T54,T58,T55

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	34	0	0
SrcPulseCheck_M	418184762	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	34
T54	7078	1
T55	10410	2
T56	10590	2
T58	6306	1
T59	6477	1
T60	9627	1
T62	5724	3
T63	5435	1
T116	16052	2
T118	16999	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	418184762	34
T54	7004	1
T55	10302	2
T56	10165	2
T58	6177	1
T59	12955	1
T60	9627	1
T62	22895	3
T63	5217	1
T116	16052	2
T118	17177	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T56
1	0	Covered	T54,T55,T56
1	1	Covered	T62,T65,T119

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T56
1	0	Covered	T62,T65,T119
1	1	Covered	T54,T55,T56

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	35	0	0
SrcPulseCheck_M	418184762	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	35
T54	7078	1
T55	10410	2
T56	10590	2
T59	6477	1
T60	9627	3
T62	5724	2
T64	7576	1
T115	5801	1
T116	16052	1
T118	16999	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	418184762	35
T54	7004	1
T55	10302	2
T56	10165	2
T59	12955	1
T60	9627	3
T62	22895	2
T64	29091	1
T115	6053	1
T116	16052	1
T118	17177	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T57,T58
1	0	Covered	T54,T57,T58
1	1	Covered	T58,T60,T63

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T57,T58
1	0	Covered	T58,T60,T63
1	1	Covered	T54,T57,T58

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	35	0	0
SrcPulseCheck_M	208240366	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	35
T54	7078	1
T57	9186	1
T58	6306	2
T59	6477	1
T60	9627	2
T61	14648	1
T62	5724	1
T63	5435	2
T115	5801	3
T120	5128	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	208240366	35
T54	2862	1
T57	3994	1
T58	2619	2
T59	5811	1
T60	4016	2
T61	6267	1
T62	10781	1
T63	2250	2
T115	2590	3
T120	9760	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T58,T55
1	0	Covered	T54,T58,T55
1	1	Covered	T63,T115,T121

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T58,T55
1	0	Covered	T63,T115,T121
1	1	Covered	T54,T58,T55

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	33	0	0
SrcPulseCheck_M	208240366	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	33
T54	7078	1
T55	10410	1
T58	6306	1
T59	6477	1
T60	9627	2
T61	14648	2
T62	5724	1
T63	5435	2
T115	5801	2
T120	5128	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	208240366	33
T54	2862	1
T55	4287	1
T58	2619	1
T59	5811	1
T60	4016	2
T61	6267	2
T62	10781	1
T63	2250	2
T115	2590	2
T120	9760	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T55,T56,T59
1	0	Covered	T55,T56,T59
1	1	Covered	T120,T119,T122

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T55,T56,T59
1	0	Covered	T120,T119,T122
1	1	Covered	T55,T56,T59

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	36	0	0
SrcPulseCheck_M	104119562	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	36
T55	10410	1
T56	10590	1
T59	6477	1
T60	9627	2
T62	5724	2
T63	5435	1
T115	5801	1
T118	16999	1
T120	5128	2
T123	4546	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	104119562	36
T55	2143	1
T56	2234	1
T59	2906	1
T60	2008	2
T62	5390	2
T63	1125	1
T115	1295	1
T118	3961	1
T120	4879	2
T123	2177	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T56,T59,T60
1	0	Covered	T56,T59,T60
1	1	Covered	T60,T120,T118

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T56,T59,T60
1	0	Covered	T60,T120,T118
1	1	Covered	T56,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	36	0	0
SrcPulseCheck_M	104119562	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	36
T56	10590	2
T59	6477	1
T60	9627	2
T62	5724	2
T63	5435	1
T64	7576	2
T115	5801	2
T118	16999	2
T120	5128	2
T123	4546	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	104119562	36
T56	2234	2
T59	2906	1
T60	2008	2
T62	5390	2
T63	1125	1
T64	6925	2
T115	1295	2
T118	3961	2
T120	4879	2
T123	2177	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T57,T58,T55
1	0	Covered	T57,T58,T55
1	1	Covered	T56,T61

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T57,T58,T55
1	0	Covered	T56,T61
1	1	Covered	T57,T58,T55

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	33	0	0
SrcPulseCheck_M	447454333	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	33
T55	10410	1
T56	10590	3
T57	9186	1
T58	6306	1
T59	6477	2
T60	9627	1
T61	14648	3
T62	5724	1
T63	5435	1
T115	5801	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	447454333	33
T55	10732	1
T56	10590	3
T57	9186	1
T58	6435	1
T59	13496	2
T60	10030	1
T61	14648	3
T62	23850	1
T63	5435	1
T115	6305	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T58,T56,T59
1	0	Covered	T58,T56,T59
1	1	Covered	T56,T61

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T58,T56,T59
1	0	Covered	T56,T61
1	1	Covered	T58,T56,T59

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	31	0	0
SrcPulseCheck_M	447454333	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	31
T56	10590	3
T58	6306	1
T59	6477	1
T60	9627	2
T61	14648	4
T62	5724	1
T64	7576	1
T65	6041	1
T115	5801	1
T119	11775	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	447454333	31
T56	10590	3
T58	6435	1
T59	13496	1
T60	10030	2
T61	14648	4
T62	23850	1
T64	30305	1
T65	6165	1
T115	6305	1
T119	11775	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T57,T58,T56
1	0	Covered	T57,T58,T56
1	1	Covered	T56,T59,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T57,T58,T56
1	0	Covered	T56,T59,T64
1	1	Covered	T57,T58,T56

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	26	0	0
SrcPulseCheck_M	214575857	26	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	26
T56	10590	2
T57	9186	1
T58	6306	1
T59	6477	2
T64	7576	3
T65	6041	3
T116	16052	1
T118	16999	1
T119	11775	1
T121	8023	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	214575857	26
T56	5083	2
T57	4409	1
T58	3089	1
T59	6477	2
T64	14546	3
T65	2959	3
T116	8027	1
T118	8589	1
T119	5652	1
T121	7860	2

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T57,T58
1	0	Covered	T54,T57,T58
1	1	Covered	T57,T56,T59

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T57,T58
1	0	Covered	T57,T56,T59
1	1	Covered	T54,T57,T58

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	169618918	34	0	0
SrcPulseCheck_M	214575857	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	169618918	34
T54	7078	1
T56	10590	3
T57	9186	2
T58	6306	1
T59	6477	2
T61	14648	1
T64	7576	3
T116	16052	1
T118	16999	1
T124	6476	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	214575857	34
T54	3502	1
T56	5083	3
T57	4409	2
T58	3089	1
T59	6477	2
T61	7031	1
T64	14546	3
T116	8027	1
T118	8589	1
T124	6218	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	415827939	100096	0	0
SrcPulseCheck_M	14168540	98656	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	415827939	100096
T1	679234	428
T2	0	110
T3	0	1441
T4	134781	1
T5	42144	0
T6	133953	153
T11	0	928
T12	0	113
T13	0	64
T14	0	1999
T23	2577	0
T24	20816	0
T25	2344	0
T26	5550	0
T27	1989	0
T29	0	6
T36	3832	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14168540	98656
T1	2813	428
T2	0	110
T3	0	1441
T4	309	1
T5	101	0
T6	296	153
T11	0	928
T12	0	113
T13	0	64
T14	0	1999
T23	188	0
T24	1518	0
T25	171	0
T26	404	0
T27	145	0
T29	0	6
T36	289	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	207108743	99723	0	0
SrcPulseCheck_M	14168540	98284	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	207108743	99723
T1	339586	428
T2	0	110
T3	0	1429
T4	41896	0
T5	12400	0
T6	66930	153
T11	0	928
T12	0	113
T13	0	64
T14	0	1987
T15	0	104
T23	1276	0
T24	11671	0
T25	1228	0
T26	3250	0
T27	968	0
T29	0	1
T36	1897	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14168540	98284
T1	2813	428
T2	0	110
T3	0	1429
T4	309	0
T5	101	0
T6	296	153
T11	0	928
T12	0	113
T13	0	64
T14	0	1987
T15	0	104
T23	188	0
T24	1518	0
T25	171	0
T26	404	0
T27	145	0
T29	0	1
T36	289	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	103553759	98810	0	0
SrcPulseCheck_M	14168540	97393	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	103553759	98810
T1	169789	428
T2	0	110
T3	0	1363
T4	20950	0
T5	6201	0
T6	33465	153
T11	0	928
T12	0	113
T13	0	64
T14	0	1979
T15	0	103
T23	638	0
T24	5834	0
T25	613	0
T26	1625	0
T27	484	0
T29	0	4
T36	948	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14168540	97393
T1	2813	428
T2	0	110
T3	0	1363
T4	309	0
T5	101	0
T6	296	153
T11	0	928
T12	0	113
T13	0	64
T14	0	1979
T15	0	103
T23	188	0
T24	1518	0
T25	171	0
T26	404	0
T27	145	0
T29	0	4
T36	289	0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	444999203	121183	0	0
SrcPulseCheck_M	15027486	120857	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	444999203	121183
T1	731558	476
T2	0	110
T3	0	1588
T4	140401	0
T5	43902	0
T6	169536	213
T11	0	1276
T12	0	113
T13	0	64
T14	0	2560
T15	0	101
T23	2685	0
T24	21684	0
T25	2442	0
T26	5781	0
T27	2072	0
T29	0	1
T36	3892	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	15027486	120857
T1	2861	476
T2	0	110
T3	0	1588
T4	309	0
T5	101	0
T6	356	213
T11	0	1276
T12	0	113
T13	0	64
T14	0	2560
T15	0	101
T23	188	0
T24	1518	0
T25	171	0
T26	404	0
T27	145	0
T29	0	1
T36	289	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	213397424	119126	0	0
SrcPulseCheck_M	15014271	118671	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	213397424	119126
T1	339633	428
T2	0	108
T3	0	1660
T4	67393	0
T5	21073	0
T6	72739	177
T11	0	1204
T12	0	113
T13	0	64
T14	0	2501
T15	0	96
T16	0	1475
T23	1289	0
T24	10409	0
T25	1172	0
T26	2775	0
T27	994	0
T36	1871	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	15014271	118671
T1	2813	428
T2	0	108
T3	0	1660
T4	309	0
T5	101	0
T6	320	177
T11	0	1204
T12	0	113
T13	0	64
T14	0	2501
T15	0	96
T16	0	1475
T23	188	0
T24	1518	0
T25	171	0
T26	404	0
T27	145	0
T36	289	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb