Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	169618918	5145870	0	0
clk_enables_rd_A	169618918	45306	0	0
clk_hints_rd_A	169618918	39764	0	0
extclk_ctrl_rd_A	169618918	51005	0	0
extclk_ctrl_regwen_rd_A	169618918	38763	0	0
jitter_enable_rd_A	169618918	58475	0	0
jitter_regwen_rd_A	169618918	43363	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169618918	5145870	0	0
T3	301897	94790	0	0
T11	299288	0	0	0
T14	0	89847	0	0
T16	0	77088	0	0
T17	0	153204	0	0
T28	0	73478	0	0
T29	13842	0	0	0
T37	1239	0	0	0
T38	1648	0	0	0
T39	746	0	0	0
T66	0	50379	0	0
T67	0	97261	0	0
T68	0	108187	0	0
T69	0	116515	0	0
T70	0	82411	0	0
T71	1909	0	0	0
T72	2649	0	0	0
T73	2629	0	0	0
T74	926	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169618918	45306	0	0
T3	301897	1822	0	0
T11	299288	0	0	0
T14	0	3453	0	0
T29	13842	0	0	0
T37	1239	0	0	0
T38	1648	0	0	0
T39	746	0	0	0
T71	1909	0	0	0
T72	2649	0	0	0
T73	2629	0	0	0
T74	926	0	0	0
T109	0	8	0	0
T125	0	6	0	0
T126	0	19	0	0
T127	0	5	0	0
T128	0	8	0	0
T129	0	1938	0	0
T130	0	6	0	0
T131	0	2	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169618918	39764	0	0
T3	301897	1604	0	0
T11	299288	0	0	0
T14	0	2906	0	0
T29	13842	0	0	0
T37	1239	0	0	0
T38	1648	0	0	0
T39	746	0	0	0
T71	1909	0	0	0
T72	2649	0	0	0
T73	2629	0	0	0
T74	926	0	0	0
T96	0	10	0	0
T109	0	1	0	0
T125	0	9	0	0
T126	0	17	0	0
T128	0	16	0	0
T129	0	1881	0	0
T130	0	1	0	0
T132	0	10	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169618918	51005	0	0
T3	0	2088	0	0
T4	15444	0	0	0
T6	179722	0	0	0
T7	5122	2	0	0
T8	1679	0	0	0
T9	1452	33	0	0
T14	0	3742	0	0
T19	0	18	0	0
T23	1341	0	0	0
T24	1083	0	0	0
T25	2344	0	0	0
T26	2775	71	0	0
T27	1596	0	0	0
T71	0	37	0	0
T75	0	65	0	0
T86	0	58	0	0
T133	0	9	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169618918	38763	0	0
T3	0	1793	0	0
T4	15444	0	0	0
T6	179722	0	0	0
T7	5122	3	0	0
T8	1679	0	0	0
T9	1452	0	0	0
T14	0	2770	0	0
T23	1341	0	0	0
T24	1083	0	0	0
T25	2344	0	0	0
T26	2775	0	0	0
T27	1596	0	0	0
T129	0	1863	0	0
T134	0	20	0	0
T135	0	17	0	0
T136	0	27	0	0
T137	0	56	0	0
T138	0	2875	0	0
T139	0	2288	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169618918	58475	0	0
T3	301897	2388	0	0
T11	299288	0	0	0
T14	0	5362	0	0
T29	13842	0	0	0
T37	1239	0	0	0
T38	1648	0	0	0
T39	746	0	0	0
T71	1909	0	0	0
T72	2649	0	0	0
T73	2629	0	0	0
T74	926	0	0	0
T96	0	71	0	0
T109	0	111	0	0
T125	0	118	0	0
T126	0	437	0	0
T127	0	191	0	0
T128	0	220	0	0
T129	0	2902	0	0
T140	0	55	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169618918	43363	0	0
T3	301897	1914	0	0
T11	299288	0	0	0
T14	0	3551	0	0
T29	13842	0	0	0
T37	1239	0	0	0
T38	1648	0	0	0
T39	746	0	0	0
T71	1909	0	0	0
T72	2649	0	0	0
T73	2629	0	0	0
T74	926	0	0	0
T129	0	2164	0	0
T138	0	3395	0	0
T139	0	2684	0	0
T141	0	2489	0	0
T142	0	1686	0	0
T143	0	3620	0	0
T144	0	3004	0	0
T145	0	1658	0	0