Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T36
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47482	0	0
CgEnOn_A	2147483647	38370	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47482	0	0
T1	5917535	8	0	0
T2	2062274	0	0	0
T3	2351691	0	0	0
T4	265020	63	0	0
T5	336559	0	0	0
T6	307087	3	0	0
T7	20229	6	0	0
T8	15086	3	0	0
T9	40734	3	0	0
T18	117764	0	0	0
T19	25434	0	0	0
T20	63342	0	0	0
T21	37615	0	0	0
T22	20138	0	0	0
T23	5780	46	0	0
T24	48730	3	0	0
T25	5357	3	0	0
T26	13200	3	0	0
T27	4435	3	0	0
T36	31925	12	0	0
T37	0	6	0	0
T38	0	18	0	0
T146	0	25	0	0
T147	0	30	0	0
T148	0	5	0	0
T149	0	10	0	0
T150	0	5	0	0
T151	0	25	0	0
T152	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38370	0	0
T1	7445777	77	0	0
T2	2062274	0	0	0
T3	2351691	538	0	0
T4	265020	0	0	0
T5	418377	0	0	0
T11	0	113	0	0
T18	146867	0	0	0
T19	25434	0	0	0
T20	63342	10	0	0
T21	37615	5	0	0
T22	20138	44	0	0
T23	5780	43	0	0
T24	48730	0	0	0
T25	5357	0	0	0
T26	13200	0	0	0
T27	4435	0	0	0
T36	40473	22	0	0
T37	0	11	0	0
T38	0	33	0	0
T39	0	3	0	0
T73	0	13	0	0
T96	0	2	0	0
T146	0	29	0	0
T147	0	35	0	0
T148	0	5	0	0
T149	0	13	0	0
T150	0	5	0	0
T151	0	31	0	0
T152	0	17	0	0
T153	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T36
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	207108743	138	0	0
CgEnOn_A	207108743	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207108743	138	0	0
T1	339586	0	0	0
T2	121273	0	0	0
T3	593513	0	0	0
T5	12400	0	0	0
T18	4823	0	0	0
T19	1551	0	0	0
T20	3686	0	0	0
T21	2161	0	0	0
T22	1157	0	0	0
T36	1897	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	5	0	0
T152	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207108743	138	0	0
T1	339586	0	0	0
T2	121273	0	0	0
T3	593513	0	0	0
T5	12400	0	0	0
T18	4823	0	0	0
T19	1551	0	0	0
T20	3686	0	0	0
T21	2161	0	0	0
T22	1157	0	0	0
T36	1897	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	5	0	0
T152	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T36
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103553759	138	0	0
CgEnOn_A	103553759	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103553759	138	0	0
T1	169789	0	0	0
T2	60637	0	0	0
T3	296755	0	0	0
T5	6201	0	0	0
T18	2411	0	0	0
T19	776	0	0	0
T20	1843	0	0	0
T21	1081	0	0	0
T22	578	0	0	0
T36	948	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	5	0	0
T152	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103553759	138	0	0
T1	169789	0	0	0
T2	60637	0	0	0
T3	296755	0	0	0
T5	6201	0	0	0
T18	2411	0	0	0
T19	776	0	0	0
T20	1843	0	0	0
T21	1081	0	0	0
T22	578	0	0	0
T36	948	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	5	0	0
T152	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T36
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	415827939	138	0	0
CgEnOn_A	415827939	133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415827939	138	0	0
T1	679234	0	0	0
T2	242626	0	0	0
T3	118567	0	0	0
T5	42144	0	0	0
T18	14580	0	0	0
T19	2973	0	0	0
T20	7465	0	0	0
T21	4443	0	0	0
T22	2379	0	0	0
T36	3832	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	5	0	0
T152	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415827939	133	0	0
T1	679234	0	0	0
T2	242626	0	0	0
T3	118567	0	0	0
T5	42144	0	0	0
T18	14580	0	0	0
T19	2973	0	0	0
T20	7465	0	0	0
T21	4443	0	0	0
T22	2379	0	0	0
T36	3832	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	5	0	0
T152	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T36
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	444999203	148	0	0
CgEnOn_A	444999203	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999203	148	0	0
T1	731558	0	0	0
T2	252744	0	0	0
T3	124891	0	0	0
T5	43902	0	0	0
T14	0	1	0	0
T18	15188	0	0	0
T19	3097	0	0	0
T20	7777	0	0	0
T21	4628	0	0	0
T22	2478	0	0	0
T36	3892	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T146	0	4	0	0
T147	0	5	0	0
T149	0	3	0	0
T151	0	6	0	0
T152	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999203	144	0	0
T1	731558	0	0	0
T2	252744	0	0	0
T3	124891	0	0	0
T5	43902	0	0	0
T18	15188	0	0	0
T19	3097	0	0	0
T20	7777	0	0	0
T21	4628	0	0	0
T22	2478	0	0	0
T36	3892	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T146	0	4	0	0
T147	0	5	0	0
T149	0	3	0	0
T151	0	6	0	0
T152	0	2	0	0
T153	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T36
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103553759	138	0	0
CgEnOn_A	103553759	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103553759	138	0	0
T1	169789	0	0	0
T2	60637	0	0	0
T3	296755	0	0	0
T5	6201	0	0	0
T18	2411	0	0	0
T19	776	0	0	0
T20	1843	0	0	0
T21	1081	0	0	0
T22	578	0	0	0
T36	948	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	5	0	0
T152	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103553759	138	0	0
T1	169789	0	0	0
T2	60637	0	0	0
T3	296755	0	0	0
T5	6201	0	0	0
T18	2411	0	0	0
T19	776	0	0	0
T20	1843	0	0	0
T21	1081	0	0	0
T22	578	0	0	0
T36	948	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	5	0	0
T152	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T36
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	444999203	148	0	0
CgEnOn_A	444999203	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999203	148	0	0
T1	731558	0	0	0
T2	252744	0	0	0
T3	124891	0	0	0
T5	43902	0	0	0
T14	0	1	0	0
T18	15188	0	0	0
T19	3097	0	0	0
T20	7777	0	0	0
T21	4628	0	0	0
T22	2478	0	0	0
T36	3892	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T146	0	4	0	0
T147	0	5	0	0
T149	0	3	0	0
T151	0	6	0	0
T152	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999203	144	0	0
T1	731558	0	0	0
T2	252744	0	0	0
T3	124891	0	0	0
T5	43902	0	0	0
T18	15188	0	0	0
T19	3097	0	0	0
T20	7777	0	0	0
T21	4628	0	0	0
T22	2478	0	0	0
T36	3892	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T146	0	4	0	0
T147	0	5	0	0
T149	0	3	0	0
T151	0	6	0	0
T152	0	2	0	0
T153	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T36
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103553759	138	0	0
CgEnOn_A	103553759	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103553759	138	0	0
T1	169789	0	0	0
T2	60637	0	0	0
T3	296755	0	0	0
T5	6201	0	0	0
T18	2411	0	0	0
T19	776	0	0	0
T20	1843	0	0	0
T21	1081	0	0	0
T22	578	0	0	0
T36	948	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	5	0	0
T152	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103553759	138	0	0
T1	169789	0	0	0
T2	60637	0	0	0
T3	296755	0	0	0
T5	6201	0	0	0
T18	2411	0	0	0
T19	776	0	0	0
T20	1843	0	0	0
T21	1081	0	0	0
T22	578	0	0	0
T36	948	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T146	0	5	0	0
T147	0	6	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	5	0	0
T152	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	207108743	7534	0	0
CgEnOn_A	207108743	5266	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207108743	7534	0	0
T4	41896	21	0	0
T6	66930	1	0	0
T7	3651	2	0	0
T8	3607	1	0	0
T9	9716	1	0	0
T23	1276	15	0	0
T24	11671	1	0	0
T25	1228	1	0	0
T26	3250	1	0	0
T27	968	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207108743	5266	0	0
T1	339586	20	0	0
T3	0	141	0	0
T4	41896	0	0	0
T5	12400	0	0	0
T11	0	29	0	0
T18	4823	0	0	0
T20	0	4	0	0
T21	0	1	0	0
T22	0	15	0	0
T23	1276	14	0	0
T24	11671	0	0	0
T25	1228	0	0	0
T26	3250	0	0	0
T27	968	0	0	0
T36	1897	2	0	0
T37	0	1	0	0
T38	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103553759	7478	0	0
CgEnOn_A	103553759	5210	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103553759	7478	0	0
T4	20950	21	0	0
T6	33465	1	0	0
T7	1825	2	0	0
T8	1803	1	0	0
T9	4858	1	0	0
T23	638	17	0	0
T24	5834	1	0	0
T25	613	1	0	0
T26	1625	1	0	0
T27	484	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103553759	5210	0	0
T1	169789	18	0	0
T3	0	139	0	0
T4	20950	0	0	0
T5	6201	0	0	0
T11	0	28	0	0
T18	2411	0	0	0
T20	0	3	0	0
T21	0	1	0	0
T22	0	14	0	0
T23	638	16	0	0
T24	5834	0	0	0
T25	613	0	0	0
T26	1625	0	0	0
T27	484	0	0	0
T36	948	2	0	0
T37	0	1	0	0
T38	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	415827939	7516	0	0
CgEnOn_A	415827939	5243	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415827939	7516	0	0
T4	134781	21	0	0
T6	133953	1	0	0
T7	9835	2	0	0
T8	6451	1	0	0
T9	17440	1	0	0
T23	2577	14	0	0
T24	20816	1	0	0
T25	2344	1	0	0
T26	5550	1	0	0
T27	1989	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415827939	5243	0	0
T1	679234	20	0	0
T3	0	137	0	0
T4	134781	0	0	0
T5	42144	0	0	0
T11	0	28	0	0
T18	14580	0	0	0
T20	0	3	0	0
T21	0	1	0	0
T22	0	15	0	0
T23	2577	13	0	0
T24	20816	0	0	0
T25	2344	0	0	0
T26	5550	0	0	0
T27	1989	0	0	0
T36	3832	2	0	0
T37	0	1	0	0
T38	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T39
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	213397424	7461	0	0
CgEnOn_A	213397424	5187	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213397424	7461	0	0
T4	67393	21	0	0
T6	72739	1	0	0
T7	4918	2	0	0
T8	3225	1	0	0
T9	8720	1	0	0
T23	1289	15	0	0
T24	10409	1	0	0
T25	1172	1	0	0
T26	2775	1	0	0
T27	994	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213397424	5187	0	0
T1	339633	19	0	0
T3	0	131	0	0
T4	67393	0	0	0
T5	21073	0	0	0
T11	0	27	0	0
T18	7289	0	0	0
T20	0	3	0	0
T21	0	1	0	0
T22	0	14	0	0
T23	1289	14	0	0
T24	10409	0	0	0
T25	1172	0	0	0
T26	2775	0	0	0
T27	994	0	0	0
T36	1871	2	0	0
T37	0	1	0	0
T39	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T36
1	0	Covered	T1,T21,T3
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	444999203	4103	0	0
CgEnOn_A	444999203	4099	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999203	4103	0	0
T1	731558	8	0	0
T2	252744	0	0	0
T3	124891	66	0	0
T5	43902	0	0	0
T11	0	10	0	0
T18	15188	0	0	0
T19	3097	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2478	0	0	0
T36	3892	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T73	0	7	0	0
T96	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999203	4099	0	0
T1	731558	8	0	0
T2	252744	0	0	0
T3	124891	66	0	0
T5	43902	0	0	0
T11	0	10	0	0
T18	15188	0	0	0
T19	3097	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2478	0	0	0
T36	3892	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T73	0	7	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T36
1	0	Covered	T1,T21,T3
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	444999203	4194	0	0
CgEnOn_A	444999203	4190	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999203	4194	0	0
T1	731558	11	0	0
T2	252744	0	0	0
T3	124891	55	0	0
T5	43902	0	0	0
T11	0	18	0	0
T18	15188	0	0	0
T19	3097	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2478	0	0	0
T36	3892	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T73	0	6	0	0
T96	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999203	4190	0	0
T1	731558	11	0	0
T2	252744	0	0	0
T3	124891	55	0	0
T5	43902	0	0	0
T11	0	18	0	0
T18	15188	0	0	0
T19	3097	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2478	0	0	0
T36	3892	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T73	0	6	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T36
1	0	Covered	T1,T21,T3
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	444999203	4163	0	0
CgEnOn_A	444999203	4159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999203	4163	0	0
T1	731558	11	0	0
T2	252744	0	0	0
T3	124891	53	0	0
T5	43902	0	0	0
T11	0	13	0	0
T18	15188	0	0	0
T19	3097	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2478	0	0	0
T36	3892	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T73	0	5	0	0
T96	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999203	4159	0	0
T1	731558	11	0	0
T2	252744	0	0	0
T3	124891	53	0	0
T5	43902	0	0	0
T11	0	13	0	0
T18	15188	0	0	0
T19	3097	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2478	0	0	0
T36	3892	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T73	0	5	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T36
1	0	Covered	T1,T21,T3
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	444999203	4047	0	0
CgEnOn_A	444999203	4043	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999203	4047	0	0
T1	731558	16	0	0
T2	252744	0	0	0
T3	124891	50	0	0
T5	43902	0	0	0
T11	0	14	0	0
T18	15188	0	0	0
T19	3097	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2478	0	0	0
T36	3892	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T73	0	3	0	0
T96	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444999203	4043	0	0
T1	731558	16	0	0
T2	252744	0	0	0
T3	124891	50	0	0
T5	43902	0	0	0
T11	0	14	0	0
T18	15188	0	0	0
T19	3097	0	0	0
T20	7777	0	0	0
T21	4628	1	0	0
T22	2478	0	0	0
T36	3892	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T73	0	3	0	0
T96	0	1	0	0