Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T23,T36,T1
0	1	Covered	T23,T1,T20
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T1,T20
1	0	Covered	T36,T37,T39
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	939889563	13470	0	0
GateOpen_A	939889563	13470	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939889563	13470	0	0
T1	1528244	45	0	0
T3	0	348	0	0
T4	265022	0	0	0
T5	81821	0	0	0
T11	0	72	0	0
T18	29105	0	0	0
T20	0	8	0	0
T21	0	4	0	0
T22	0	35	0	0
T23	5782	33	0	0
T24	48732	0	0	0
T25	5359	0	0	0
T26	13203	0	0	0
T27	4439	0	0	0
T36	8551	8	0	0
T37	0	4	0	0
T38	0	9	0	0
T39	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939889563	13470	0	0
T1	1528244	45	0	0
T3	0	348	0	0
T4	265022	0	0	0
T5	81821	0	0	0
T11	0	72	0	0
T18	29105	0	0	0
T20	0	8	0	0
T21	0	4	0	0
T22	0	35	0	0
T23	5782	33	0	0
T24	48732	0	0	0
T25	5359	0	0	0
T26	13203	0	0	0
T27	4439	0	0	0
T36	8551	8	0	0
T37	0	4	0	0
T38	0	9	0	0
T39	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T23,T36,T1
0	1	Covered	T23,T1,T20
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T1,T20
1	0	Covered	T36,T37,T38
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	103554189	3331	0	0
GateOpen_A	103554189	3331	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103554189	3331	0	0
T1	169790	10	0	0
T3	0	84	0	0
T4	20950	0	0	0
T5	6202	0	0	0
T11	0	20	0	0
T18	2412	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	0	8	0	0
T23	639	8	0	0
T24	5835	0	0	0
T25	613	0	0	0
T26	1626	0	0	0
T27	485	0	0	0
T36	949	2	0	0
T37	0	1	0	0
T38	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103554189	3331	0	0
T1	169790	10	0	0
T3	0	84	0	0
T4	20950	0	0	0
T5	6202	0	0	0
T11	0	20	0	0
T18	2412	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	0	8	0	0
T23	639	8	0	0
T24	5835	0	0	0
T25	613	0	0	0
T26	1626	0	0	0
T27	485	0	0	0
T36	949	2	0	0
T37	0	1	0	0
T38	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T23,T36,T1
0	1	Covered	T23,T1,T20
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T1,T20
1	0	Covered	T36,T37,T38
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	207109163	3385	0	0
GateOpen_A	207109163	3385	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207109163	3385	0	0
T1	339586	11	0	0
T3	0	92	0	0
T4	41897	0	0	0
T5	12401	0	0	0
T11	0	18	0	0
T18	4823	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	0	8	0	0
T23	1277	9	0	0
T24	11671	0	0	0
T25	1229	0	0	0
T26	3251	0	0	0
T27	969	0	0	0
T36	1897	2	0	0
T37	0	1	0	0
T38	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207109163	3385	0	0
T1	339586	11	0	0
T3	0	92	0	0
T4	41897	0	0	0
T5	12401	0	0	0
T11	0	18	0	0
T18	4823	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	0	8	0	0
T23	1277	9	0	0
T24	11671	0	0	0
T25	1229	0	0	0
T26	3251	0	0	0
T27	969	0	0	0
T36	1897	2	0	0
T37	0	1	0	0
T38	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T23,T36,T1
0	1	Covered	T23,T1,T20
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T1,T20
1	0	Covered	T36,T37,T38
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	415828381	3404	0	0
GateOpen_A	415828381	3404	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415828381	3404	0	0
T1	679235	12	0	0
T3	0	89	0	0
T4	134782	0	0	0
T5	42145	0	0	0
T11	0	15	0	0
T18	14580	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	0	9	0	0
T23	2577	8	0	0
T24	20817	0	0	0
T25	2345	0	0	0
T26	5551	0	0	0
T27	1990	0	0	0
T36	3833	2	0	0
T37	0	1	0	0
T38	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415828381	3404	0	0
T1	679235	12	0	0
T3	0	89	0	0
T4	134782	0	0	0
T5	42145	0	0	0
T11	0	15	0	0
T18	14580	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	0	9	0	0
T23	2577	8	0	0
T24	20817	0	0	0
T25	2345	0	0	0
T26	5551	0	0	0
T27	1990	0	0	0
T36	3833	2	0	0
T37	0	1	0	0
T38	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T23,T36,T1
0	1	Covered	T23,T1,T20
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T1,T20
1	0	Covered	T36,T37,T39
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	213397830	3350	0	0
GateOpen_A	213397830	3350	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213397830	3350	0	0
T1	339633	12	0	0
T3	0	83	0	0
T4	67393	0	0	0
T5	21073	0	0	0
T11	0	19	0	0
T18	7290	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	0	10	0	0
T23	1289	8	0	0
T24	10409	0	0	0
T25	1172	0	0	0
T26	2775	0	0	0
T27	995	0	0	0
T36	1872	2	0	0
T37	0	1	0	0
T39	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213397830	3350	0	0
T1	339633	12	0	0
T3	0	83	0	0
T4	67393	0	0	0
T5	21073	0	0	0
T11	0	19	0	0
T18	7290	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	0	10	0	0
T23	1289	8	0	0
T24	10409	0	0	0
T25	1172	0	0	0
T26	2775	0	0	0
T27	995	0	0	0
T36	1872	2	0	0
T37	0	1	0	0
T39	0	2	0	0