Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	596241	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3524110

1

T7

40

T8

14

T9

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1010628	1			T7	64		T8	11		T9	4
values[0x0]	1428495	1			T7	24		T8	14		T28	10
values[0x1]	1681228	1			T7	24		T8	9		T9	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	326102	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3794249

1

T7

52

T8

15

T9

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15171	1			T6	1		T1	151		T5	3
valid_sources[0x01]	16747	1			T7	3		T1	172		T5	3
valid_sources[0x02]	15163	1			T8	1		T40	1		T41	1
valid_sources[0x03]	15585	1			T7	1		T8	1		T30	1
valid_sources[0x04]	18784	1			T8	1		T31	10		T39	1
valid_sources[0x05]	16681	1			T7	1		T32	1		T1	160
valid_sources[0x06]	15976	1			T32	2		T1	187		T5	5
valid_sources[0x07]	18270	1			T7	2		T1	148		T5	3
valid_sources[0x08]	15926	1			T8	3		T1	183		T5	2
valid_sources[0x09]	16439	1			T29	1		T30	1		T6	3
valid_sources[0x0a]	17075	1			T8	1		T32	1		T1	177
valid_sources[0x0b]	15854	1			T1	192		T5	3		T2	522
valid_sources[0x0c]	14669	1			T1	195		T5	5		T26	2
valid_sources[0x0d]	15048	1			T6	2		T38	1		T1	196
valid_sources[0x0e]	16893	1			T6	2		T39	2		T42	3
valid_sources[0x0f]	15452	1			T1	183		T20	1		T5	11
valid_sources[0x10]	15197	1			T6	1		T1	148		T5	1
valid_sources[0x11]	14694	1			T32	1		T6	1		T1	162
valid_sources[0x12]	15066	1			T6	2		T39	1		T1	183
valid_sources[0x13]	15866	1			T1	170		T21	1		T5	3
valid_sources[0x14]	15485	1			T1	171		T5	4		T27	1
valid_sources[0x15]	16911	1			T7	1		T6	1		T1	162
valid_sources[0x16]	16171	1			T6	1		T1	148		T20	1
valid_sources[0x17]	15744	1			T32	1		T42	1		T1	160
valid_sources[0x18]	15906	1			T38	1		T40	3		T1	201
valid_sources[0x19]	14978	1			T1	171		T5	5		T26	1
valid_sources[0x1a]	15740	1			T38	1		T40	1		T1	168
valid_sources[0x1b]	15558	1			T7	3		T32	2		T6	1
valid_sources[0x1c]	15502	1			T6	1		T38	4		T1	173
valid_sources[0x1d]	16427	1			T29	1		T41	2		T1	188
valid_sources[0x1e]	16318	1			T31	3		T6	1		T1	129
valid_sources[0x1f]	15195	1			T39	1		T1	202		T5	4
valid_sources[0x20]	16721	1			T7	1		T8	1		T1	218
valid_sources[0x21]	15838	1			T30	1		T6	1		T1	236
valid_sources[0x22]	14560	1			T7	3		T6	1		T39	1
valid_sources[0x23]	16398	1			T1	218		T5	5		T2	460
valid_sources[0x24]	15062	1			T32	1		T42	1		T1	199
valid_sources[0x25]	15988	1			T8	1		T1	197		T20	1
valid_sources[0x26]	16788	1			T7	1		T42	1		T1	143
valid_sources[0x27]	15985	1			T32	6		T1	142		T5	2
valid_sources[0x28]	16089	1			T42	1		T1	183		T5	1
valid_sources[0x29]	15193	1			T8	1		T6	1		T1	145
valid_sources[0x2a]	14882	1			T38	1		T1	164		T21	1
valid_sources[0x2b]	17015	1			T6	1		T41	1		T1	173
valid_sources[0x2c]	16030	1			T6	1		T40	1		T42	1
valid_sources[0x2d]	16609	1			T7	1		T40	1		T1	176
valid_sources[0x2e]	15780	1			T1	133		T5	3		T2	284
valid_sources[0x2f]	16371	1			T29	1		T6	1		T42	1
valid_sources[0x30]	15883	1			T6	1		T1	175		T5	5
valid_sources[0x31]	16284	1			T29	6		T6	2		T1	119
valid_sources[0x32]	15312	1			T29	4		T41	1		T1	215
valid_sources[0x33]	17647	1			T1	154		T5	1		T53	1
valid_sources[0x34]	16462	1			T7	2		T1	173		T5	4
valid_sources[0x35]	16797	1			T42	1		T1	173		T5	5
valid_sources[0x36]	15697	1			T8	2		T1	217		T5	1
valid_sources[0x37]	17252	1			T1	204		T20	1		T5	2
valid_sources[0x38]	15723	1			T29	1		T6	1		T1	200
valid_sources[0x39]	16385	1			T6	2		T42	1		T1	154
valid_sources[0x3a]	15969	1			T41	1		T1	219		T5	3
valid_sources[0x3b]	16017	1			T1	139		T5	1		T2	103
valid_sources[0x3c]	15644	1			T6	1		T1	155		T5	3
valid_sources[0x3d]	15923	1			T7	2		T1	186		T20	1
valid_sources[0x3e]	16885	1			T30	2		T31	1		T6	1
valid_sources[0x3f]	16607	1			T1	198		T5	3		T26	1
valid_sources[0x40]	15355	1			T7	3		T41	1		T1	218
valid_sources[0x41]	15918	1			T1	125		T2	608		T59	1
valid_sources[0x42]	17552	1			T7	4		T32	1		T41	1
valid_sources[0x43]	15382	1			T1	212		T20	1		T21	1
valid_sources[0x44]	16681	1			T1	194		T21	1		T27	1
valid_sources[0x45]	15544	1			T6	1		T1	141		T5	1
valid_sources[0x46]	16495	1			T1	189		T5	8		T26	1
valid_sources[0x47]	16091	1			T29	1		T1	193		T5	2
valid_sources[0x48]	15972	1			T9	1		T1	159		T5	2
valid_sources[0x49]	18041	1			T8	1		T1	174		T20	1
valid_sources[0x4a]	16583	1			T7	4		T1	186		T5	1
valid_sources[0x4b]	15235	1			T7	3		T29	1		T1	161
valid_sources[0x4c]	17113	1			T7	1		T8	1		T42	1
valid_sources[0x4d]	15367	1			T32	2		T6	2		T1	144
valid_sources[0x4e]	17303	1			T42	1		T1	148		T5	3
valid_sources[0x4f]	15510	1			T8	1		T30	1		T6	1
valid_sources[0x50]	16682	1			T6	3		T40	1		T1	173
valid_sources[0x51]	15773	1			T8	1		T1	141		T5	3
valid_sources[0x52]	16039	1			T29	5		T6	1		T1	172
valid_sources[0x53]	16461	1			T41	1		T1	209		T53	1
valid_sources[0x54]	15929	1			T38	1		T1	205		T5	3
valid_sources[0x55]	16074	1			T7	5		T1	148		T5	4
valid_sources[0x56]	16359	1			T29	2		T1	205		T5	4
valid_sources[0x57]	16666	1			T6	2		T1	140		T5	2
valid_sources[0x58]	15117	1			T42	1		T1	154		T5	5
valid_sources[0x59]	15740	1			T1	156		T5	1		T2	186
valid_sources[0x5a]	20082	1			T9	1		T6	1		T1	176
valid_sources[0x5b]	16045	1			T1	163		T5	1		T2	470
valid_sources[0x5c]	16456	1			T32	3		T6	1		T38	1
valid_sources[0x5d]	17353	1			T1	171		T5	3		T55	1
valid_sources[0x5e]	15243	1			T6	3		T1	182		T21	1
valid_sources[0x5f]	17005	1			T40	1		T1	128		T5	1
valid_sources[0x60]	15569	1			T8	1		T6	2		T42	1
valid_sources[0x61]	16575	1			T6	1		T39	1		T40	3
valid_sources[0x62]	16161	1			T1	196		T20	1		T5	7
valid_sources[0x63]	15998	1			T39	1		T40	2		T1	149
valid_sources[0x64]	15644	1			T7	1		T6	1		T1	134
valid_sources[0x65]	15551	1			T8	1		T30	1		T41	1
valid_sources[0x66]	14913	1			T41	1		T1	121		T26	1
valid_sources[0x67]	15915	1			T6	2		T41	2		T1	191
valid_sources[0x68]	15071	1			T30	1		T42	1		T1	156
valid_sources[0x69]	16044	1			T32	2		T41	1		T1	188
valid_sources[0x6a]	15916	1			T30	1		T40	1		T42	1
valid_sources[0x6b]	16574	1			T1	148		T5	2		T2	382
valid_sources[0x6c]	15396	1			T9	1		T38	2		T39	1
valid_sources[0x6d]	14805	1			T42	2		T1	132		T5	9
valid_sources[0x6e]	15911	1			T1	196		T5	11		T2	320
valid_sources[0x6f]	15493	1			T7	3		T8	1		T38	2
valid_sources[0x70]	15847	1			T38	1		T1	180		T5	2
valid_sources[0x71]	15092	1			T6	2		T39	2		T1	135
valid_sources[0x72]	17111	1			T6	1		T38	4		T1	223
valid_sources[0x73]	15909	1			T1	175		T5	1		T2	342
valid_sources[0x74]	15693	1			T6	1		T1	163		T5	3
valid_sources[0x75]	17070	1			T29	3		T42	1		T1	210
valid_sources[0x76]	16200	1			T42	1		T1	194		T21	1
valid_sources[0x77]	15018	1			T6	2		T40	2		T1	148
valid_sources[0x78]	17706	1			T1	155		T5	4		T26	5
valid_sources[0x79]	17073	1			T7	2		T1	166		T5	2
valid_sources[0x7a]	17936	1			T32	1		T6	1		T1	171
valid_sources[0x7b]	15490	1			T6	1		T39	1		T42	2
valid_sources[0x7c]	17369	1			T7	4		T31	3		T6	2
valid_sources[0x7d]	15711	1			T6	2		T1	147		T5	4
valid_sources[0x7e]	15628	1			T6	1		T42	1		T1	158
valid_sources[0x7f]	15691	1			T1	169		T21	1		T2	141
valid_sources[0x80]	16391	1			T1	177		T5	1		T53	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

888389

1

T7

30

T8

8

T9

2

values[0x0]

all_enables

biggest_size

1339138

1

T7

6

T8

6

T28

4

values[0x1]

all_enables

biggest_size

1296583

1

T7

4

T9

1

T28

2