Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	789874115	79445	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789874115	79445	0	0
T1	659070	312	0	0
T2	0	752	0	0
T3	0	206	0	0
T5	261590	0	0	0
T13	0	447	0	0
T14	0	1337	0	0
T15	0	188	0	0
T16	0	412	0	0
T17	0	364	0	0
T18	0	149	0	0
T19	0	226	0	0
T20	7235	0	0	0
T21	8710	0	0	0
T22	8620	0	0	0
T23	4535	0	0	0
T24	620690	0	0	0
T25	3840	0	0	0
T26	10670	0	0	0
T27	73345	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157974823	11461	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157974823	11461	0	0
T1	131814	41	0	0
T2	0	100	0	0
T3	0	34	0	0
T5	52318	0	0	0
T13	0	62	0	0
T14	0	197	0	0
T15	0	28	0	0
T16	0	79	0	0
T17	0	59	0	0
T18	0	21	0	0
T19	0	36	0	0
T20	1447	0	0	0
T21	1742	0	0	0
T22	1724	0	0	0
T23	907	0	0	0
T24	124138	0	0	0
T25	768	0	0	0
T26	2134	0	0	0
T27	14669	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157974823	15932	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157974823	15932	0	0
T1	131814	62	0	0
T2	0	152	0	0
T3	0	42	0	0
T5	52318	0	0	0
T13	0	91	0	0
T14	0	269	0	0
T15	0	38	0	0
T16	0	79	0	0
T17	0	72	0	0
T18	0	30	0	0
T19	0	46	0	0
T20	1447	0	0	0
T21	1742	0	0	0
T22	1724	0	0	0
T23	907	0	0	0
T24	124138	0	0	0
T25	768	0	0	0
T26	2134	0	0	0
T27	14669	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157974823	24756	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157974823	24756	0	0
T1	131814	105	0	0
T2	0	250	0	0
T3	0	56	0	0
T5	52318	0	0	0
T13	0	141	0	0
T14	0	442	0	0
T15	0	61	0	0
T16	0	96	0	0
T17	0	101	0	0
T18	0	47	0	0
T19	0	62	0	0
T20	1447	0	0	0
T21	1742	0	0	0
T22	1724	0	0	0
T23	907	0	0	0
T24	124138	0	0	0
T25	768	0	0	0
T26	2134	0	0	0
T27	14669	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157974823	11274	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157974823	11274	0	0
T1	131814	41	0	0
T2	0	99	0	0
T3	0	33	0	0
T5	52318	0	0	0
T13	0	62	0	0
T14	0	166	0	0
T15	0	23	0	0
T16	0	79	0	0
T17	0	58	0	0
T18	0	21	0	0
T19	0	36	0	0
T20	1447	0	0	0
T21	1742	0	0	0
T22	1724	0	0	0
T23	907	0	0	0
T24	124138	0	0	0
T25	768	0	0	0
T26	2134	0	0	0
T27	14669	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	157974823	16022	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157974823	16022	0	0
T1	131814	63	0	0
T2	0	151	0	0
T3	0	41	0	0
T5	52318	0	0	0
T13	0	91	0	0
T14	0	263	0	0
T15	0	38	0	0
T16	0	79	0	0
T17	0	74	0	0
T18	0	30	0	0
T19	0	46	0	0
T20	1447	0	0	0
T21	1742	0	0	0
T22	1724	0	0	0
T23	907	0	0	0
T24	124138	0	0	0
T25	768	0	0	0
T26	2134	0	0	0
T27	14669	0	0	0