Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T5

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	157974823	155135028	0	0
AllClkBypReqTrue_A	157974823	126339	0	0
IoClkBypReqFalse_A	157974823	155055644	0	2415
IoClkBypReqTrue_A	157974823	201103	0	0
LcClkBypAckFalse_A	157974823	155141466	0	0
LcClkBypAckTrue_A	157974823	119901	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157974823	155135028	0	0
T6	6720	6700	0	0
T7	3508	3338	0	0
T8	1927	1761	0	0
T9	914	891	0	0
T28	2057	1873	0	0
T29	2435	2070	0	0
T30	1424	1197	0	0
T31	1421	1354	0	0
T32	1607	1387	0	0
T33	1626	1588	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157974823	126339	0	0
T1	0	352	0	0
T4	26720	0	0	0
T6	6720	0	0	0
T8	1927	65	0	0
T9	914	0	0	0
T20	0	38	0	0
T22	0	243	0	0
T28	2057	0	0	0
T29	2435	360	0	0
T30	1424	0	0	0
T31	1421	40	0	0
T32	1607	0	0	0
T33	1626	0	0	0
T38	0	72	0	0
T42	0	110	0	0
T54	0	26	0	0
T56	0	354	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157974823	155055644	0	2415
T6	6720	6698	0	3
T7	3508	3336	0	3
T8	1927	1611	0	3
T9	914	889	0	3
T28	2057	1871	0	3
T29	2435	1885	0	3
T30	1424	1195	0	3
T31	1421	1109	0	3
T32	1607	1385	0	3
T33	1626	1346	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157974823	201103	0	0
T1	0	738	0	0
T4	26720	0	0	0
T6	6720	0	0	0
T8	1927	213	0	0
T9	914	0	0	0
T20	0	229	0	0
T28	2057	0	0	0
T29	2435	543	0	0
T30	1424	0	0	0
T31	1421	283	0	0
T32	1607	0	0	0
T33	1626	240	0	0
T38	0	325	0	0
T39	0	118	0	0
T40	0	262	0	0
T42	0	312	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157974823	155141466	0	0
T6	6720	6700	0	0
T7	3508	3338	0	0
T8	1927	1749	0	0
T9	914	891	0	0
T28	2057	1873	0	0
T29	2435	2121	0	0
T30	1424	1197	0	0
T31	1421	1305	0	0
T32	1607	1387	0	0
T33	1626	1506	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157974823	119901	0	0
T1	0	315	0	0
T4	26720	0	0	0
T6	6720	0	0	0
T8	1927	77	0	0
T9	914	0	0	0
T20	0	119	0	0
T28	2057	0	0	0
T29	2435	309	0	0
T30	1424	0	0	0
T31	1421	89	0	0
T32	1607	0	0	0
T33	1626	82	0	0
T38	0	188	0	0
T39	0	50	0	0
T40	0	168	0	0
T42	0	211	0	0