Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1468867256	14680	0	0
TransStop_A	1468867256	7597	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468867256	14680	0	0
T1	0	72	0	0
T2	0	105	0	0
T6	268840	0	0	0
T7	14036	32	0	0
T8	11864	0	0	0
T9	13544	3	0	0
T26	0	26	0	0
T28	8232	12	0	0
T29	194908	0	0	0
T30	5700	0	0	0
T31	24708	0	0	0
T32	6628	0	0	0
T33	27112	0	0	0
T37	0	4	0	0
T41	0	11	0	0
T59	0	22	0	0
T101	0	8	0	0
T102	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468867256	7597	0	0
T1	0	28	0	0
T2	0	57	0	0
T6	268840	0	0	0
T7	14036	16	0	0
T8	11864	0	0	0
T9	13544	3	0	0
T26	0	17	0	0
T28	8232	5	0	0
T29	194908	0	0	0
T30	5700	0	0	0
T31	24708	0	0	0
T32	6628	0	0	0
T33	27112	0	0	0
T37	0	4	0	0
T41	0	3	0	0
T59	0	16	0	0
T101	0	8	0	0
T102	0	1	0	0
T103	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	367216814	3678	0	0
TransStop_A	367216814	1882	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216814	3678	0	0
T1	0	21	0	0
T2	0	22	0	0
T6	67210	0	0	0
T7	3509	6	0	0
T8	2966	0	0	0
T9	3386	1	0	0
T26	0	6	0	0
T28	2058	4	0	0
T29	48727	0	0	0
T30	1425	0	0	0
T31	6177	0	0	0
T32	1657	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	3	0	0
T59	0	6	0	0
T101	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216814	1882	0	0
T1	0	11	0	0
T2	0	11	0	0
T6	67210	0	0	0
T7	3509	3	0	0
T8	2966	0	0	0
T9	3386	1	0	0
T26	0	4	0	0
T28	2058	1	0	0
T29	48727	0	0	0
T30	1425	0	0	0
T31	6177	0	0	0
T32	1657	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T59	0	5	0	0
T101	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	367216814	3715	0	0
TransStop_A	367216814	1923	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216814	3715	0	0
T1	0	18	0	0
T2	0	21	0	0
T6	67210	0	0	0
T7	3509	11	0	0
T8	2966	0	0	0
T9	3386	1	0	0
T26	0	5	0	0
T28	2058	3	0	0
T29	48727	0	0	0
T30	1425	0	0	0
T31	6177	0	0	0
T32	1657	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	3	0	0
T59	0	4	0	0
T101	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216814	1923	0	0
T1	0	6	0	0
T2	0	15	0	0
T6	67210	0	0	0
T7	3509	6	0	0
T8	2966	0	0	0
T9	3386	1	0	0
T26	0	4	0	0
T28	2058	2	0	0
T29	48727	0	0	0
T30	1425	0	0	0
T31	6177	0	0	0
T32	1657	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T59	0	3	0	0
T101	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	367216814	3642	0	0
TransStop_A	367216814	1878	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216814	3642	0	0
T1	0	16	0	0
T2	0	30	0	0
T6	67210	0	0	0
T7	3509	7	0	0
T8	2966	0	0	0
T9	3386	0	0	0
T26	0	6	0	0
T28	2058	3	0	0
T29	48727	0	0	0
T30	1425	0	0	0
T31	6177	0	0	0
T32	1657	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	2	0	0
T59	0	5	0	0
T101	0	2	0	0
T102	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216814	1878	0	0
T1	0	5	0	0
T2	0	14	0	0
T6	67210	0	0	0
T7	3509	1	0	0
T8	2966	0	0	0
T9	3386	0	0	0
T26	0	3	0	0
T28	2058	1	0	0
T29	48727	0	0	0
T30	1425	0	0	0
T31	6177	0	0	0
T32	1657	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T59	0	3	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	367216814	3645	0	0
TransStop_A	367216814	1914	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216814	3645	0	0
T1	0	17	0	0
T2	0	32	0	0
T6	67210	0	0	0
T7	3509	8	0	0
T8	2966	0	0	0
T9	3386	1	0	0
T26	0	9	0	0
T28	2058	2	0	0
T29	48727	0	0	0
T30	1425	0	0	0
T31	6177	0	0	0
T32	1657	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	3	0	0
T59	0	7	0	0
T101	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216814	1914	0	0
T1	0	6	0	0
T2	0	17	0	0
T6	67210	0	0	0
T7	3509	6	0	0
T8	2966	0	0	0
T9	3386	1	0	0
T26	0	6	0	0
T28	2058	1	0	0
T29	48727	0	0	0
T30	1425	0	0	0
T31	6177	0	0	0
T32	1657	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T59	0	5	0	0
T101	0	2	0	0