Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10CoveredT8,T29,T31 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT8,T29,T31
11CoveredT8,T29,T31 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT8,T29,T31
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 425626431 425624016 0 0
selKnown1 1027633764 1027631349 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 425626431 425624016 0 0
T6 66183 66180 0 0
T7 4145 4142 0 0
T8 3600 3597 0 0
T9 4015 4012 0 0
T28 2422 2419 0 0
T29 64026 64023 0 0
T30 1558 1555 0 0
T31 7642 7639 0 0
T32 1872 1869 0 0
T33 8380 8377 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027633764 1027631349 0 0
T6 158997 158994 0 0
T7 10104 10101 0 0
T8 8544 8541 0 0
T9 9750 9747 0 0
T28 5925 5922 0 0
T29 140328 140325 0 0
T30 4101 4098 0 0
T31 17790 17787 0 0
T32 4770 4767 0 0
T33 19521 19518 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 170344332 170343527 0 0
selKnown1 342544588 342543783 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 170344332 170343527 0 0
T6 26473 26472 0 0
T7 1658 1657 0 0
T8 1473 1472 0 0
T9 1606 1605 0 0
T28 969 968 0 0
T29 27116 27115 0 0
T30 623 622 0 0
T31 3140 3139 0 0
T32 749 748 0 0
T33 3426 3425 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 342544588 342543783 0 0
T6 52999 52998 0 0
T7 3368 3367 0 0
T8 2848 2847 0 0
T9 3250 3249 0 0
T28 1975 1974 0 0
T29 46776 46775 0 0
T30 1367 1366 0 0
T31 5930 5929 0 0
T32 1590 1589 0 0
T33 6507 6506 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10CoveredT8,T29,T31 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT8,T29,T31
11CoveredT8,T29,T31 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT8,T29,T31
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 170110534 170109729 0 0
selKnown1 342544588 342543783 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 170110534 170109729 0 0
T6 26473 26472 0 0
T7 1658 1657 0 0
T8 1391 1390 0 0
T9 1606 1605 0 0
T28 969 968 0 0
T29 23355 23354 0 0
T30 623 622 0 0
T31 2932 2931 0 0
T32 749 748 0 0
T33 3241 3240 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 342544588 342543783 0 0
T6 52999 52998 0 0
T7 3368 3367 0 0
T8 2848 2847 0 0
T9 3250 3249 0 0
T28 1975 1974 0 0
T29 46776 46775 0 0
T30 1367 1366 0 0
T31 5930 5929 0 0
T32 1590 1589 0 0
T33 6507 6506 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 85171565 85170760 0 0
selKnown1 342544588 342543783 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 85171565 85170760 0 0
T6 13237 13236 0 0
T7 829 828 0 0
T8 736 735 0 0
T9 803 802 0 0
T28 484 483 0 0
T29 13555 13554 0 0
T30 312 311 0 0
T31 1570 1569 0 0
T32 374 373 0 0
T33 1713 1712 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 342544588 342543783 0 0
T6 52999 52998 0 0
T7 3368 3367 0 0
T8 2848 2847 0 0
T9 3250 3249 0 0
T28 1975 1974 0 0
T29 46776 46775 0 0
T30 1367 1366 0 0
T31 5930 5929 0 0
T32 1590 1589 0 0
T33 6507 6506 0 0

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