Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	157974823	22036377	0	60

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157974823	22036377	0	60
T1	131814	365318	0	0
T2	0	784067	0	0
T3	0	13139	0	1
T5	52318	0	0	0
T13	0	40690	0	0
T14	0	806417	0	0
T15	0	24327	0	1
T16	0	13468	0	0
T17	0	24888	0	0
T18	0	12494	0	0
T19	0	0	0	1
T20	1447	0	0	0
T21	1742	0	0	0
T22	1724	0	0	0
T23	907	0	0	0
T24	124138	0	0	0
T25	768	0	0	0
T26	2134	0	0	0
T27	14669	0	0	0
T34	0	823	0	0
T128	0	0	0	1
T129	0	0	0	1
T130	0	0	0	1
T131	0	0	0	1
T132	0	0	0	1
T133	0	0	0	1
T134	0	0	0	1